From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hqXvE-00037D-WA for mharc-qemu-riscv@gnu.org; Thu, 25 Jul 2019 03:12:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54323) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXvC-000374-M8 for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 03:12:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqXvB-0006MD-Db for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 03:12:14 -0400 Received: from smtpe1.intersmtp.com ([62.239.224.234]:18705) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqXvB-0006KM-2D; Thu, 25 Jul 2019 03:12:13 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by RDW083A012ED68.bt.com (10.187.98.38) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 08:11:32 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 08:12:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 08:12:10 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit Thread-Index: AQHVQrhGgJTlyfNcZkCelTTHDacpvA== Date: Thu, 25 Jul 2019 07:12:10 +0000 Message-ID: <1564038730242.51356@bt.com> References: , <1563810716254.18886@bt.com>,<1564038073754.91133@bt.com> In-Reply-To: <1564038073754.91133@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_156403873024251356btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.234 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jul 2019 07:12:16 -0000 --_000_156403873024251356btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This bit configures endianness of PCI MMIO devices. It is used by Solaris and OpenBSD sunhme drivers. Tested working on OpenBSD. Unfortunately Solaris 10 had a unrelated keyboard issue blocking testing... another inch towards Solaris 10 on SPARC64 =3D) Signed-off-by: Tony Nguyen --- target/sparc/cpu.h | 2 ++ target/sparc/mmu_helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250..77e8e07 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -277,6 +277,7 @@ enum { #define TTE_VALID_BIT (1ULL << 63) #define TTE_NFO_BIT (1ULL << 60) +#define TTE_IE_BIT (1ULL << 59) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) #define TTE_SIDEEFFECT_BIT (1ULL << 3) @@ -293,6 +294,7 @@ enum { #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) +#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 826e14b..77dc86a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { int do_fault =3D 0; + if (TTE_IS_IE(env->dtlb[i].tte)) { + attrs->byte_swap =3D true; + } + /* access ok? */ /* multiple bits in SFSR.FT may be set on TT_DFAULT */ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { @@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env) } if (TTE_IS_VALID(env->dtlb[i].tte)) { qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", + ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n= ", i, env->dtlb[i].tag & (uint64_t)~0x1fffULL, TTE_PA(env->dtlb[i].tte), @@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env) TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", TTE_IS_LOCKED(env->dtlb[i].tte) ? "locked" : "unlocked", + TTE_IS_IE(env->dtlb[i].tte) ? + "yes" : "no", env->dtlb[i].tag & (uint64_t)0x1fffULL, TTE_IS_GLOBAL(env->dtlb[i].tte) ? "global" : "local"); -- 1.8.3.1 --_000_156403873024251356btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

This bit configures endianness of PCI= MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.

Tested working on OpenBSD.

Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =3D)

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 target/sparc/cpu.h        | 2 ++
 target/sparc/mmu_helper.c | 8 +++++++= ;-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 8ed2250..77e8e07 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -277,6 +277,7 @@ enum {
 
 #define TTE_VALID_BIT       (1ULL << 63)
 #define TTE_NFO_BIT         (1ULL << 6= 0)
+#define TTE_IE_BIT          (1ULL <&l= t; 59)
 #define TTE_USED_BIT        (1ULL << 4= 1)
 #define TTE_LOCKED_BIT      (1ULL <<  = 6)
 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
@@ -293,6 +294,7 @@ enum {
 
 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)<= /div>
+#define TTE_IS_IE(tte)      ((tte) & TTE_IE_BI= T)
 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)=
 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)<= /div>
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 826e14b..77dc86a 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARC= State *env, hwaddr *physical,
         if (ultrasparc_tag_match(&env-&g= t;dtlb[i], address, context, physical)) {
             int do_fault =3D 0;
 
+            if (TTE_IS_IE(env->d= tlb[i].tte)) {
+                attrs->= ;byte_swap =3D true;
+            }
+
             /* access ok? */
             /* multiple bits in SF= SR.FT may be set on TT_DFAULT */
             if (TTE_IS_PRIV(env-&g= t;dtlb[i].tte) && is_user) {
@@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env)
             }
             if (TTE_IS_VALID(env-&= gt;dtlb[i].tte)) {
                 qemu_pri= ntf("[%02u] VA: %" PRIx64 ", PA: %llx"
-                    = ;        ", %s, %s, %s, %s, ctx %" PRId64 &qu= ot; %s\n",
+                   &= nbsp;        ", %s, %s, %s, %s, ie %s, ctx %"= PRId64 " %s\n",
                    =          i,
                    =          env->dtlb[i].tag & (uint64_t)~0x1f= ffULL,
                    =          TTE_PA(env->dtlb[i].tte),
@@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env)
                    =          TTE_IS_W_OK(env->dtlb[i].tte) ? "= RW" : "RO",
                    =          TTE_IS_LOCKED(env->dtlb[i].tte) ?
                    =          "locked" : "unlocked"= ,
+                   &= nbsp;        TTE_IS_IE(env->dtlb[i].tte) ?
+                   &= nbsp;        "yes" : "no",
                    =          env->dtlb[i].tag & (uint64_t)0x1ff= fULL,
                    =          TTE_IS_GLOBAL(env->dtlb[i].tte) ?
                    =          "global" : "local");<= /div>
-- 
1.8.3.1



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[209.51.188.17]) by mx.google.com with ESMTPS id l53si11022780edd.293.2019.07.25.00.12.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jul 2019 00:12:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=bt.com Received: from localhost ([::1]:56412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXvL-0003Bi-JW for alex.bennee@linaro.org; Thu, 25 Jul 2019 03:12:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54385) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXvH-000394-Qi for qemu-arm@nongnu.org; Thu, 25 Jul 2019 03:12:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqXvG-0006Tj-JE for qemu-arm@nongnu.org; Thu, 25 Jul 2019 03:12:19 -0400 Received: from smtpe1.intersmtp.com ([62.239.224.234]:18705) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqXvB-0006KM-2D; Thu, 25 Jul 2019 03:12:13 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by RDW083A012ED68.bt.com (10.187.98.38) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 08:11:32 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 08:12:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 08:12:10 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit Thread-Index: AQHVQrhGgJTlyfNcZkCelTTHDacpvA== Date: Thu, 25 Jul 2019 07:12:10 +0000 Message-ID: <1564038730242.51356@bt.com> References: , <1563810716254.18886@bt.com>,<1564038073754.91133@bt.com> In-Reply-To: <1564038073754.91133@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_156403873024251356btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.234 Subject: [Qemu-arm] [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, alex.williamson@redhat.com, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: y9iiYdOt8N5/ --_000_156403873024251356btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This bit configures endianness of PCI MMIO devices. It is used by Solaris and OpenBSD sunhme drivers. Tested working on OpenBSD. Unfortunately Solaris 10 had a unrelated keyboard issue blocking testing... another inch towards Solaris 10 on SPARC64 =3D) Signed-off-by: Tony Nguyen --- target/sparc/cpu.h | 2 ++ target/sparc/mmu_helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250..77e8e07 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -277,6 +277,7 @@ enum { #define TTE_VALID_BIT (1ULL << 63) #define TTE_NFO_BIT (1ULL << 60) +#define TTE_IE_BIT (1ULL << 59) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) #define TTE_SIDEEFFECT_BIT (1ULL << 3) @@ -293,6 +294,7 @@ enum { #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) +#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 826e14b..77dc86a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { int do_fault =3D 0; + if (TTE_IS_IE(env->dtlb[i].tte)) { + attrs->byte_swap =3D true; + } + /* access ok? */ /* multiple bits in SFSR.FT may be set on TT_DFAULT */ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { @@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env) } if (TTE_IS_VALID(env->dtlb[i].tte)) { qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", + ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n= ", i, env->dtlb[i].tag & (uint64_t)~0x1fffULL, TTE_PA(env->dtlb[i].tte), @@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env) TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", TTE_IS_LOCKED(env->dtlb[i].tte) ? "locked" : "unlocked", + TTE_IS_IE(env->dtlb[i].tte) ? + "yes" : "no", env->dtlb[i].tag & (uint64_t)0x1fffULL, TTE_IS_GLOBAL(env->dtlb[i].tte) ? "global" : "local"); -- 1.8.3.1 --_000_156403873024251356btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

This bit configures endianness of PCI= MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.

Tested working on OpenBSD.

Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =3D)

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 target/sparc/cpu.h        | 2 ++
 target/sparc/mmu_helper.c | 8 +++++++= ;-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 8ed2250..77e8e07 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -277,6 +277,7 @@ enum {
 
 #define TTE_VALID_BIT       (1ULL << 63)
 #define TTE_NFO_BIT         (1ULL << 6= 0)
+#define TTE_IE_BIT          (1ULL <&l= t; 59)
 #define TTE_USED_BIT        (1ULL << 4= 1)
 #define TTE_LOCKED_BIT      (1ULL <<  = 6)
 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
@@ -293,6 +294,7 @@ enum {
 
 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)<= /div>
+#define TTE_IS_IE(tte)      ((tte) & TTE_IE_BI= T)
 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)=
 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)<= /div>
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 826e14b..77dc86a 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARC= State *env, hwaddr *physical,
         if (ultrasparc_tag_match(&env-&g= t;dtlb[i], address, context, physical)) {
             int do_fault =3D 0;
 
+            if (TTE_IS_IE(env->d= tlb[i].tte)) {
+                attrs->= ;byte_swap =3D true;
+            }
+
             /* access ok? */
             /* multiple bits in SF= SR.FT may be set on TT_DFAULT */
             if (TTE_IS_PRIV(env-&g= t;dtlb[i].tte) && is_user) {
@@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env)
             }
             if (TTE_IS_VALID(env-&= gt;dtlb[i].tte)) {
                 qemu_pri= ntf("[%02u] VA: %" PRIx64 ", PA: %llx"
-                    = ;        ", %s, %s, %s, %s, ctx %" PRId64 &qu= ot; %s\n",
+                   &= nbsp;        ", %s, %s, %s, %s, ie %s, ctx %"= PRId64 " %s\n",
                    =          i,
                    =          env->dtlb[i].tag & (uint64_t)~0x1f= ffULL,
                    =          TTE_PA(env->dtlb[i].tte),
@@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env)
                    =          TTE_IS_W_OK(env->dtlb[i].tte) ? "= RW" : "RO",
                    =          TTE_IS_LOCKED(env->dtlb[i].tte) ?
                    =          "locked" : "unlocked"= ,
+                   &= nbsp;        TTE_IS_IE(env->dtlb[i].tte) ?
+                   &= nbsp;        "yes" : "no",
                    =          env->dtlb[i].tag & (uint64_t)0x1ff= fULL,
                    =          TTE_IS_GLOBAL(env->dtlb[i].tte) ?
                    =          "global" : "local");<= /div>
-- 
1.8.3.1



--_000_156403873024251356btcom_-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08E9BC7618B for ; Thu, 25 Jul 2019 07:12:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D310120840 for ; Thu, 25 Jul 2019 07:12:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D310120840 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bt.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXvW-0003ml-59 for qemu-devel@archiver.kernel.org; Thu, 25 Jul 2019 03:12:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54412) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXvK-0003CM-I7 for qemu-devel@nongnu.org; Thu, 25 Jul 2019 03:12:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqXvJ-0006Wj-9M for qemu-devel@nongnu.org; Thu, 25 Jul 2019 03:12:22 -0400 Received: from smtpe1.intersmtp.com ([62.239.224.234]:18705) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqXvB-0006KM-2D; Thu, 25 Jul 2019 03:12:13 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by RDW083A012ED68.bt.com (10.187.98.38) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 08:11:32 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 08:12:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 08:12:10 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit Thread-Index: AQHVQrhGgJTlyfNcZkCelTTHDacpvA== Date: Thu, 25 Jul 2019 07:12:10 +0000 Message-ID: <1564038730242.51356@bt.com> References: , <1563810716254.18886@bt.com>,<1564038073754.91133@bt.com> In-Reply-To: <1564038073754.91133@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.234 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, alex.williamson@redhat.com, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This bit configures endianness of PCI MMIO devices. It is used by Solaris and OpenBSD sunhme drivers. Tested working on OpenBSD. Unfortunately Solaris 10 had a unrelated keyboard issue blocking testing... another inch towards Solaris 10 on SPARC64 =3D) Signed-off-by: Tony Nguyen --- target/sparc/cpu.h | 2 ++ target/sparc/mmu_helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250..77e8e07 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -277,6 +277,7 @@ enum { #define TTE_VALID_BIT (1ULL << 63) #define TTE_NFO_BIT (1ULL << 60) +#define TTE_IE_BIT (1ULL << 59) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) #define TTE_SIDEEFFECT_BIT (1ULL << 3) @@ -293,6 +294,7 @@ enum { #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) +#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 826e14b..77dc86a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { int do_fault =3D 0; + if (TTE_IS_IE(env->dtlb[i].tte)) { + attrs->byte_swap =3D true; + } + /* access ok? */ /* multiple bits in SFSR.FT may be set on TT_DFAULT */ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { @@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env) } if (TTE_IS_VALID(env->dtlb[i].tte)) { qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", + ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n= ", i, env->dtlb[i].tag & (uint64_t)~0x1fffULL, TTE_PA(env->dtlb[i].tte), @@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env) TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", TTE_IS_LOCKED(env->dtlb[i].tte) ? "locked" : "unlocked", + TTE_IS_IE(env->dtlb[i].tte) ? + "yes" : "no", env->dtlb[i].tag & (uint64_t)0x1fffULL, TTE_IS_GLOBAL(env->dtlb[i].tte) ? "global" : "local"); -- 1.8.3.1