From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hqYkn-00016C-8j for mharc-qemu-riscv@gnu.org; Thu, 25 Jul 2019 04:05:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38441) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqYkj-0000sJ-Ts for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 04:05:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqYki-0003dw-JJ for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 04:05:29 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.72]:55312) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqYkc-0003Y7-T9; Thu, 25 Jul 2019 04:05:23 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926077.bt.com (10.36.82.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 09:05:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 09:05:17 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 09:05:17 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path Thread-Index: AQHVQr+y/H9707CquU6/1OwIMKzlIg== Date: Thu, 25 Jul 2019 08:05:17 +0000 Message-ID: <1564041917034.8581@bt.com> References: , <1563810716254.18886@bt.com>, <1564038073754.91133@bt.com>, <1564041524365.23360@bt.com> In-Reply-To: <1564041524365.23360@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_15640419170348581btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jul 2019 08:05:31 -0000 --_000_15640419170348581btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable The fast path is taken when TLB_FLAGS_MASK is all zero. TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path, there are no other side effects. Signed-off-by: Tony Nguyen --- include/exec/cpu-all.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58..e496f99 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) /* Set if TLB entry must have MMU lookup repeated for every access */ #define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) +/* Set if TLB entry must take the slow path. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK \ + | TLB_NOTDIRTY \ + | TLB_MMIO \ + | TLB_RECHECK \ + | TLB_FORCE_SLOW) /** * tlb_hit_page: return true if page aligned @addr is a hit against the -- 1.8.3.1 --_000_15640419170348581btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

The fast path is taken when TLB_FLAGS= _MASK is all zero.

TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,<= /div>
there are no other side effects.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 include/exec/cpu-all.h | 10 +++++++&= #43;--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 536ea58..e496f99 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
 #define TLB_MMIO            (1 <= ;< (TARGET_PAGE_BITS - 3))
 /* Set if TLB entry must have MMU lookup repeated for every acce= ss */
 #define TLB_RECHECK         (1 << (TAR= GET_PAGE_BITS - 4))
+/* Set if TLB entry must take the slow path.  */
+#define TLB_FORCE_SLOW      (1 << (TARGET_PA= GE_BITS - 5))
 
 /* Use this mask to check interception with an alignment mask
  * in a TCG backend.
  */
-#define TLB_FLAGS_MASK  (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_M= MIO \
-                    = ;     | TLB_RECHECK)
+#define TLB_FLAGS_MASK \
+    (TLB_INVALID_MASK  \
+     | TLB_NOTDIRTY    \
+     | TLB_MMIO        \
+     | TLB_RECHECK     \
+     | TLB_FORCE_SLOW)
 
 /**
  * tlb_hit_page: return true if page aligned @addr is a hit agai= nst the
-- 
1.8.3.1



--_000_15640419170348581btcom_-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 2002:a5d:51d0:0:0:0:0:0 with SMTP id n16csp10324294wrv; Thu, 25 Jul 2019 01:05:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqzQwWev4oUOa5Y0ZgaRhHqpsZzqpHty2byCkXg3CktwNFYg5ecz1VQ2W6pHCUftYXTcoUZd X-Received: by 2002:ac8:f8c:: with SMTP id b12mr62227769qtk.381.1564041936510; Thu, 25 Jul 2019 01:05:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564041936; cv=none; d=google.com; s=arc-20160816; b=o0IZIActELTXJdHWMjhWEqw/M5ztYOoI+mCRWDCcc+R6ogezrNG2sKiX7uiExuKmkE Nud4l065EOZrAUUGzE+PfGbspmcyZ+RJJRMaHRZId4xGSYiMW+t8aQLys0JVj1boFQuS MYFsfr9tTXfv+CcrTLxNhDu341ZZGY0OeqyFj82TzPiwop3gscIuXxL+8fR91uhxEasZ rNdM1TL4khGkdP+m8J/Z1jp7cOglLGypDC7L0bEhRlxC5t3vBRcTowBQQ0pnfuU7OuSr pd9KIDIWF5JeNW5NCOsygCIOmqRZsKBVbaID6lW3isnEGNsEXF/jQ/gm0f4M4waII/ap Xihw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:mime-version :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:to:from; bh=z8b5lG87XNhYZivcwOq20N/n8a13ZY5uE341G86mW0Y=; b=cbFkDQ/2CEwfFa4STg1DJJLqaeZFcu//4U7cFf8oxxFIwd18UTPt4Q67QFnGKJoucB G0B6QcJG0wDVb3/EtxDQKOZQAFVosdMXFs+5u06FTeSlersmp9DHf65zXLcpBgmqLHDK oBlZ2yv0uzfW3Y5CgwTDxzhXLHdw76KCooHF7cDtzqNpA4FhIP5kDi6iLcJG8VwF/6IN HUx/JXG7uWuQfRn/NU0UHGsdmgNoPY6f9CkoH/Gyy0Irl0+XD6FBTqkEijwaeSkXMovJ 37b9DxjzTvO0a6ElI5W/BGOkIOlUzNu/iZ68EF44X9wKiS6TbsTTzzVbzgHaym55N+nP 6RrA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=bt.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8si3598481qtu.149.2019.07.25.01.05.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jul 2019 01:05:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=bt.com Received: from localhost ([::1]:56870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqYkq-0001Az-2a for alex.bennee@linaro.org; Thu, 25 Jul 2019 04:05:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38457) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqYkm-00011r-53 for qemu-arm@nongnu.org; Thu, 25 Jul 2019 04:05:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqYkk-0003fe-W9 for qemu-arm@nongnu.org; Thu, 25 Jul 2019 04:05:32 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.72]:55312) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqYkc-0003Y7-T9; Thu, 25 Jul 2019 04:05:23 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926077.bt.com (10.36.82.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 09:05:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 09:05:17 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 09:05:17 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path Thread-Index: AQHVQr+y/H9707CquU6/1OwIMKzlIg== Date: Thu, 25 Jul 2019 08:05:17 +0000 Message-ID: <1564041917034.8581@bt.com> References: , <1563810716254.18886@bt.com>, <1564038073754.91133@bt.com>, <1564041524365.23360@bt.com> In-Reply-To: <1564041524365.23360@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_15640419170348581btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Subject: [Qemu-arm] [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: WP0zEUe1Ak82 --_000_15640419170348581btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable The fast path is taken when TLB_FLAGS_MASK is all zero. TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path, there are no other side effects. Signed-off-by: Tony Nguyen --- include/exec/cpu-all.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58..e496f99 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) /* Set if TLB entry must have MMU lookup repeated for every access */ #define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) +/* Set if TLB entry must take the slow path. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK \ + | TLB_NOTDIRTY \ + | TLB_MMIO \ + | TLB_RECHECK \ + | TLB_FORCE_SLOW) /** * tlb_hit_page: return true if page aligned @addr is a hit against the -- 1.8.3.1 --_000_15640419170348581btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

The fast path is taken when TLB_FLAGS= _MASK is all zero.

TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,<= /div>
there are no other side effects.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 include/exec/cpu-all.h | 10 +++++++&= #43;--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 536ea58..e496f99 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
 #define TLB_MMIO            (1 <= ;< (TARGET_PAGE_BITS - 3))
 /* Set if TLB entry must have MMU lookup repeated for every acce= ss */
 #define TLB_RECHECK         (1 << (TAR= GET_PAGE_BITS - 4))
+/* Set if TLB entry must take the slow path.  */
+#define TLB_FORCE_SLOW      (1 << (TARGET_PA= GE_BITS - 5))
 
 /* Use this mask to check interception with an alignment mask
  * in a TCG backend.
  */
-#define TLB_FLAGS_MASK  (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_M= MIO \
-                    = ;     | TLB_RECHECK)
+#define TLB_FLAGS_MASK \
+    (TLB_INVALID_MASK  \
+     | TLB_NOTDIRTY    \
+     | TLB_MMIO        \
+     | TLB_RECHECK     \
+     | TLB_FORCE_SLOW)
 
 /**
  * tlb_hit_page: return true if page aligned @addr is a hit agai= nst the
-- 
1.8.3.1



--_000_15640419170348581btcom_-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EC83C76191 for ; Thu, 25 Jul 2019 08:05:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1ADE521901 for ; Thu, 25 Jul 2019 08:05:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1ADE521901 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bt.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqYky-0001f0-EY for qemu-devel@archiver.kernel.org; Thu, 25 Jul 2019 04:05:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38471) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqYko-0001Aa-DB for qemu-devel@nongnu.org; Thu, 25 Jul 2019 04:05:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqYkn-0003gh-8y for qemu-devel@nongnu.org; Thu, 25 Jul 2019 04:05:34 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.72]:55312) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqYkc-0003Y7-T9; Thu, 25 Jul 2019 04:05:23 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926077.bt.com (10.36.82.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 09:05:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 09:05:17 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 09:05:17 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path Thread-Index: AQHVQr+y/H9707CquU6/1OwIMKzlIg== Date: Thu, 25 Jul 2019 08:05:17 +0000 Message-ID: <1564041917034.8581@bt.com> References: , <1563810716254.18886@bt.com>, <1564038073754.91133@bt.com>, <1564041524365.23360@bt.com> In-Reply-To: <1564041524365.23360@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The fast path is taken when TLB_FLAGS_MASK is all zero. TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path, there are no other side effects. Signed-off-by: Tony Nguyen --- include/exec/cpu-all.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58..e496f99 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) /* Set if TLB entry must have MMU lookup repeated for every access */ #define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) +/* Set if TLB entry must take the slow path. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK \ + | TLB_NOTDIRTY \ + | TLB_MMIO \ + | TLB_RECHECK \ + | TLB_FORCE_SLOW) /** * tlb_hit_page: return true if page aligned @addr is a hit against the -- 1.8.3.1