From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hqaV1-0002KG-8H for mharc-qemu-riscv@gnu.org; Thu, 25 Jul 2019 05:57:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46193) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqaUy-0002HJ-HO for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 05:57:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqaUx-0001xk-Bo for qemu-riscv@nongnu.org; Thu, 25 Jul 2019 05:57:20 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.77]:45331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqaUq-0001r1-SK; Thu, 25 Jul 2019 05:57:13 -0400 Received: from tpw09926dag18h.domain1.systemhost.net (10.9.212.42) by BWP09926082.bt.com (10.36.82.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18h.domain1.systemhost.net (10.9.212.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 10:57:10 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute Thread-Index: AQHVQs9TV3Ksh5mCZEubSX87RH7OKg== Date: Thu, 25 Jul 2019 09:57:10 +0000 Message-ID: <1564048630378.78008@bt.com> References: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_156404863037878008btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.77 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jul 2019 09:57:21 -0000 --_000_156404863037878008btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e61b1eb..f292a87 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1 --_000_156404863037878008btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Notice new attribute, byte swap, and = force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c      | 11 ++++= +++++++
 include/exec/memattrs.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e61b1eb..f292a87 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, ta= rget_ulong vaddr,
          */
         address |=3D TLB_RECHECK;
     }
+    if (attrs.byte_swap) {
+        address |=3D TLB_FORCE_SLOW;
+    }
     if (!memory_region_is_ram(section->mr) &&am= p;
         !memory_region_is_romd(section->m= r)) {
         /* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, C= PUIOTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUI= OTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..a0644eb 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
     unsigned int user:1;
     /* Requester ID (for MSI for example) */
     unsigned int requester_id:16;
+    /* SPARC64: TTE invert endianness */
+    unsigned int byte_swap:1;
     /*
      * The following are target-specific page-table bi= ts.  These are not
      * related to actual memory transactions at all. &= nbsp;However, this structure
-- 
1.8.3.1



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[209.51.188.17]) by mx.google.com with ESMTPS id y25si9836746edc.377.2019.07.25.02.57.27 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jul 2019 02:57:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=bt.com Received: from localhost ([::1]:57994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqaV4-0002Lv-AY for alex.bennee@linaro.org; Thu, 25 Jul 2019 05:57:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46221) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqaV1-0002KF-4L for qemu-arm@nongnu.org; Thu, 25 Jul 2019 05:57:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqaUz-00020a-TN for qemu-arm@nongnu.org; Thu, 25 Jul 2019 05:57:23 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.77]:45331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqaUq-0001r1-SK; Thu, 25 Jul 2019 05:57:13 -0400 Received: from tpw09926dag18h.domain1.systemhost.net (10.9.212.42) by BWP09926082.bt.com (10.36.82.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18h.domain1.systemhost.net (10.9.212.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 10:57:10 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute Thread-Index: AQHVQs9TV3Ksh5mCZEubSX87RH7OKg== Date: Thu, 25 Jul 2019 09:57:10 +0000 Message-ID: <1564048630378.78008@bt.com> References: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_156404863037878008btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.77 Subject: [Qemu-arm] [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, sagark@eecs.berkeley.edu, david@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, laurent@vivier.eu, Alistair.Francis@wdc.com, arikalo@wavecomp.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, stefanha@redhat.com, shorne@gmail.com, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, kbastian@mail.uni-paderborn.de, cohuck@redhat.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: TRQQZ/fc8T5R --_000_156404863037878008btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e61b1eb..f292a87 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1 --_000_156404863037878008btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Notice new attribute, byte swap, and = force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c      | 11 ++++= +++++++
 include/exec/memattrs.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e61b1eb..f292a87 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, ta= rget_ulong vaddr,
          */
         address |=3D TLB_RECHECK;
     }
+    if (attrs.byte_swap) {
+        address |=3D TLB_FORCE_SLOW;
+    }
     if (!memory_region_is_ram(section->mr) &&am= p;
         !memory_region_is_romd(section->m= r)) {
         /* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, C= PUIOTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUI= OTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..a0644eb 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
     unsigned int user:1;
     /* Requester ID (for MSI for example) */
     unsigned int requester_id:16;
+    /* SPARC64: TTE invert endianness */
+    unsigned int byte_swap:1;
     /*
      * The following are target-specific page-table bi= ts.  These are not
      * related to actual memory transactions at all. &= nbsp;However, this structure
-- 
1.8.3.1



--_000_156404863037878008btcom_-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0352C7618B for ; Thu, 25 Jul 2019 09:57:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB8F820840 for ; Thu, 25 Jul 2019 09:57:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB8F820840 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bt.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqaVE-0002pp-1L for qemu-devel@archiver.kernel.org; Thu, 25 Jul 2019 05:57:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46235) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqaV3-0002NW-JY for qemu-devel@nongnu.org; Thu, 25 Jul 2019 05:57:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqaV2-000225-Cn for qemu-devel@nongnu.org; Thu, 25 Jul 2019 05:57:25 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.77]:45331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqaUq-0001r1-SK; Thu, 25 Jul 2019 05:57:13 -0400 Received: from tpw09926dag18h.domain1.systemhost.net (10.9.212.42) by BWP09926082.bt.com (10.36.82.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18h.domain1.systemhost.net (10.9.212.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 10:57:10 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 10:57:10 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute Thread-Index: AQHVQs9TV3Ksh5mCZEubSX87RH7OKg== Date: Thu, 25 Jul 2019 09:57:10 +0000 Message-ID: <1564048630378.78008@bt.com> References: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45d1ebe4b2ed4c039c9da20a738652df@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.77 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, sagark@eecs.berkeley.edu, david@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, laurent@vivier.eu, Alistair.Francis@wdc.com, edgar.iglesias@gmail.com, arikalo@wavecomp.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, stefanha@redhat.com, shorne@gmail.com, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, kbastian@mail.uni-paderborn.de, cohuck@redhat.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e61b1eb..f292a87 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1