From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hqu0Y-0001FR-CD for mharc-qemu-riscv@gnu.org; Fri, 26 Jul 2019 02:47:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50406) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqu0U-0000uU-2U for qemu-riscv@nongnu.org; Fri, 26 Jul 2019 02:47:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqu0Q-0003KD-Cb for qemu-riscv@nongnu.org; Fri, 26 Jul 2019 02:47:08 -0400 Received: from smtpe1.intersmtp.com ([62.239.224.235]:32449) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqu0P-00032B-Oe; Fri, 26 Jul 2019 02:47:06 -0400 Received: from tpw09926dag18f.domain1.systemhost.net (10.9.212.26) by RDW083A011ED67.bt.com (10.187.98.37) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 26 Jul 2019 07:52:09 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18f.domain1.systemhost.net (10.9.212.26) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 26 Jul 2019 07:46:58 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Fri, 26 Jul 2019 07:46:58 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v5 09/15] cputlb: Access MemoryRegion with MemOp Thread-Index: AQHVQ33sEAGS5m5KhE2amU/8grrKQg== Date: Fri, 26 Jul 2019 06:46:58 +0000 Message-ID: <1564123618147.19868@bt.com> References: <3106a3c959c4498fad13a5799c89ba7b@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <3106a3c959c4498fad13a5799c89ba7b@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] Content-Type: multipart/alternative; boundary="_000_156412361814719868btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.235 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v5 09/15] cputlb: Access MemoryRegion with MemOp X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Jul 2019 06:47:13 -0000 --_000_156412361814719868btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily convert memory_region_dispatch_{read|write} paramter "unsigned size" into a size+sign+endianness encoded "MemOp op". Being a no-op macro, this patch does not introduce any logical change. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 523be4c..5d88cec 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, = int size, static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr= , - MMUAccessType access_type, int size) + MMUAccessType access_type, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, - &val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), access= _type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { @@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, - val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, - mmu_idx, iotlbentry->attrs, r, retaddr); + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1306,7 +1305,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, } res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, size); + mmu_idx, addr, retaddr, access_type, SIZE_MEMOP(siz= e)); return handle_bswap(res, size, big_endian); } @@ -1555,7 +1554,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, handle_bswap(val, size, big_endian), - addr, retaddr, size); + addr, retaddr, SIZE_MEMOP(size)); return; } -- 1.8.3.1 --_000_156412361814719868btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

No-op MEMOP_SIZE and SIZE_MEMOP macro= s allows us to later easily
convert memory_region_dispatch_{read|write} paramter "unsigned si= ze"
into a size+sign+endianness encoded "MemOp op".

Being a no-op macro, this patch does not introduce any logical change.=

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c | 21 ++++++++= ++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 523be4c..5d88cec 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulo= ng addr, int size,
 
 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlb= entry,
                    =       int mmu_idx, target_ulong addr, uintptr_t retaddr,
-                    = ;     MMUAccessType access_type, int size)
+                   &= nbsp;     MMUAccessType access_type, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, = CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_read(mr, mr_offset,
-                    = ;                &val, size, io= tlbentry->attrs);
+    r =3D memory_region_dispatch_read(mr, mr_offset, &a= mp;val, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, access_type,
+        cpu_transaction_failed(cpu, physaddr,= addr, MEMOP_SIZE(op), access_type,
                    =             mmu_idx, iotlbentry->attrs, r,= retaddr);
     }
     if (locked) {
@@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CP= UIOTLBEntry *iotlbentry,
 
 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbent= ry,
                    =    int mmu_idx, uint64_t val, target_ulong addr,
-                    = ;  uintptr_t retaddr, int size)
+                   &= nbsp;  uintptr_t retaddr, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPU= IOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_write(mr, mr_offset,
-                    = ;                 val, size, iotlbe= ntry->attrs);
+    r =3D memory_region_dispatch_write(mr, mr_offset, v= al, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, MMU_DATA_STORE,
-                    = ;           mmu_idx, iotlbentry->attrs, r, reta= ddr);
+        cpu_transaction_failed(cpu, physaddr,= addr, MEMOP_SIZE(op),
+                   &= nbsp;           MMU_DATA_STORE, mmu_idx, iotlbentr= y->attrs, r,
+                   &= nbsp;           retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -1306,7 +1305,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
         }
 
         res =3D io_readx(env, &env_tlb(e= nv)->d[mmu_idx].iotlb[index],
-                    = ;   mmu_idx, addr, retaddr, access_type, size);
+                   &= nbsp;   mmu_idx, addr, retaddr, access_type, SIZE_MEMOP(size));
         return handle_bswap(res, size, big_e= ndian);
     }
 
@@ -1555,7 +1554,7 @@ store_helper(CPUArchState *env, target_ulong= addr, uint64_t val,
 
         io_writex(env, &env_tlb(env)->= ;d[mmu_idx].iotlb[index], mmu_idx,
                   h= andle_bswap(val, size, big_endian),
-                  addr, = retaddr, size);
+                  ad= dr, retaddr, SIZE_MEMOP(size));
         return;
     }
 
-- 
1.8.3.1



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X-Received-From: 62.239.224.235 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v5 09/15] cputlb: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, sagark@eecs.berkeley.edu, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, laurent@vivier.eu, Alistair.Francis@wdc.com, edgar.iglesias@gmail.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, stefanha@redhat.com, shorne@gmail.com, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, kbastian@mail.uni-paderborn.de, cohuck@redhat.com, alex.williamson@redhat.com, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: WiD3DTFv79u+ No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily convert memory_region_dispatch_{read|write} paramter "unsigned size" into a size+sign+endianness encoded "MemOp op". Being a no-op macro, this patch does not introduce any logical change. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 523be4c..5d88cec 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, = int size, static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr= , - MMUAccessType access_type, int size) + MMUAccessType access_type, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, - &val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), access= _type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { @@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, - val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, - mmu_idx, iotlbentry->attrs, r, retaddr); + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1306,7 +1305,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, } res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, size); + mmu_idx, addr, retaddr, access_type, SIZE_MEMOP(siz= e)); return handle_bswap(res, size, big_endian); } @@ -1555,7 +1554,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, handle_bswap(val, size, big_endian), - addr, retaddr, size); + addr, retaddr, SIZE_MEMOP(size)); return; } -- 1.8.3.1