From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:45646 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726229AbeHTTTI (ORCPT ); Mon, 20 Aug 2018 15:19:08 -0400 From: Laurent Pinchart To: Kieran Bingham Cc: David Airlie , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] drm: rcar-du: Refactor Feature and Quirk definitions Date: Mon, 20 Aug 2018 19:03:49 +0300 Message-ID: <1564177.rmXuzezsgn@avalon> In-Reply-To: <20180820160044.15783-2-kieran.bingham+renesas@ideasonboard.com> References: <20180820160044.15783-1-kieran.bingham+renesas@ideasonboard.com> <20180820160044.15783-2-kieran.bingham+renesas@ideasonboard.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Kieran, Thank you for the patch. On Monday, 20 August 2018 19:00:43 EEST Kieran Bingham wrote: > These flags are represented by bit fields. To make this clear, utilise > the BIT() macro. > > Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart > --- > This patch fails checkpatch's 80-char limit, due to the line comments > extending across the 80-char boundary on RCAR_DU_FEATURE_EXT_CTRL_REGS > > To preserve formatting - this warning has been ignored. > > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index b3a25e8e07d0..78ea20abfb30 > 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h > @@ -27,11 +27,11 @@ struct drm_device; > struct drm_fbdev_cma; > struct rcar_du_device; > > -#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK (1 << 0) /* Per-CRTC IRQ and clock > */ -#define RCAR_DU_FEATURE_EXT_CTRL_REGS (1 << 1) /* Has extended control > registers */ -#define RCAR_DU_FEATURE_VSP1_SOURCE (1 << 2) /* Has inputs > from VSP1 */ +#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ > and clock */ +#define RCAR_DU_FEATURE_EXT_CTRL_REGS BIT(1) /* Has extended > control registers */ +#define RCAR_DU_FEATURE_VSP1_SOURCE BIT(2) /* Has > inputs from VSP1 */ > > -#define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ > +#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ > > /* > * struct rcar_du_output_routing - Output routing specification -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 1/2] drm: rcar-du: Refactor Feature and Quirk definitions Date: Mon, 20 Aug 2018 19:03:49 +0300 Message-ID: <1564177.rmXuzezsgn@avalon> References: <20180820160044.15783-1-kieran.bingham+renesas@ideasonboard.com> <20180820160044.15783-2-kieran.bingham+renesas@ideasonboard.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7246D6E2AC for ; Mon, 20 Aug 2018 16:02:55 +0000 (UTC) In-Reply-To: <20180820160044.15783-2-kieran.bingham+renesas@ideasonboard.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Kieran Bingham Cc: David Airlie , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgS2llcmFuLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBNb25kYXksIDIwIEF1Z3Vz dCAyMDE4IDE5OjAwOjQzIEVFU1QgS2llcmFuIEJpbmdoYW0gd3JvdGU6Cj4gVGhlc2UgZmxhZ3Mg YXJlIHJlcHJlc2VudGVkIGJ5IGJpdCBmaWVsZHMuIFRvIG1ha2UgdGhpcyBjbGVhciwgdXRpbGlz ZQo+IHRoZSBCSVQoKSBtYWNyby4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBLaWVyYW4gQmluZ2hhbSA8 a2llcmFuLmJpbmdoYW0rcmVuZXNhc0BpZGVhc29uYm9hcmQuY29tPgoKUmV2aWV3ZWQtYnk6IExh dXJlbnQgUGluY2hhcnQgPGxhdXJlbnQucGluY2hhcnRAaWRlYXNvbmJvYXJkLmNvbT4KCj4gLS0t Cj4gVGhpcyBwYXRjaCBmYWlscyBjaGVja3BhdGNoJ3MgODAtY2hhciBsaW1pdCwgZHVlIHRvIHRo ZSBsaW5lIGNvbW1lbnRzCj4gZXh0ZW5kaW5nIGFjcm9zcyB0aGUgODAtY2hhciBib3VuZGFyeSBv biBSQ0FSX0RVX0ZFQVRVUkVfRVhUX0NUUkxfUkVHUwo+IAo+IFRvIHByZXNlcnZlIGZvcm1hdHRp bmcgLSB0aGlzIHdhcm5pbmcgaGFzIGJlZW4gaWdub3JlZC4KPiAKPiAgZHJpdmVycy9ncHUvZHJt L3JjYXItZHUvcmNhcl9kdV9kcnYuaCB8IDggKysrKy0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDQg aW5zZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL3JjYXItZHUvcmNhcl9kdV9kcnYuaAo+IGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUv cmNhcl9kdV9kcnYuaCBpbmRleCBiM2EyNWU4ZTA3ZDAuLjc4ZWEyMGFiZmIzMAo+IDEwMDY0NAo+ IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmgKPiArKysgYi9kcml2 ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5oCj4gQEAgLTI3LDExICsyNywxMSBAQCBz dHJ1Y3QgZHJtX2RldmljZTsKPiAgc3RydWN0IGRybV9mYmRldl9jbWE7Cj4gIHN0cnVjdCByY2Fy X2R1X2RldmljZTsKPiAKPiAtI2RlZmluZSBSQ0FSX0RVX0ZFQVRVUkVfQ1JUQ19JUlFfQ0xPQ0sJ KDEgPDwgMCkJLyogUGVyLUNSVEMgSVJRIGFuZCBjbG9jawo+ICovIC0jZGVmaW5lIFJDQVJfRFVf RkVBVFVSRV9FWFRfQ1RSTF9SRUdTCSgxIDw8IDEpCS8qIEhhcyBleHRlbmRlZCBjb250cm9sCj4g cmVnaXN0ZXJzICovIC0jZGVmaW5lIFJDQVJfRFVfRkVBVFVSRV9WU1AxX1NPVVJDRQkoMSA8PCAy KQkvKiBIYXMgaW5wdXRzCj4gZnJvbSBWU1AxICovICsjZGVmaW5lIFJDQVJfRFVfRkVBVFVSRV9D UlRDX0lSUV9DTE9DSwlCSVQoMCkJLyogUGVyLUNSVEMgSVJRCj4gYW5kIGNsb2NrICovICsjZGVm aW5lIFJDQVJfRFVfRkVBVFVSRV9FWFRfQ1RSTF9SRUdTCUJJVCgxKQkvKiBIYXMgZXh0ZW5kZWQK PiBjb250cm9sIHJlZ2lzdGVycyAqLyArI2RlZmluZSBSQ0FSX0RVX0ZFQVRVUkVfVlNQMV9TT1VS Q0UJQklUKDIpCS8qIEhhcwo+IGlucHV0cyBmcm9tIFZTUDEgKi8KPiAKPiAtI2RlZmluZSBSQ0FS X0RVX1FVSVJLX0FMSUdOXzEyOEIJKDEgPDwgMCkJLyogQWxpZ24gcGl0Y2hlcyB0byAxMjggYnl0 ZXMgCiovCj4gKyNkZWZpbmUgUkNBUl9EVV9RVUlSS19BTElHTl8xMjhCCUJJVCgwKQkvKiBBbGln biBwaXRjaGVzIHRvIDEyOCBieXRlcyAqLwo+IAo+ICAvKgo+ICAgKiBzdHJ1Y3QgcmNhcl9kdV9v dXRwdXRfcm91dGluZyAtIE91dHB1dCByb3V0aW5nIHNwZWNpZmljYXRpb24KCgotLSAKUmVnYXJk cywKCkxhdXJlbnQgUGluY2hhcnQKCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJl ZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vZHJpLWRldmVsCg==