diff for duplicates of <1564701.sT8vso17XV@avalon> diff --git a/a/1.txt b/N1/1.txt index 972c57e..129a2dc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -41,13 +41,13 @@ Happy new year ;-) > + static const unsigned int name##_pins[] = { pin }; \ > + static const unsigned int name##_mux[] = { mark##_MARK } > + -> +/* = [ System ] ====== */ +> +/* = [ System ] =========== */ > +EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB); > +EMEV_MUX_PIN(ref_clko, 4, REF_CLKO); > +EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI); > +EMEV_MUX_PIN(lowpwr, 154, LOWPWR); > + -> +/* = [ External Memory] == */ +> +/* = [ External Memory] === */ I don't have much information on the external memory bus, would it make sense to group some of the pins ? I expect that at AB_AD[15:0] will always be @@ -94,7 +94,7 @@ read-only or write-only memory maybe ? > +EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0); > +EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1); > + -> +/* = [ CAM ] ======= */ +> +/* = [ CAM ] ============== */ > +static const unsigned int cam_ctrl_pins[] = { > + /* CLKO, CLKI, VS, HS */ @@ -121,7 +121,7 @@ can't be used separately. [snip] -> +/* = [ JTAG ] ======= */ +> +/* = [ JTAG ] ============= */ > +EMEV_MUX_PIN(jt_sel, 2, JT_SEL); > +EMEV_MUX_PIN(jt_tdo, 151, JT_TDO); > +EMEV_MUX_PIN(jt_tdoen, 152, JT_TDOEN); @@ -131,7 +131,7 @@ used together you can combine the pins into a single group. [snip] -> +/* = [ TP33 ] ======= */ +> +/* = [ TP33 ] ============= */ Can the trace port control and data signals be used independently ? If they always need to be used together you can combine the pins into a single group. @@ -162,7 +162,7 @@ always need to be used together you can combine the pins into a single group. [snip] -> +/* = [ USI0 ] ======= */ +> +/* = [ USI0 ] ============== */ > +EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1); > +EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2); > +EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3); @@ -170,7 +170,7 @@ always need to be used together you can combine the pins into a single group. > +EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5); > +EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6); > + -> +/* = [ USI1 ] ======= */ +> +/* = [ USI1 ] ============== */ > +static const unsigned int usi1_ctrl_pins[] = { Those are data pins, shouldn't the group be named usi1_data ? @@ -182,7 +182,7 @@ Those are data pins, shouldn't the group be named usi1_data ? > + USI1_DI_MARK, USI1_DO_MARK, > +}; > + -> +/* = [ USI2 ] ======= */ +> +/* = [ USI2 ] ============== */ > +static const unsigned int usi2_ctrl_pins[] = { Same here, although there's also a clock pin. @@ -198,7 +198,7 @@ Same comment for usi[345]_ctrl* below. [snip] -> +/* = [ YUV ] ======= */ +> +/* = [ YUV ] ============== */ I believe the clock input is optional, but I think the clock output, data and synchronization signals should be part of the same group as they can't be used diff --git a/a/content_digest b/N1/content_digest index d098c00..fdf8176 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,7 @@ "ref\01421583604-27256-3-git-send-email-niso@kth.se\0" "From\0Laurent Pinchart <laurent.pinchart@ideasonboard.com>\0" "Subject\0Re: [PATCH v2 2/4] sh-pfc: Add emev2 pinmux support\0" - "Date\0Thu, 22 Jan 2015 22:37:33 +0000\0" + "Date\0Fri, 23 Jan 2015 00:37:33 +0200\0" "To\0Niklas S\303\266derlund <niso@kth.se>\0" "Cc\0linux-kernel@vger.kernel.org" linus.walleij@linaro.org @@ -54,13 +54,13 @@ "> +\tstatic const unsigned int name##_pins[] = { pin }; \\\n" "> +\tstatic const unsigned int name##_mux[] = { mark##_MARK }\n" "> +\n" - "> +/* = [ System ] ====== */\n" + "> +/* = [ System ] =========== */\n" "> +EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);\n" "> +EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);\n" "> +EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);\n" "> +EMEV_MUX_PIN(lowpwr, 154, LOWPWR);\n" "> +\n" - "> +/* = [ External Memory] == */\n" + "> +/* = [ External Memory] === */\n" "\n" "I don't have much information on the external memory bus, would it make sense \n" "to group some of the pins ? I expect that at AB_AD[15:0] will always be \n" @@ -107,7 +107,7 @@ "> +EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);\n" "> +EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);\n" "> +\n" - "> +/* = [ CAM ] ======= */\n" + "> +/* = [ CAM ] ============== */\n" "> +static const unsigned int cam_ctrl_pins[] = {\n" "> +\t/* CLKO, CLKI, VS, HS */\n" "\n" @@ -134,7 +134,7 @@ "\n" "[snip]\n" "\n" - "> +/* = [ JTAG ] ======= */\n" + "> +/* = [ JTAG ] ============= */\n" "> +EMEV_MUX_PIN(jt_sel, 2, JT_SEL);\n" "> +EMEV_MUX_PIN(jt_tdo, 151, JT_TDO);\n" "> +EMEV_MUX_PIN(jt_tdoen, 152, JT_TDOEN);\n" @@ -144,7 +144,7 @@ "\n" "[snip]\n" "\n" - "> +/* = [ TP33 ] ======= */\n" + "> +/* = [ TP33 ] ============= */\n" "\n" "Can the trace port control and data signals be used independently ? If they \n" "always need to be used together you can combine the pins into a single group.\n" @@ -175,7 +175,7 @@ "\n" "[snip]\n" "\n" - "> +/* = [ USI0 ] ======= */\n" + "> +/* = [ USI0 ] ============== */\n" "> +EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);\n" "> +EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);\n" "> +EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);\n" @@ -183,7 +183,7 @@ "> +EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);\n" "> +EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);\n" "> +\n" - "> +/* = [ USI1 ] ======= */\n" + "> +/* = [ USI1 ] ============== */\n" "> +static const unsigned int usi1_ctrl_pins[] = {\n" "\n" "Those are data pins, shouldn't the group be named usi1_data ?\n" @@ -195,7 +195,7 @@ "> +\tUSI1_DI_MARK, USI1_DO_MARK,\n" "> +};\n" "> +\n" - "> +/* = [ USI2 ] ======= */\n" + "> +/* = [ USI2 ] ============== */\n" "> +static const unsigned int usi2_ctrl_pins[] = {\n" "\n" "Same here, although there's also a clock pin.\n" @@ -211,7 +211,7 @@ "\n" "[snip]\n" "\n" - "> +/* = [ YUV ] ======= */\n" + "> +/* = [ YUV ] ============== */\n" "\n" "I believe the clock input is optional, but I think the clock output, data and \n" "synchronization signals should be part of the same group as they can't be used \n" @@ -250,4 +250,4 @@ "\n" Laurent Pinchart -15247f61da989c5515b3f702f79f42f369111a431963db40b17ffc65c425958d +00c11fe8ac27cc25310966aaf7be6eb0888ae114bc550d5688075b90d8ffa883
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