From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.86_2) id 1hvLdc-0006Lf-6M for mharc-qemu-riscv@gnu.org; Wed, 07 Aug 2019 09:05:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45478) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hvHNv-0002tf-Qi for qemu-riscv@nongnu.org; Wed, 07 Aug 2019 04:33:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hvHNq-0002x0-K3 for qemu-riscv@nongnu.org; Wed, 07 Aug 2019 04:33:27 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.72]:22696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hvHNo-0002tF-T3; Wed, 07 Aug 2019 04:33:22 -0400 Received: from tpw09926dag18f.domain1.systemhost.net (10.9.212.26) by BWP09926077.bt.com (10.36.82.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Wed, 7 Aug 2019 09:32:54 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18f.domain1.systemhost.net (10.9.212.26) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 7 Aug 2019 09:33:15 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Wed, 7 Aug 2019 09:33:15 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness Thread-Index: AQHVTPrBMLYYco2250O7I7O3jldIgg== Date: Wed, 7 Aug 2019 08:33:15 +0000 Message-ID: <1565166794966.57397@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] Content-Type: multipart/alternative; boundary="_000_156516679496657397btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 X-Mailman-Approved-At: Wed, 07 Aug 2019 09:05:48 -0400 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Aug 2019 08:33:33 -0000 --_000_156516679496657397btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps need to collapse them into adjust_endianness. Signed-off-by: Tony Nguyen --- hw/s390x/s390-pci-inst.c | 3 ++- hw/virtio/virtio-pci.c | 2 ++ include/exec/memop.h | 4 ++++ memory_ldst.inc.c | 20 +++++++++++++------- target/mips/op_helper.c | 4 ++-- 5 files changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a37..d322b86 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, ldq_p(buffer + i * 8), - MO_64, MEMTXATTRS_UNSPECIFIE= D); + MO_64 | MO_TE, + MEMTXATTRS_UNSPECIFIED); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b929e44..70eb161 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ memory_region_dispatch_write(mr, addr, val, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ memory_region_dispatch_read(mr, addr, &val, size_memop(len), MEMTXATTRS_UNSPECIFIED); switch (len) { diff --git a/include/exec/memop.h b/include/exec/memop.h index 4a4212d..47a5500 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size) /* Power of 2 up to 8. */ assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); #endif +#ifdef NEED_CPU_H + return ctz32(size) | MO_TE; +#else return ctz32(size); +#endif } #endif diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index d7e28d0..ff28b30 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap32(val); @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap64(val); @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap16(val); @@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | MO_TE, = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -343,7 +346,8 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -448,7 +452,8 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e79f99d..1b475f3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED= ); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED)= ; } #endif } -- 1.8.3.1 ? --_000_156516679496657397btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into<= /div>
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps need to
collapse them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/s390x/s390-pci-inst.c |  3 ++-
 hw/virtio/virtio-pci.c   |  2 ++
 include/exec/memop.h     |  4 ++++= ;
 memory_ldst.inc.c        | 20 +++= ;++++++++++-------
 target/mips/op_helper.c  |  4 ++--
 5 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..d322b86 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t = r1, uint8_t r3, uint64_t gaddr,
     for (i =3D 0; i < len / 8; i++) {
         result =3D memory_region_dispatch_wr= ite(mr, offset + i * 8,
                    =                      = ;      ldq_p(buffer + i * 8),
-                    = ;                     &nb= sp;    MO_64, MEMTXATTRS_UNSPECIFIED);
+                   &= nbsp;                    =      MO_64 | MO_TE,
+                   &= nbsp;                    =      MEMTXATTRS_UNSPECIFIED);
         if (result !=3D MEMTX_OK) {
             s390_program_interrupt= (env, PGM_OPERAND, 6, ra);
             return 0;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..70eb161 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy= *proxy, hwaddr addr,
         /* As length is under guest control,= handle illegal values. */
         return;
     }
+    /* FIXME: memory_region_dispatch_write ignores MO_B= SWAP.  */
     memory_region_dispatch_write(mr, addr, val, size_m= emop(len),
                    =               MEMTXATTRS_UNSPECIFIED);
 }
@@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
+    /* FIXME: memory_region_dispatch_read ignores MO_BS= WAP.  */
     memory_region_dispatch_read(mr, addr, &val, si= ze_memop(len),
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 4a4212d..47a5500 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size)=
     /* Power of 2 up to 8.  */
     assert((size & (size - 1)) =3D=3D 0 &&= size >=3D 1 && size <=3D 8);
 #endif
+#ifdef NEED_CPU_H
+    return ctz32(size) | MO_TE;
+#else
     return ctz32(size);
+#endif
 }
 
 #endif
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d7e28d0..ff28b30 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap32(val);<= /div>
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap64(val);<= /div>
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap16(val);<= /div>
@@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
 
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | MO_TE, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
         stl_p(ptr, val);
@@ -343,7 +346,8 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -448,7 +452,8 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e79f99d..1b475f3 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, targe= t_ulong addr, uint32_t op)
     if (op =3D=3D 9) {
         /* Index Store Tag */
         memory_region_dispatch_write(env->= ;itc_tag, index, env->CP0_TagLo,
-                    = ;                 MO_64, MEMTXATTRS= _UNSPECIFIED);
+                   &= nbsp;                 MO_64 | MO_TE= , MEMTXATTRS_UNSPECIFIED);
     } else if (op =3D=3D 5) {
         /* Index Load Tag */
         memory_region_dispatch_read(env->= itc_tag, index, &env->CP0_TagLo,
-                    = ;                MO_64, MEMTXATTRS_= UNSPECIFIED);
+                   &= nbsp;                MO_64 | MO_TE,= MEMTXATTRS_UNSPECIFIED);
     }
 #endif
 }
-- 
1.8.3.1

​


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Wed, 7 Aug 2019 09:33:15 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness Thread-Index: AQHVTPrBMLYYco2250O7I7O3jldIgg== Date: Wed, 7 Aug 2019 08:33:15 +0000 Message-ID: <1565166794966.57397@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] Content-Type: multipart/alternative; boundary="_000_156516679496657397btcom_" MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Subject: [Qemu-arm] [Qemu-devel] [PATCH v6 20/26] memory: Access MemoryRegion with endianness X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: ApvO/xJVdtJq --_000_156516679496657397btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps need to collapse them into adjust_endianness. Signed-off-by: Tony Nguyen --- hw/s390x/s390-pci-inst.c | 3 ++- hw/virtio/virtio-pci.c | 2 ++ include/exec/memop.h | 4 ++++ memory_ldst.inc.c | 20 +++++++++++++------- target/mips/op_helper.c | 4 ++-- 5 files changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a37..d322b86 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, ldq_p(buffer + i * 8), - MO_64, MEMTXATTRS_UNSPECIFIE= D); + MO_64 | MO_TE, + MEMTXATTRS_UNSPECIFIED); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b929e44..70eb161 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ memory_region_dispatch_write(mr, addr, val, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ memory_region_dispatch_read(mr, addr, &val, size_memop(len), MEMTXATTRS_UNSPECIFIED); switch (len) { diff --git a/include/exec/memop.h b/include/exec/memop.h index 4a4212d..47a5500 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size) /* Power of 2 up to 8. */ assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); #endif +#ifdef NEED_CPU_H + return ctz32(size) | MO_TE; +#else return ctz32(size); +#endif } #endif diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index d7e28d0..ff28b30 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap32(val); @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap64(val); @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap16(val); @@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | MO_TE, = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -343,7 +346,8 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -448,7 +452,8 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e79f99d..1b475f3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED= ); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED)= ; } #endif } -- 1.8.3.1 ? --_000_156516679496657397btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into<= /div>
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps need to
collapse them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/s390x/s390-pci-inst.c |  3 ++-
 hw/virtio/virtio-pci.c   |  2 ++
 include/exec/memop.h     |  4 ++++= ;
 memory_ldst.inc.c        | 20 +++= ;++++++++++-------
 target/mips/op_helper.c  |  4 ++--
 5 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..d322b86 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t = r1, uint8_t r3, uint64_t gaddr,
     for (i =3D 0; i < len / 8; i++) {
         result =3D memory_region_dispatch_wr= ite(mr, offset + i * 8,
                    =                      = ;      ldq_p(buffer + i * 8),
-                    = ;                     &nb= sp;    MO_64, MEMTXATTRS_UNSPECIFIED);
+                   &= nbsp;                    =      MO_64 | MO_TE,
+                   &= nbsp;                    =      MEMTXATTRS_UNSPECIFIED);
         if (result !=3D MEMTX_OK) {
             s390_program_interrupt= (env, PGM_OPERAND, 6, ra);
             return 0;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..70eb161 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy= *proxy, hwaddr addr,
         /* As length is under guest control,= handle illegal values. */
         return;
     }
+    /* FIXME: memory_region_dispatch_write ignores MO_B= SWAP.  */
     memory_region_dispatch_write(mr, addr, val, size_m= emop(len),
                    =               MEMTXATTRS_UNSPECIFIED);
 }
@@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
+    /* FIXME: memory_region_dispatch_read ignores MO_BS= WAP.  */
     memory_region_dispatch_read(mr, addr, &val, si= ze_memop(len),
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 4a4212d..47a5500 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size)=
     /* Power of 2 up to 8.  */
     assert((size & (size - 1)) =3D=3D 0 &&= size >=3D 1 && size <=3D 8);
 #endif
+#ifdef NEED_CPU_H
+    return ctz32(size) | MO_TE;
+#else
     return ctz32(size);
+#endif
 }
 
 #endif
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d7e28d0..ff28b30 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap32(val);<= /div>
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap64(val);<= /div>
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap16(val);<= /div>
@@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
 
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | MO_TE, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
         stl_p(ptr, val);
@@ -343,7 +346,8 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -448,7 +452,8 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e79f99d..1b475f3 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, targe= t_ulong addr, uint32_t op)
     if (op =3D=3D 9) {
         /* Index Store Tag */
         memory_region_dispatch_write(env->= ;itc_tag, index, env->CP0_TagLo,
-                    = ;                 MO_64, MEMTXATTRS= _UNSPECIFIED);
+                   &= nbsp;                 MO_64 | MO_TE= , MEMTXATTRS_UNSPECIFIED);
     } else if (op =3D=3D 5) {
         /* Index Load Tag */
         memory_region_dispatch_read(env->= itc_tag, index, &env->CP0_TagLo,
-                    = ;                MO_64, MEMTXATTRS_= UNSPECIFIED);
+                   &= nbsp;                MO_64 | MO_TE,= MEMTXATTRS_UNSPECIFIED);
     }
 #endif
 }
-- 
1.8.3.1

​


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boundary="===============8022994538016741085==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============8022994538016741085== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516679496657397btcom_" --_000_156516679496657397btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps need to collapse them into adjust_endianness. Signed-off-by: Tony Nguyen --- hw/s390x/s390-pci-inst.c | 3 ++- hw/virtio/virtio-pci.c | 2 ++ include/exec/memop.h | 4 ++++ memory_ldst.inc.c | 20 +++++++++++++------- target/mips/op_helper.c | 4 ++-- 5 files changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a37..d322b86 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, ldq_p(buffer + i * 8), - MO_64, MEMTXATTRS_UNSPECIFIE= D); + MO_64 | MO_TE, + MEMTXATTRS_UNSPECIFIED); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b929e44..70eb161 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ memory_region_dispatch_write(mr, addr, val, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ memory_region_dispatch_read(mr, addr, &val, size_memop(len), MEMTXATTRS_UNSPECIFIED); switch (len) { diff --git a/include/exec/memop.h b/include/exec/memop.h index 4a4212d..47a5500 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size) /* Power of 2 up to 8. */ assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); #endif +#ifdef NEED_CPU_H + return ctz32(size) | MO_TE; +#else return ctz32(size); +#endif } #endif diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index d7e28d0..ff28b30 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap32(val); @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap64(val); @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap16(val); @@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | MO_TE, = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -343,7 +346,8 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -448,7 +452,8 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e79f99d..1b475f3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED= ); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED)= ; } #endif } -- 1.8.3.1 ? --_000_156516679496657397btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into<= /div>
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps need to
collapse them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/s390x/s390-pci-inst.c |  3 ++-
 hw/virtio/virtio-pci.c   |  2 ++
 include/exec/memop.h     |  4 ++++= ;
 memory_ldst.inc.c        | 20 +++= ;++++++++++-------
 target/mips/op_helper.c  |  4 ++--
 5 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..d322b86 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t = r1, uint8_t r3, uint64_t gaddr,
     for (i =3D 0; i < len / 8; i++) {
         result =3D memory_region_dispatch_wr= ite(mr, offset + i * 8,
                    =                      = ;      ldq_p(buffer + i * 8),
-                    = ;                     &nb= sp;    MO_64, MEMTXATTRS_UNSPECIFIED);
+                   &= nbsp;                    =      MO_64 | MO_TE,
+                   &= nbsp;                    =      MEMTXATTRS_UNSPECIFIED);
         if (result !=3D MEMTX_OK) {
             s390_program_interrupt= (env, PGM_OPERAND, 6, ra);
             return 0;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..70eb161 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy= *proxy, hwaddr addr,
         /* As length is under guest control,= handle illegal values. */
         return;
     }
+    /* FIXME: memory_region_dispatch_write ignores MO_B= SWAP.  */
     memory_region_dispatch_write(mr, addr, val, size_m= emop(len),
                    =               MEMTXATTRS_UNSPECIFIED);
 }
@@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
+    /* FIXME: memory_region_dispatch_read ignores MO_BS= WAP.  */
     memory_region_dispatch_read(mr, addr, &val, si= ze_memop(len),
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 4a4212d..47a5500 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size)=
     /* Power of 2 up to 8.  */
     assert((size & (size - 1)) =3D=3D 0 &&= size >=3D 1 && size <=3D 8);
 #endif
+#ifdef NEED_CPU_H
+    return ctz32(size) | MO_TE;
+#else
     return ctz32(size);
+#endif
 }
 
 #endif
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d7e28d0..ff28b30 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap32(val);<= /div>
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap64(val);<= /div>
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap16(val);<= /div>
@@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
 
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | MO_TE, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
         stl_p(ptr, val);
@@ -343,7 +346,8 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -448,7 +452,8 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e79f99d..1b475f3 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, targe= t_ulong addr, uint32_t op)
     if (op =3D=3D 9) {
         /* Index Store Tag */
         memory_region_dispatch_write(env->= ;itc_tag, index, env->CP0_TagLo,
-                    = ;                 MO_64, MEMTXATTRS= _UNSPECIFIED);
+                   &= nbsp;                 MO_64 | MO_TE= , MEMTXATTRS_UNSPECIFIED);
     } else if (op =3D=3D 5) {
         /* Index Load Tag */
         memory_region_dispatch_read(env->= itc_tag, index, &env->CP0_TagLo,
-                    = ;                MO_64, MEMTXATTRS_= UNSPECIFIED);
+                   &= nbsp;                MO_64 | MO_TE,= MEMTXATTRS_UNSPECIFIED);
     }
 #endif
 }
-- 
1.8.3.1

​


--_000_156516679496657397btcom_-- --===============8022994538016741085== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0 cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== --===============8022994538016741085==--