diff for duplicates of <1565940417783.5399@bt.com> diff --git a/a/content_digest b/N1/content_digest index 3f3745a..83cff3c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,95 +1,94 @@ "ref\043bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" + "Subject\0[Qemu-arm] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" "Date\0Fri, 16 Aug 2019 07:26:59 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<rth@twiddle.net>" - <pbonzini@redhat.com> - <mst@redhat.com> - <imammedo@redhat.com> - <marcel.apfelbaum@gmail.com> - <xiaoguangrong.eric@gmail.com> - <alistair@alistair23.me> - <peter.maydell@linaro.org> - <b.galvani@gmail.com> - <clg@kaod.org> - <andrew@aj.id.au> - <joel@jms.id.au> - <i.mitsyanko@gmail.com> - <robh@kernel.org> - <peter.chubb@nicta.com.au> - <sundeep.lkml@gmail.com> - <jan.kiszka@web.de> - <balrogg@gmail.com> - <eric.auger@redhat.com> - <kraxel@redhat.com> - <michael@walle.cc> - <kwolf@redhat.com> - <mreitz@redhat.com> - <jsnow@redhat.com> - <keith.busch@intel.com> - <philmd@redhat.com> - <marcandre.lureau@redhat.com> - <Andrew.Baumann@microsoft.com> - <edgar.iglesias@gmail.com> - <antonynpavlov@gmail.com> - <chouteau@adacore.com> - <frederic.konrad@adacore.com> - <huth@tuxfamily.org> - <mark.cave-ayland@ilande.co.uk> - <hpoussin@reactos.org> - <arikalo@wavecomp.com> - <balaton@eik.bme.hu> - <gxt@mprc.pku.edu.cn> - <david@gibson.dropbear.id.au> - <deller@gmx.de> - <ehabkost@redhat.com> - <sstabellini@kernel.org> - <anthony.perard@citrix.com> - <paul.durrant@citrix.com> - <aurelien@aurel32.net> - <amarkovic@wavecomp.com> - <magnus.damm@gmail.com> - <berto@igalia.com> - <minyard@acm.org> - <pburton@wavecomp.com> - <jslaby@suse.cz> - <jcd@tribudubois.net> - <andrew.smirnov@gmail.com> - <green@moxielogic.com> - <jasowang@redhat.com> - <dmitry.fleytman@gmail.com> - <sw@weilnetz.de> - <jiri@resnulli.us> - <crwulff@gmail.com> - <marex@denx.de> - <lersek@redhat.com> - <proljc@gmail.com> - <shorne@gmail.com> - <yuval.shaia@oracle.com> - <palmer@sifive.com> - <sagark@eecs.berkeley.edu> - <kbastian@mail.uni-paderborn.de> - <walling@linux.ibm.com> - <cohuck@redhat.com> - <david@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <fam@euphon.net> - <hare@suse.com> - <atar4qemu@gmail.com> - <stefanb@linux.ibm.com> - <alex.williamson@redhat.com> - <jcmvbkbc@gmail.com> - <laurent@vivier.eu> - <claudio.fontana@suse.com> - <stefanha@redhat.com> - <qemu-arm@nongnu.org> - <qemu-block@nongnu.org> - <qemu-ppc@nongnu.org> - <xen-devel@lists.xenproject.org> - <qemu-riscv@nongnu.org> - " <qemu-s390x@nongnu.org>\0" + "Cc\0frederic.konrad@adacore.com" + berto@igalia.com + qemu-block@nongnu.org + arikalo@wavecomp.com + pasic@linux.ibm.com + hpoussin@reactos.org + anthony.perard@citrix.com + xen-devel@lists.xenproject.org + lersek@redhat.com + jasowang@redhat.com + jiri@resnulli.us + ehabkost@redhat.com + b.galvani@gmail.com + eric.auger@redhat.com + alex.williamson@redhat.com + stefanha@redhat.com + jsnow@redhat.com + rth@twiddle.net + kwolf@redhat.com + andrew@aj.id.au + claudio.fontana@suse.com + crwulff@gmail.com + laurent@vivier.eu + sundeep.lkml@gmail.com + michael@walle.cc + qemu-ppc@nongnu.org + kbastian@mail.uni-paderborn.de + imammedo@redhat.com + fam@euphon.net + peter.maydell@linaro.org + david@redhat.com + palmer@sifive.com + balaton@eik.bme.hu + keith.busch@intel.com + jcmvbkbc@gmail.com + hare@suse.com + sstabellini@kernel.org + andrew.smirnov@gmail.com + deller@gmx.de + magnus.damm@gmail.com + marcel.apfelbaum@gmail.com + atar4qemu@gmail.com + minyard@acm.org + sw@weilnetz.de + yuval.shaia@oracle.com + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + jan.kiszka@web.de + clg@kaod.org + shorne@gmail.com + qemu-riscv@nongnu.org + i.mitsyanko@gmail.com + cohuck@redhat.com + philmd@redhat.com + amarkovic@wavecomp.com + peter.chubb@nicta.com.au + aurelien@aurel32.net + pburton@wavecomp.com + sagark@eecs.berkeley.edu + green@moxielogic.com + kraxel@redhat.com + gxt@mprc.pku.edu.cn + robh@kernel.org + borntraeger@de.ibm.com + joel@jms.id.au + antonynpavlov@gmail.com + chouteau@adacore.com + balrogg@gmail.com + Andrew.Baumann@microsoft.com + mreitz@redhat.com + walling@linux.ibm.com + dmitry.fleytman@gmail.com + mst@redhat.com + mark.cave-ayland@ilande.co.uk + jslaby@suse.cz + marex@denx.de + proljc@gmail.com + marcandre.lureau@redhat.com + alistair@alistair23.me + paul.durrant@citrix.com + david@gibson.dropbear.id.au + xiaoguangrong.eric@gmail.com + huth@tuxfamily.org + jcd@tribudubois.net + pbonzini@redhat.com + " stefanb@linux.ibm.com\0" "\01:1\0" "b\0" "Preparation for collapsing the two byte swaps, adjust_endianness and\n" @@ -5565,4 +5564,4 @@ "</body>\r\n" "</html>\r\n" -db8536e3ed94cbe04b09d62e3589775b76edac95045071f5f61d3b26de193fa8 +7bfc6f8a93ce6ff351768d02b222714c7652c2740c208f458286b95d2538365a
diff --git a/N2/1.1.hdr b/N2/1.1.hdr new file mode 100644 index 0000000..12686e4 --- /dev/null +++ b/N2/1.1.hdr @@ -0,0 +1,2 @@ +Content-Type: text/plain; charset="iso-8859-1" +Content-Transfer-Encoding: quoted-printable diff --git a/a/1.txt b/N2/1.1.txt similarity index 100% rename from a/1.txt rename to N2/1.1.txt diff --git a/a/2.bin b/N2/1.2.bin similarity index 100% rename from a/2.bin rename to N2/1.2.bin diff --git a/N2/1.2.hdr b/N2/1.2.hdr new file mode 100644 index 0000000..e54d0ae --- /dev/null +++ b/N2/1.2.hdr @@ -0,0 +1,2 @@ +Content-Type: text/html; charset="iso-8859-1" +Content-Transfer-Encoding: quoted-printable diff --git a/a/2.hdr b/N2/2.hdr index e54d0ae..5216513 100644 --- a/a/2.hdr +++ b/N2/2.hdr @@ -1,2 +1,4 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline diff --git a/N2/2.txt b/N2/2.txt new file mode 100644 index 0000000..d2ea9a6 --- /dev/null +++ b/N2/2.txt @@ -0,0 +1,4 @@ +_______________________________________________ +Xen-devel mailing list +Xen-devel@lists.xenproject.org +https://lists.xenproject.org/mailman/listinfo/xen-devel diff --git a/a/content_digest b/N2/content_digest index 3f3745a..acc7eb0 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,96 +1,96 @@ "ref\043bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" + "Subject\0[Xen-devel] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" "Date\0Fri, 16 Aug 2019 07:26:59 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<rth@twiddle.net>" - <pbonzini@redhat.com> - <mst@redhat.com> - <imammedo@redhat.com> - <marcel.apfelbaum@gmail.com> - <xiaoguangrong.eric@gmail.com> - <alistair@alistair23.me> - <peter.maydell@linaro.org> - <b.galvani@gmail.com> - <clg@kaod.org> - <andrew@aj.id.au> - <joel@jms.id.au> - <i.mitsyanko@gmail.com> - <robh@kernel.org> - <peter.chubb@nicta.com.au> - <sundeep.lkml@gmail.com> - <jan.kiszka@web.de> - <balrogg@gmail.com> - <eric.auger@redhat.com> - <kraxel@redhat.com> - <michael@walle.cc> - <kwolf@redhat.com> - <mreitz@redhat.com> - <jsnow@redhat.com> - <keith.busch@intel.com> - <philmd@redhat.com> - <marcandre.lureau@redhat.com> - <Andrew.Baumann@microsoft.com> - <edgar.iglesias@gmail.com> - <antonynpavlov@gmail.com> - <chouteau@adacore.com> - <frederic.konrad@adacore.com> - <huth@tuxfamily.org> - <mark.cave-ayland@ilande.co.uk> - <hpoussin@reactos.org> - <arikalo@wavecomp.com> - <balaton@eik.bme.hu> - <gxt@mprc.pku.edu.cn> - <david@gibson.dropbear.id.au> - <deller@gmx.de> - <ehabkost@redhat.com> - <sstabellini@kernel.org> - <anthony.perard@citrix.com> - <paul.durrant@citrix.com> - <aurelien@aurel32.net> - <amarkovic@wavecomp.com> - <magnus.damm@gmail.com> - <berto@igalia.com> - <minyard@acm.org> - <pburton@wavecomp.com> - <jslaby@suse.cz> - <jcd@tribudubois.net> - <andrew.smirnov@gmail.com> - <green@moxielogic.com> - <jasowang@redhat.com> - <dmitry.fleytman@gmail.com> - <sw@weilnetz.de> - <jiri@resnulli.us> - <crwulff@gmail.com> - <marex@denx.de> - <lersek@redhat.com> - <proljc@gmail.com> - <shorne@gmail.com> - <yuval.shaia@oracle.com> - <palmer@sifive.com> - <sagark@eecs.berkeley.edu> - <kbastian@mail.uni-paderborn.de> - <walling@linux.ibm.com> - <cohuck@redhat.com> - <david@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <fam@euphon.net> - <hare@suse.com> - <atar4qemu@gmail.com> - <stefanb@linux.ibm.com> - <alex.williamson@redhat.com> - <jcmvbkbc@gmail.com> - <laurent@vivier.eu> - <claudio.fontana@suse.com> - <stefanha@redhat.com> - <qemu-arm@nongnu.org> - <qemu-block@nongnu.org> - <qemu-ppc@nongnu.org> - <xen-devel@lists.xenproject.org> - <qemu-riscv@nongnu.org> - " <qemu-s390x@nongnu.org>\0" - "\01:1\0" + "Cc\0frederic.konrad@adacore.com" + berto@igalia.com + qemu-block@nongnu.org + arikalo@wavecomp.com + pasic@linux.ibm.com + hpoussin@reactos.org + anthony.perard@citrix.com + xen-devel@lists.xenproject.org + lersek@redhat.com + jasowang@redhat.com + jiri@resnulli.us + ehabkost@redhat.com + b.galvani@gmail.com + eric.auger@redhat.com + alex.williamson@redhat.com + stefanha@redhat.com + jsnow@redhat.com + rth@twiddle.net + kwolf@redhat.com + andrew@aj.id.au + claudio.fontana@suse.com + crwulff@gmail.com + laurent@vivier.eu + sundeep.lkml@gmail.com + michael@walle.cc + qemu-ppc@nongnu.org + kbastian@mail.uni-paderborn.de + imammedo@redhat.com + fam@euphon.net + peter.maydell@linaro.org + david@redhat.com + palmer@sifive.com + balaton@eik.bme.hu + keith.busch@intel.com + jcmvbkbc@gmail.com + hare@suse.com + sstabellini@kernel.org + andrew.smirnov@gmail.com + deller@gmx.de + magnus.damm@gmail.com + marcel.apfelbaum@gmail.com + atar4qemu@gmail.com + minyard@acm.org + sw@weilnetz.de + yuval.shaia@oracle.com + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + jan.kiszka@web.de + clg@kaod.org + shorne@gmail.com + qemu-riscv@nongnu.org + i.mitsyanko@gmail.com + cohuck@redhat.com + philmd@redhat.com + amarkovic@wavecomp.com + peter.chubb@nicta.com.au + aurelien@aurel32.net + pburton@wavecomp.com + sagark@eecs.berkeley.edu + green@moxielogic.com + kraxel@redhat.com + edgar.iglesias@gmail.com + gxt@mprc.pku.edu.cn + robh@kernel.org + borntraeger@de.ibm.com + joel@jms.id.au + antonynpavlov@gmail.com + chouteau@adacore.com + balrogg@gmail.com + Andrew.Baumann@microsoft.com + mreitz@redhat.com + walling@linux.ibm.com + dmitry.fleytman@gmail.com + mst@redhat.com + mark.cave-ayland@ilande.co.uk + jslaby@suse.cz + marex@denx.de + proljc@gmail.com + marcandre.lureau@redhat.com + alistair@alistair23.me + paul.durrant@citrix.com + david@gibson.dropbear.id.au + xiaoguangrong.eric@gmail.com + huth@tuxfamily.org + jcd@tribudubois.net + pbonzini@redhat.com + " stefanb@linux.ibm.com\0" + "\02:1.1\0" "b\0" "Preparation for collapsing the two byte swaps, adjust_endianness and\n" "handle_bswap, along the I/O path.\n" @@ -2819,7 +2819,7 @@ "1.8.3.1\n" "\n" ? - "\01:2\0" + "\02:1.2\0" "b\0" "<html>\r\n" "<head>\r\n" @@ -5564,5 +5564,11 @@ "</p>\r\n" "</body>\r\n" "</html>\r\n" + "\01:2\0" + "b\0" + "_______________________________________________\n" + "Xen-devel mailing list\n" + "Xen-devel@lists.xenproject.org\n" + https://lists.xenproject.org/mailman/listinfo/xen-devel -db8536e3ed94cbe04b09d62e3589775b76edac95045071f5f61d3b26de193fa8 +d5b8bc8518eceb3ce8fda7302fb45b1021e26764a1bfbeea963d324fb023b1b5
diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index acf4da8..0000000 --- a/a/2.bin +++ /dev/null @@ -1,2743 +0,0 @@ -<html> -<head> -<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> -<style type="text/css" style="display:none"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style> -</head> -<body dir="ltr" style="font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;"> -<p></p> -<div><span style="font-size: 12pt;">Preparation for collapsing the two byte swaps, adjust_endianness and</span><br> -</div> -<div>handle_bswap, along the I/O path.</div> -<div><br> -</div> -<div>Target dependant attributes are conditionalized upon NEED_CPU_H.</div> -<div><br> -</div> -<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div> -<div>Acked-by: David Gibson <david@gibson.dropbear.id.au></div> -<div>Reviewed-by: Richard Henderson <richard.henderson@linaro.org></div> -<div>Acked-by: Cornelia Huck <cohuck@redhat.com></div> -<div>---</div> -<div> MAINTAINERS | 1 +</div> -<div> accel/tcg/cputlb.c | 2 +-</div> -<div> include/exec/memop.h | 110 ++++++++++++++++++++++++++</div> -<div> target/alpha/translate.c | 2 +-</div> -<div> target/arm/translate-a64.c | 48 ++++++------</div> -<div> target/arm/translate-a64.h | 2 +-</div> -<div> target/arm/translate-sve.c | 2 +-</div> -<div> target/arm/translate.c | 32 ++++----</div> -<div> target/arm/translate.h | 2 +-</div> -<div> target/hppa/translate.c | 14 ++--</div> -<div> target/i386/translate.c | 132 ++++++++++++++++----------------</div> -<div> target/m68k/translate.c | 2 +-</div> -<div> target/microblaze/translate.c | 4 +-</div> -<div> target/mips/translate.c | 8 +-</div> -<div> target/openrisc/translate.c | 4 +-</div> -<div> target/ppc/translate.c | 12 +--</div> -<div> target/riscv/insn_trans/trans_rva.inc.c | 8 +-</div> -<div> target/riscv/insn_trans/trans_rvi.inc.c | 4 +-</div> -<div> target/s390x/translate.c | 6 +-</div> -<div> target/s390x/translate_vx.inc.c | 10 +--</div> -<div> target/sparc/translate.c | 14 ++--</div> -<div> target/tilegx/translate.c | 10 +--</div> -<div> target/tricore/translate.c | 8 +-</div> -<div> tcg/README | 2 +-</div> -<div> tcg/aarch64/tcg-target.inc.c | 26 +++----</div> -<div> tcg/arm/tcg-target.inc.c | 26 +++----</div> -<div> tcg/i386/tcg-target.inc.c | 24 +++---</div> -<div> tcg/mips/tcg-target.inc.c | 16 ++--</div> -<div> tcg/optimize.c | 2 +-</div> -<div> tcg/ppc/tcg-target.inc.c | 12 +--</div> -<div> tcg/riscv/tcg-target.inc.c | 20 ++---</div> -<div> tcg/s390/tcg-target.inc.c | 14 ++--</div> -<div> tcg/sparc/tcg-target.inc.c | 6 +-</div> -<div> tcg/tcg-op.c | 38 ++++-----</div> -<div> tcg/tcg-op.h | 86 ++++++++++-----------</div> -<div> tcg/tcg.c | 2 +-</div> -<div> tcg/tcg.h | 101 ++----------------------</div> -<div> trace/mem-internal.h | 4 +-</div> -<div> trace/mem.h | 4 +-</div> -<div> 39 files changed, 421 insertions(+), 399 deletions(-)</div> -<div> create mode 100644 include/exec/memop.h</div> -<div><br> -</div> -<div>diff --git a/MAINTAINERS b/MAINTAINERS</div> -<div>index d6de200..c7cf84a 100644</div> -<div>--- a/MAINTAINERS</div> -<div>+++ b/MAINTAINERS</div> -<div>@@ -1889,6 +1889,7 @@ M: Paolo Bonzini <pbonzini@redhat.com></div> -<div> S: Supported</div> -<div> F: include/exec/ioport.h</div> -<div> F: ioport.c</div> -<div>+F: include/exec/memop.h</div> -<div> F: include/exec/memory.h</div> -<div> F: include/exec/ram_addr.h</div> -<div> F: memory.c</div> -<div>diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c</div> -<div>index bb9897b..523be4c 100644</div> -<div>--- a/accel/tcg/cputlb.c</div> -<div>+++ b/accel/tcg/cputlb.c</div> -<div>@@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,</div> -<div> uintptr_t index = tlb_index(env, mmu_idx, addr);</div> -<div> CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);</div> -<div> target_ulong tlb_addr = tlb_addr_write(tlbe);</div> -<div>- TCGMemOp mop = get_memop(oi);</div> -<div>+ MemOp mop = get_memop(oi);</div> -<div> int a_bits = get_alignment_bits(mop);</div> -<div> int s_bits = mop & MO_SIZE;</div> -<div> void *hostaddr;</div> -<div>diff --git a/include/exec/memop.h b/include/exec/memop.h</div> -<div>new file mode 100644</div> -<div>index 0000000..7262ca3</div> -<div>--- /dev/null</div> -<div>+++ b/include/exec/memop.h</div> -<div>@@ -0,0 +1,110 @@</div> -<div>+/*</div> -<div>+ * Constants for memory operations</div> -<div>+ *</div> -<div>+ * Authors:</div> -<div>+ * Richard Henderson <rth@twiddle.net></div> -<div>+ *</div> -<div>+ * This work is licensed under the terms of the GNU GPL, version 2 or later.</div> -<div>+ * See the COPYING file in the top-level directory.</div> -<div>+ *</div> -<div>+ */</div> -<div>+</div> -<div>+#ifndef MEMOP_H</div> -<div>+#define MEMOP_H</div> -<div>+</div> -<div>+typedef enum MemOp {</div> -<div>+ MO_8 = 0,</div> -<div>+ MO_16 = 1,</div> -<div>+ MO_32 = 2,</div> -<div>+ MO_64 = 3,</div> -<div>+ MO_SIZE = 3, /* Mask for the above. */</div> -<div>+</div> -<div>+ MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */</div> -<div>+</div> -<div>+ MO_BSWAP = 8, /* Host reverse endian. */</div> -<div>+#ifdef HOST_WORDS_BIGENDIAN</div> -<div>+ MO_LE = MO_BSWAP,</div> -<div>+ MO_BE = 0,</div> -<div>+#else</div> -<div>+ MO_LE = 0,</div> -<div>+ MO_BE = MO_BSWAP,</div> -<div>+#endif</div> -<div>+#ifdef NEED_CPU_H</div> -<div>+#ifdef TARGET_WORDS_BIGENDIAN</div> -<div>+ MO_TE = MO_BE,</div> -<div>+#else</div> -<div>+ MO_TE = MO_LE,</div> -<div>+#endif</div> -<div>+#endif</div> -<div>+</div> -<div>+ /*</div> -<div>+ * MO_UNALN accesses are never checked for alignment.</div> -<div>+ * MO_ALIGN accesses will result in a call to the CPU's</div> -<div>+ * do_unaligned_access hook if the guest address is not aligned.</div> -<div>+ * The default depends on whether the target CPU defines</div> -<div>+ * TARGET_ALIGNED_ONLY.</div> -<div>+ *</div> -<div>+ * Some architectures (e.g. ARMv8) need the address which is aligned</div> -<div>+ * to a size more than the size of the memory access.</div> -<div>+ * Some architectures (e.g. SPARCv9) need an address which is aligned,</div> -<div>+ * but less strictly than the natural alignment.</div> -<div>+ *</div> -<div>+ * MO_ALIGN supposes the alignment size is the size of a memory access.</div> -<div>+ *</div> -<div>+ * There are three options:</div> -<div>+ * - unaligned access permitted (MO_UNALN).</div> -<div>+ * - an alignment to the size of an access (MO_ALIGN);</div> -<div>+ * - an alignment to a specified size, which may be more or less than</div> -<div>+ * the access size (MO_ALIGN_x where 'x' is a size in bytes);</div> -<div>+ */</div> -<div>+ MO_ASHIFT = 4,</div> -<div>+ MO_AMASK = 7 << MO_ASHIFT,</div> -<div>+#ifdef NEED_CPU_H</div> -<div>+#ifdef TARGET_ALIGNED_ONLY</div> -<div>+ MO_ALIGN = 0,</div> -<div>+ MO_UNALN = MO_AMASK,</div> -<div>+#else</div> -<div>+ MO_ALIGN = MO_AMASK,</div> -<div>+ MO_UNALN = 0,</div> -<div>+#endif</div> -<div>+#endif</div> -<div>+ MO_ALIGN_2 = 1 << MO_ASHIFT,</div> -<div>+ MO_ALIGN_4 = 2 << MO_ASHIFT,</div> -<div>+ MO_ALIGN_8 = 3 << MO_ASHIFT,</div> -<div>+ MO_ALIGN_16 = 4 << MO_ASHIFT,</div> -<div>+ MO_ALIGN_32 = 5 << MO_ASHIFT,</div> -<div>+ MO_ALIGN_64 = 6 << MO_ASHIFT,</div> -<div>+</div> -<div>+ /* Combinations of the above, for ease of use. */</div> -<div>+ MO_UB = MO_8,</div> -<div>+ MO_UW = MO_16,</div> -<div>+ MO_UL = MO_32,</div> -<div>+ MO_SB = MO_SIGN | MO_8,</div> -<div>+ MO_SW = MO_SIGN | MO_16,</div> -<div>+ MO_SL = MO_SIGN | MO_32,</div> -<div>+ MO_Q = MO_64,</div> -<div>+</div> -<div>+ MO_LEUW = MO_LE | MO_UW,</div> -<div>+ MO_LEUL = MO_LE | MO_UL,</div> -<div>+ MO_LESW = MO_LE | MO_SW,</div> -<div>+ MO_LESL = MO_LE | MO_SL,</div> -<div>+ MO_LEQ = MO_LE | MO_Q,</div> -<div>+</div> -<div>+ MO_BEUW = MO_BE | MO_UW,</div> -<div>+ MO_BEUL = MO_BE | MO_UL,</div> -<div>+ MO_BESW = MO_BE | MO_SW,</div> -<div>+ MO_BESL = MO_BE | MO_SL,</div> -<div>+ MO_BEQ = MO_BE | MO_Q,</div> -<div>+</div> -<div>+#ifdef NEED_CPU_H</div> -<div>+ MO_TEUW = MO_TE | MO_UW,</div> -<div>+ MO_TEUL = MO_TE | MO_UL,</div> -<div>+ MO_TESW = MO_TE | MO_SW,</div> -<div>+ MO_TESL = MO_TE | MO_SL,</div> -<div>+ MO_TEQ = MO_TE | MO_Q,</div> -<div>+#endif</div> -<div>+</div> -<div>+ MO_SSIZE = MO_SIZE | MO_SIGN,</div> -<div>+} MemOp;</div> -<div>+</div> -<div>+#endif</div> -<div>diff --git a/target/alpha/translate.c b/target/alpha/translate.c</div> -<div>index 2c9cccf..d5d4888 100644</div> -<div>--- a/target/alpha/translate.c</div> -<div>+++ b/target/alpha/translate.c</div> -<div>@@ -403,7 +403,7 @@ static inline void gen_store_mem(DisasContext *ctx,</div> -<div> </div> -<div> static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,</div> -<div> int32_t disp16, int mem_idx,</div> -<div>- TCGMemOp op)</div> -<div>+ MemOp op)</div> -<div> {</div> -<div> TCGLabel *lab_fail, *lab_done;</div> -<div> TCGv addr, val;</div> -<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div> -<div>index d323147..b6c07d6 100644</div> -<div>--- a/target/arm/translate-a64.c</div> -<div>+++ b/target/arm/translate-a64.c</div> -<div>@@ -85,7 +85,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);</div> -<div> typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);</div> -<div> typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);</div> -<div> typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);</div> -<div>-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);</div> -<div> </div> -<div> /* initialize TCG globals. */</div> -<div> void a64_translate_init(void)</div> -<div>@@ -455,7 +455,7 @@ TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)</div> -<div> * Dn, Sn, Hn or Bn).</div> -<div> * (Note that this is not the same mapping as for A32; see cpu.h)</div> -<div> */</div> -<div>-static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)</div> -<div>+static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size)</div> -<div> {</div> -<div> return vec_reg_offset(s, regno, 0, size);</div> -<div> }</div> -<div>@@ -871,7 +871,7 @@ static void do_gpr_ld_memidx(DisasContext *s,</div> -<div> bool iss_valid, unsigned int iss_srt,</div> -<div> bool iss_sf, bool iss_ar)</div> -<div> {</div> -<div>- TCGMemOp memop = s->be_data + size;</div> -<div>+ MemOp memop = s->be_data + size;</div> -<div> </div> -<div> g_assert(size <= 3);</div> -<div> </div> -<div>@@ -948,7 +948,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div> -<div> TCGv_i64 tmphi;</div> -<div> </div> -<div> if (size < 4) {</div> -<div>- TCGMemOp memop = s->be_data + size;</div> -<div>+ MemOp memop = s->be_data + size;</div> -<div> tmphi = tcg_const_i64(0);</div> -<div> tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);</div> -<div> } else {</div> -<div>@@ -989,7 +989,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div> -<div> </div> -<div> /* Get value of an element within a vector register */</div> -<div> static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div>- int element, TCGMemOp memop)</div> -<div>+ int element, MemOp memop)</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>@@ -1021,7 +1021,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div> -<div> }</div> -<div> </div> -<div> static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div> -<div>- int element, TCGMemOp memop)</div> -<div>+ int element, MemOp memop)</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>@@ -1048,7 +1048,7 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div> -<div> </div> -<div> /* Set value of an element within a vector register */</div> -<div> static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div>- int element, TCGMemOp memop)</div> -<div>+ int element, MemOp memop)</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>@@ -1070,7 +1070,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div> -<div> }</div> -<div> </div> -<div> static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div> -<div>- int destidx, int element, TCGMemOp memop)</div> -<div>+ int destidx, int element, MemOp memop)</div> -<div> {</div> -<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div> -<div> switch (memop) {</div> -<div>@@ -1090,7 +1090,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div> -<div> </div> -<div> /* Store from vector register to memory */</div> -<div> static void do_vec_st(DisasContext *s, int srcidx, int element,</div> -<div>- TCGv_i64 tcg_addr, int size, TCGMemOp endian)</div> -<div>+ TCGv_i64 tcg_addr, int size, MemOp endian)</div> -<div> {</div> -<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div> -<div> </div> -<div>@@ -1102,7 +1102,7 @@ static void do_vec_st(DisasContext *s, int srcidx, int element,</div> -<div> </div> -<div> /* Load from memory to vector register */</div> -<div> static void do_vec_ld(DisasContext *s, int destidx, int element,</div> -<div>- TCGv_i64 tcg_addr, int size, TCGMemOp endian)</div> -<div>+ TCGv_i64 tcg_addr, int size, MemOp endian)</div> -<div> {</div> -<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div> -<div> </div> -<div>@@ -2200,7 +2200,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div> -<div> TCGv_i64 addr, int size, bool is_pair)</div> -<div> {</div> -<div> int idx = get_mem_index(s);</div> -<div>- TCGMemOp memop = s->be_data;</div> -<div>+ MemOp memop = s->be_data;</div> -<div> </div> -<div> g_assert(size <= 3);</div> -<div> if (is_pair) {</div> -<div>@@ -3286,7 +3286,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)</div> -<div> bool is_postidx = extract32(insn, 23, 1);</div> -<div> bool is_q = extract32(insn, 30, 1);</div> -<div> TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;</div> -<div>- TCGMemOp endian = s->be_data;</div> -<div>+ MemOp endian = s->be_data;</div> -<div> </div> -<div> int ebytes; /* bytes per element */</div> -<div> int elements; /* elements per vector */</div> -<div>@@ -5455,7 +5455,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div> -<div> unsigned int mos, type, rm, cond, rn, rd;</div> -<div> TCGv_i64 t_true, t_false, t_zero;</div> -<div> DisasCompare64 c;</div> -<div>- TCGMemOp sz;</div> -<div>+ MemOp sz;</div> -<div> </div> -<div> mos = extract32(insn, 29, 3);</div> -<div> type = extract32(insn, 22, 2);</div> -<div>@@ -6267,7 +6267,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div> -<div> int mos = extract32(insn, 29, 3);</div> -<div> uint64_t imm;</div> -<div> TCGv_i64 tcg_res;</div> -<div>- TCGMemOp sz;</div> -<div>+ MemOp sz;</div> -<div> </div> -<div> if (mos || imm5) {</div> -<div> unallocated_encoding(s);</div> -<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div> -<div> {</div> -<div> if (esize == size) {</div> -<div> int element;</div> -<div>- TCGMemOp msize = esize == 16 ? MO_16 : MO_32;</div> -<div>+ MemOp msize = esize == 16 ? MO_16 : MO_32;</div> -<div> TCGv_i32 tcg_elem;</div> -<div> </div> -<div> /* We should have one register left here */</div> -<div>@@ -8022,7 +8022,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,</div> -<div> int shift = (2 * esize) - immhb;</div> -<div> int elements = is_scalar ? 1 : (64 / esize);</div> -<div> bool round = extract32(opcode, 0, 1);</div> -<div>- TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);</div> -<div>+ MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);</div> -<div> TCGv_i64 tcg_rn, tcg_rd, tcg_round;</div> -<div> TCGv_i32 tcg_rd_narrowed;</div> -<div> TCGv_i64 tcg_final;</div> -<div>@@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div> -<div> }</div> -<div> };</div> -<div> NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];</div> -<div>- TCGMemOp memop = scalar ? size : MO_32;</div> -<div>+ MemOp memop = scalar ? size : MO_32;</div> -<div> int maxpass = scalar ? 1 : is_q ? 4 : 2;</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div>@@ -8225,7 +8225,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div> -<div> TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);</div> -<div> TCGv_i32 tcg_shift = NULL;</div> -<div> </div> -<div>- TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div> -<div>+ MemOp mop = size | (is_signed ? MO_SIGN : 0);</div> -<div> int pass;</div> -<div> </div> -<div> if (fracbits || size == MO_64) {</div> -<div>@@ -10004,7 +10004,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,</div> -<div> int dsize = is_q ? 128 : 64;</div> -<div> int esize = 8 << size;</div> -<div> int elements = dsize/esize;</div> -<div>- TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);</div> -<div>+ MemOp memop = size | (is_u ? 0 : MO_SIGN);</div> -<div> TCGv_i64 tcg_rn = new_tmp_a64(s);</div> -<div> TCGv_i64 tcg_rd = new_tmp_a64(s);</div> -<div> TCGv_i64 tcg_round;</div> -<div>@@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div> -<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div> -<div> TCGv_i64 tcg_passres;</div> -<div>- TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div> -<div>+ MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div> -<div> </div> -<div> int elt = pass + is_q * 2;</div> -<div> </div> -<div>@@ -11827,7 +11827,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div> -<div> </div> -<div> if (size == 2) {</div> -<div> /* 32 + 32 -> 64 op */</div> -<div>- TCGMemOp memop = size + (u ? 0 : MO_SIGN);</div> -<div>+ MemOp memop = size + (u ? 0 : MO_SIGN);</div> -<div> </div> -<div> for (pass = 0; pass < maxpass; pass++) {</div> -<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div> -<div>@@ -12849,7 +12849,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> </div> -<div> switch (is_fp) {</div> -<div> case 1: /* normal fp */</div> -<div>- /* convert insn encoded size to TCGMemOp size */</div> -<div>+ /* convert insn encoded size to MemOp size */</div> -<div> switch (size) {</div> -<div> case 0: /* half-precision */</div> -<div> size = MO_16;</div> -<div>@@ -12897,7 +12897,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> return;</div> -<div> }</div> -<div> </div> -<div>- /* Given TCGMemOp size, adjust register and indexing. */</div> -<div>+ /* Given MemOp size, adjust register and indexing. */</div> -<div> switch (size) {</div> -<div> case MO_16:</div> -<div> index = h << 2 | l << 1 | m;</div> -<div>@@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div> -<div> TCGv_i64 tcg_res[2];</div> -<div> int pass;</div> -<div> bool satop = extract32(opcode, 0, 1);</div> -<div>- TCGMemOp memop = MO_32;</div> -<div>+ MemOp memop = MO_32;</div> -<div> </div> -<div> if (satop || !u) {</div> -<div> memop |= MO_SIGN;</div> -<div>diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h</div> -<div>index 9ab4087..f1246b7 100644</div> -<div>--- a/target/arm/translate-a64.h</div> -<div>+++ b/target/arm/translate-a64.h</div> -<div>@@ -64,7 +64,7 @@ static inline void assert_fp_access_checked(DisasContext *s)</div> -<div> * the FP/vector register Qn.</div> -<div> */</div> -<div> static inline int vec_reg_offset(DisasContext *s, int regno,</div> -<div>- int element, TCGMemOp size)</div> -<div>+ int element, MemOp size)</div> -<div> {</div> -<div> int element_size = 1 << size;</div> -<div> int offs = element * element_size;</div> -<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div> -<div>index fa068b0..5d7edd0 100644</div> -<div>--- a/target/arm/translate-sve.c</div> -<div>+++ b/target/arm/translate-sve.c</div> -<div>@@ -4567,7 +4567,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)</div> -<div> */</div> -<div> </div> -<div> /* The memory mode of the dtype. */</div> -<div>-static const TCGMemOp dtype_mop[16] = {</div> -<div>+static const MemOp dtype_mop[16] = {</div> -<div> MO_UB, MO_UB, MO_UB, MO_UB,</div> -<div> MO_SL, MO_UW, MO_UW, MO_UW,</div> -<div> MO_SW, MO_SW, MO_UL, MO_UL,</div> -<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div> -<div>index 7853462..d116c8c 100644</div> -<div>--- a/target/arm/translate.c</div> -<div>+++ b/target/arm/translate.c</div> -<div>@@ -114,7 +114,7 @@ typedef enum ISSInfo {</div> -<div> } ISSInfo;</div> -<div> </div> -<div> /* Save the syndrome information for a Data Abort */</div> -<div>-static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)</div> -<div>+static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo)</div> -<div> {</div> -<div> uint32_t syn;</div> -<div> int sas = memop & MO_SIZE;</div> -<div>@@ -1079,7 +1079,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)</div> -<div> * that the address argument is TCGv_i32 rather than TCGv.</div> -<div> */</div> -<div> </div> -<div>-static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div> -<div>+static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)</div> -<div> {</div> -<div> TCGv addr = tcg_temp_new();</div> -<div> tcg_gen_extu_i32_tl(addr, a32);</div> -<div>@@ -1092,7 +1092,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div> -<div> }</div> -<div> </div> -<div> static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div> -<div>- int index, TCGMemOp opc)</div> -<div>+ int index, MemOp opc)</div> -<div> {</div> -<div> TCGv addr;</div> -<div> </div> -<div>@@ -1107,7 +1107,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div> -<div> }</div> -<div> </div> -<div> static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div> -<div>- int index, TCGMemOp opc)</div> -<div>+ int index, MemOp opc)</div> -<div> {</div> -<div> TCGv addr;</div> -<div> </div> -<div>@@ -1160,7 +1160,7 @@ static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)</div> -<div> }</div> -<div> </div> -<div> static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div> -<div>- int index, TCGMemOp opc)</div> -<div>+ int index, MemOp opc)</div> -<div> {</div> -<div> TCGv addr = gen_aa32_addr(s, a32, opc);</div> -<div> tcg_gen_qemu_ld_i64(val, addr, index, opc);</div> -<div>@@ -1175,7 +1175,7 @@ static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,</div> -<div> }</div> -<div> </div> -<div> static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div> -<div>- int index, TCGMemOp opc)</div> -<div>+ int index, MemOp opc)</div> -<div> {</div> -<div> TCGv addr = gen_aa32_addr(s, a32, opc);</div> -<div> </div> -<div>@@ -1400,7 +1400,7 @@ neon_reg_offset (int reg, int n)</div> -<div> * where 0 is the least significant end of the register.</div> -<div> */</div> -<div> static inline long</div> -<div>-neon_element_offset(int reg, int element, TCGMemOp size)</div> -<div>+neon_element_offset(int reg, int element, MemOp size)</div> -<div> {</div> -<div> int element_size = 1 << size;</div> -<div> int ofs = element * element_size;</div> -<div>@@ -1422,7 +1422,7 @@ static TCGv_i32 neon_load_reg(int reg, int pass)</div> -<div> return tmp;</div> -<div> }</div> -<div> </div> -<div>-static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)</div> -<div>+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)</div> -<div> {</div> -<div> long offset = neon_element_offset(reg, ele, mop & MO_SIZE);</div> -<div> </div> -<div>@@ -1441,7 +1441,7 @@ static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)</div> -<div>+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)</div> -<div> {</div> -<div> long offset = neon_element_offset(reg, ele, mop & MO_SIZE);</div> -<div> </div> -<div>@@ -1469,7 +1469,7 @@ static void neon_store_reg(int reg, int pass, TCGv_i32 var)</div> -<div> tcg_temp_free_i32(var);</div> -<div> }</div> -<div> </div> -<div>-static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div> -<div>+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)</div> -<div> {</div> -<div> long offset = neon_element_offset(reg, ele, size);</div> -<div> </div> -<div>@@ -1488,7 +1488,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div> -<div>+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)</div> -<div> {</div> -<div> long offset = neon_element_offset(reg, ele, size);</div> -<div> </div> -<div>@@ -3558,7 +3558,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)</div> -<div> int n;</div> -<div> int vec_size;</div> -<div> int mmu_idx;</div> -<div>- TCGMemOp endian;</div> -<div>+ MemOp endian;</div> -<div> TCGv_i32 addr;</div> -<div> TCGv_i32 tmp;</div> -<div> TCGv_i32 tmp2;</div> -<div>@@ -6867,7 +6867,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div> -<div> } else if ((insn & 0x380) == 0) {</div> -<div> /* VDUP */</div> -<div> int element;</div> -<div>- TCGMemOp size;</div> -<div>+ MemOp size;</div> -<div> </div> -<div> if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {</div> -<div> return 1;</div> -<div>@@ -7435,7 +7435,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div> -<div> TCGv_i32 addr, int size)</div> -<div> {</div> -<div> TCGv_i32 tmp = tcg_temp_new_i32();</div> -<div>- TCGMemOp opc = size | MO_ALIGN | s->be_data;</div> -<div>+ MemOp opc = size | MO_ALIGN | s->be_data;</div> -<div> </div> -<div> s->is_ldex = true;</div> -<div> </div> -<div>@@ -7489,7 +7489,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,</div> -<div> TCGv taddr;</div> -<div> TCGLabel *done_label;</div> -<div> TCGLabel *fail_label;</div> -<div>- TCGMemOp opc = size | MO_ALIGN | s->be_data;</div> -<div>+ MemOp opc = size | MO_ALIGN | s->be_data;</div> -<div> </div> -<div> /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {</div> -<div> [addr] = {Rt};</div> -<div>@@ -8603,7 +8603,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)</div> -<div> */</div> -<div> </div> -<div> TCGv taddr;</div> -<div>- TCGMemOp opc = s->be_data;</div> -<div>+ MemOp opc = s->be_data;</div> -<div> </div> -<div> rm = (insn) & 0xf;</div> -<div> </div> -<div>diff --git a/target/arm/translate.h b/target/arm/translate.h</div> -<div>index a20f6e2..284c510 100644</div> -<div>--- a/target/arm/translate.h</div> -<div>+++ b/target/arm/translate.h</div> -<div>@@ -21,7 +21,7 @@ typedef struct DisasContext {</div> -<div> int condexec_cond;</div> -<div> int thumb;</div> -<div> int sctlr_b;</div> -<div>- TCGMemOp be_data;</div> -<div>+ MemOp be_data;</div> -<div> #if !defined(CONFIG_USER_ONLY)</div> -<div> int user;</div> -<div> #endif</div> -<div>diff --git a/target/hppa/translate.c b/target/hppa/translate.c</div> -<div>index 188fe68..ff4802a 100644</div> -<div>--- a/target/hppa/translate.c</div> -<div>+++ b/target/hppa/translate.c</div> -<div>@@ -1500,7 +1500,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,</div> -<div> */</div> -<div> static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,</div> -<div> unsigned rx, int scale, target_sreg disp,</div> -<div>- unsigned sp, int modify, TCGMemOp mop)</div> -<div>+ unsigned sp, int modify, MemOp mop)</div> -<div> {</div> -<div> TCGv_reg ofs;</div> -<div> TCGv_tl addr;</div> -<div>@@ -1518,7 +1518,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,</div> -<div> </div> -<div> static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,</div> -<div> unsigned rx, int scale, target_sreg disp,</div> -<div>- unsigned sp, int modify, TCGMemOp mop)</div> -<div>+ unsigned sp, int modify, MemOp mop)</div> -<div> {</div> -<div> TCGv_reg ofs;</div> -<div> TCGv_tl addr;</div> -<div>@@ -1536,7 +1536,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,</div> -<div> </div> -<div> static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,</div> -<div> unsigned rx, int scale, target_sreg disp,</div> -<div>- unsigned sp, int modify, TCGMemOp mop)</div> -<div>+ unsigned sp, int modify, MemOp mop)</div> -<div> {</div> -<div> TCGv_reg ofs;</div> -<div> TCGv_tl addr;</div> -<div>@@ -1554,7 +1554,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,</div> -<div> </div> -<div> static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,</div> -<div> unsigned rx, int scale, target_sreg disp,</div> -<div>- unsigned sp, int modify, TCGMemOp mop)</div> -<div>+ unsigned sp, int modify, MemOp mop)</div> -<div> {</div> -<div> TCGv_reg ofs;</div> -<div> TCGv_tl addr;</div> -<div>@@ -1580,7 +1580,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,</div> -<div> </div> -<div> static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,</div> -<div> unsigned rx, int scale, target_sreg disp,</div> -<div>- unsigned sp, int modify, TCGMemOp mop)</div> -<div>+ unsigned sp, int modify, MemOp mop)</div> -<div> {</div> -<div> TCGv_reg dest;</div> -<div> </div> -<div>@@ -1653,7 +1653,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a)</div> -<div> </div> -<div> static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,</div> -<div> target_sreg disp, unsigned sp,</div> -<div>- int modify, TCGMemOp mop)</div> -<div>+ int modify, MemOp mop)</div> -<div> {</div> -<div> nullify_over(ctx);</div> -<div> do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);</div> -<div>@@ -2940,7 +2940,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)</div> -<div> </div> -<div> static bool trans_ldc(DisasContext *ctx, arg_ldst *a)</div> -<div> {</div> -<div>- TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;</div> -<div>+ MemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;</div> -<div> TCGv_reg zero, dest, ofs;</div> -<div> TCGv_tl addr;</div> -<div> </div> -<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div> -<div>index 03150a8..def9867 100644</div> -<div>--- a/target/i386/translate.c</div> -<div>+++ b/target/i386/translate.c</div> -<div>@@ -87,8 +87,8 @@ typedef struct DisasContext {</div> -<div> /* current insn context */</div> -<div> int override; /* -1 if no override */</div> -<div> int prefix;</div> -<div>- TCGMemOp aflag;</div> -<div>- TCGMemOp dflag;</div> -<div>+ MemOp aflag;</div> -<div>+ MemOp dflag;</div> -<div> target_ulong pc_start;</div> -<div> target_ulong pc; /* pc = eip + cs_base */</div> -<div> /* current block context */</div> -<div>@@ -149,7 +149,7 @@ static void gen_eob(DisasContext *s);</div> -<div> static void gen_jr(DisasContext *s, TCGv dest);</div> -<div> static void gen_jmp(DisasContext *s, target_ulong eip);</div> -<div> static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);</div> -<div>-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);</div> -<div>+static void gen_op(DisasContext *s1, int op, MemOp ot, int d);</div> -<div> </div> -<div> /* i386 arith/logic operations */</div> -<div> enum {</div> -<div>@@ -320,7 +320,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div> -<div> }</div> -<div> </div> -<div> /* Select the size of a push/pop operation. */</div> -<div>-static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline MemOp mo_pushpop(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> if (CODE64(s)) {</div> -<div> return ot == MO_16 ? MO_16 : MO_64;</div> -<div>@@ -330,13 +330,13 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div> -<div> }</div> -<div> </div> -<div> /* Select the size of the stack pointer. */</div> -<div>-static inline TCGMemOp mo_stacksize(DisasContext *s)</div> -<div>+static inline MemOp mo_stacksize(DisasContext *s)</div> -<div> {</div> -<div> return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div> -<div> }</div> -<div> </div> -<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div> -<div>-static inline TCGMemOp mo_64_32(TCGMemOp ot)</div> -<div>+static inline MemOp mo_64_32(MemOp ot)</div> -<div> {</div> -<div> #ifdef TARGET_X86_64</div> -<div> return ot == MO_64 ? MO_64 : MO_32;</div> -<div>@@ -347,19 +347,19 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot)</div> -<div> </div> -<div> /* Select size 8 if lsb of B is clear, else OT. Used for decoding</div> -<div> byte vs word opcodes. */</div> -<div>-static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div> -<div>+static inline MemOp mo_b_d(int b, MemOp ot)</div> -<div> {</div> -<div> return b & 1 ? ot : MO_8;</div> -<div> }</div> -<div> </div> -<div> /* Select size 8 if lsb of B is clear, else OT capped at 32.</div> -<div> Used for decoding operand size of port opcodes. */</div> -<div>-static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div> -<div>+static inline MemOp mo_b_d32(int b, MemOp ot)</div> -<div> {</div> -<div> return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;</div> -<div> }</div> -<div> </div> -<div>-static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div>+static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0)</div> -<div> {</div> -<div> switch(ot) {</div> -<div> case MO_8:</div> -<div>@@ -388,7 +388,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div> -<div> }</div> -<div> </div> -<div> static inline</div> -<div>-void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg)</div> -<div>+void gen_op_mov_v_reg(DisasContext *s, MemOp ot, TCGv t0, int reg)</div> -<div> {</div> -<div> if (ot == MO_8 && byte_reg_is_xH(s, reg)) {</div> -<div> tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);</div> -<div>@@ -411,13 +411,13 @@ static inline void gen_op_jmp_v(TCGv dest)</div> -<div> }</div> -<div> </div> -<div> static inline</div> -<div>-void gen_op_add_reg_im(DisasContext *s, TCGMemOp size, int reg, int32_t val)</div> -<div>+void gen_op_add_reg_im(DisasContext *s, MemOp size, int reg, int32_t val)</div> -<div> {</div> -<div> tcg_gen_addi_tl(s->tmp0, cpu_regs[reg], val);</div> -<div> gen_op_mov_reg_v(s, size, reg, s->tmp0);</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_op_add_reg_T0(DisasContext *s, TCGMemOp size, int reg)</div> -<div>+static inline void gen_op_add_reg_T0(DisasContext *s, MemOp size, int reg)</div> -<div> {</div> -<div> tcg_gen_add_tl(s->tmp0, cpu_regs[reg], s->T0);</div> -<div> gen_op_mov_reg_v(s, size, reg, s->tmp0);</div> -<div>@@ -451,7 +451,7 @@ static inline void gen_jmp_im(DisasContext *s, target_ulong pc)</div> -<div> /* Compute SEG:REG into A0. SEG is selected from the override segment</div> -<div> (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to</div> -<div> indicate no override. */</div> -<div>-static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div> -<div>+static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,</div> -<div> int def_seg, int ovr_seg)</div> -<div> {</div> -<div> switch (aflag) {</div> -<div>@@ -514,13 +514,13 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)</div> -<div> gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1);</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df));</div> -<div> tcg_gen_shli_tl(s->T0, s->T0, ot);</div> -<div> };</div> -<div> </div> -<div>-static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div> -<div>+static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)</div> -<div> {</div> -<div> switch (size) {</div> -<div> case MO_8:</div> -<div>@@ -551,18 +551,18 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_extu(TCGMemOp ot, TCGv reg)</div> -<div>+static void gen_extu(MemOp ot, TCGv reg)</div> -<div> {</div> -<div> gen_ext_tl(reg, reg, ot, false);</div> -<div> }</div> -<div> </div> -<div>-static void gen_exts(TCGMemOp ot, TCGv reg)</div> -<div>+static void gen_exts(MemOp ot, TCGv reg)</div> -<div> {</div> -<div> gen_ext_tl(reg, reg, ot, true);</div> -<div> }</div> -<div> </div> -<div> static inline</div> -<div>-void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div> -<div>+void gen_op_jnz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)</div> -<div> {</div> -<div> tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);</div> -<div> gen_extu(size, s->tmp0);</div> -<div>@@ -570,14 +570,14 @@ void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div> -<div> }</div> -<div> </div> -<div> static inline</div> -<div>-void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div> -<div>+void gen_op_jz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)</div> -<div> {</div> -<div> tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);</div> -<div> gen_extu(size, s->tmp0);</div> -<div> tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1);</div> -<div> }</div> -<div> </div> -<div>-static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div>+static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n)</div> -<div> {</div> -<div> switch (ot) {</div> -<div> case MO_8:</div> -<div>@@ -594,7 +594,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div>+static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div> {</div> -<div> switch (ot) {</div> -<div> case MO_8:</div> -<div>@@ -611,7 +611,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div> -<div>+static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip,</div> -<div> uint32_t svm_flags)</div> -<div> {</div> -<div> target_ulong next_eip;</div> -<div>@@ -644,7 +644,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_movs(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_movs(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_string_movl_A0_ESI(s);</div> -<div> gen_op_ld_v(s, ot, s->T0, s->A0);</div> -<div>@@ -840,7 +840,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)</div> -<div> return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };</div> -<div> default:</div> -<div> {</div> -<div>- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div> -<div>+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div> -<div> TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);</div> -<div> return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };</div> -<div> }</div> -<div>@@ -885,7 +885,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)</div> -<div> .mask = -1 };</div> -<div> default:</div> -<div> {</div> -<div>- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div> -<div>+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div> -<div> TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);</div> -<div> return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };</div> -<div> }</div> -<div>@@ -897,7 +897,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)</div> -<div> static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)</div> -<div> {</div> -<div> int inv, jcc_op, cond;</div> -<div>- TCGMemOp size;</div> -<div>+ MemOp size;</div> -<div> CCPrepare cc;</div> -<div> TCGv t0;</div> -<div> </div> -<div>@@ -1075,7 +1075,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)</div> -<div> return l2;</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_stos(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div> -<div> gen_string_movl_A0_EDI(s);</div> -<div>@@ -1084,7 +1084,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div> -<div> gen_op_add_reg_T0(s, s->aflag, R_EDI);</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_lods(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_lods(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_string_movl_A0_ESI(s);</div> -<div> gen_op_ld_v(s, ot, s->T0, s->A0);</div> -<div>@@ -1093,7 +1093,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)</div> -<div> gen_op_add_reg_T0(s, s->aflag, R_ESI);</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_scas(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_scas(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_string_movl_A0_EDI(s);</div> -<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div> -<div>@@ -1102,7 +1102,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)</div> -<div> gen_op_add_reg_T0(s, s->aflag, R_EDI);</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_cmps(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_cmps(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_string_movl_A0_EDI(s);</div> -<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div> -<div>@@ -1126,7 +1126,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)</div> -<div> }</div> -<div> </div> -<div> </div> -<div>-static inline void gen_ins(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_ins(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {</div> -<div> gen_io_start();</div> -<div>@@ -1148,7 +1148,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_outs(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_outs(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {</div> -<div> gen_io_start();</div> -<div>@@ -1171,7 +1171,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)</div> -<div> /* same method as Valgrind : we generate jumps to current or next</div> -<div> instruction */</div> -<div> #define GEN_REPZ(op) \</div> -<div>-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \</div> -<div>+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \</div> -<div> target_ulong cur_eip, target_ulong next_eip) \</div> -<div> { \</div> -<div> TCGLabel *l2; \</div> -<div>@@ -1187,7 +1187,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \</div> -<div> }</div> -<div> </div> -<div> #define GEN_REPZ2(op) \</div> -<div>-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \</div> -<div>+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \</div> -<div> target_ulong cur_eip, \</div> -<div> target_ulong next_eip, \</div> -<div> int nz) \</div> -<div>@@ -1284,7 +1284,7 @@ static void gen_illegal_opcode(DisasContext *s)</div> -<div> }</div> -<div> </div> -<div> /* if d == OR_TMP0, it means memory operand (address in A0) */</div> -<div>-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)</div> -<div>+static void gen_op(DisasContext *s1, int op, MemOp ot, int d)</div> -<div> {</div> -<div> if (d != OR_TMP0) {</div> -<div> if (s1->prefix & PREFIX_LOCK) {</div> -<div>@@ -1395,7 +1395,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)</div> -<div> }</div> -<div> </div> -<div> /* if d == OR_TMP0, it means memory operand (address in A0) */</div> -<div>-static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)</div> -<div>+static void gen_inc(DisasContext *s1, MemOp ot, int d, int c)</div> -<div> {</div> -<div> if (s1->prefix & PREFIX_LOCK) {</div> -<div> if (d != OR_TMP0) {</div> -<div>@@ -1421,7 +1421,7 @@ static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)</div> -<div> set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot);</div> -<div> }</div> -<div> </div> -<div>-static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div> -<div>+static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,</div> -<div> TCGv shm1, TCGv count, bool is_right)</div> -<div> {</div> -<div> TCGv_i32 z32, s32, oldop;</div> -<div>@@ -1466,7 +1466,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div> -<div> set_cc_op(s, CC_OP_DYNAMIC);</div> -<div> }</div> -<div> </div> -<div>-static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div>+static void gen_shift_rm_T1(DisasContext *s, MemOp ot, int op1,</div> -<div> int is_right, int is_arith)</div> -<div> {</div> -<div> target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>@@ -1502,7 +1502,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right);</div> -<div> }</div> -<div> </div> -<div>-static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div>+static void gen_shift_rm_im(DisasContext *s, MemOp ot, int op1, int op2,</div> -<div> int is_right, int is_arith)</div> -<div> {</div> -<div> int mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>@@ -1542,7 +1542,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div>+static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)</div> -<div> {</div> -<div> target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div> TCGv_i32 t0, t1;</div> -<div>@@ -1627,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div> -<div> set_cc_op(s, CC_OP_DYNAMIC);</div> -<div> }</div> -<div> </div> -<div>-static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div>+static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2,</div> -<div> int is_right)</div> -<div> {</div> -<div> int mask = (ot == MO_64 ? 0x3f : 0x1f);</div> -<div>@@ -1705,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div> -<div> }</div> -<div> </div> -<div> /* XXX: add faster immediate = 1 case */</div> -<div>-static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div>+static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,</div> -<div> int is_right)</div> -<div> {</div> -<div> gen_compute_eflags(s);</div> -<div>@@ -1761,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> }</div> -<div> </div> -<div> /* XXX: add faster immediate case */</div> -<div>-static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div>+static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,</div> -<div> bool is_right, TCGv count_in)</div> -<div> {</div> -<div> target_ulong mask = (ot == MO_64 ? 63 : 31);</div> -<div>@@ -1842,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div> -<div> tcg_temp_free(count);</div> -<div> }</div> -<div> </div> -<div>-static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)</div> -<div>+static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s)</div> -<div> {</div> -<div> if (s != OR_TMP1)</div> -<div> gen_op_mov_v_reg(s1, ot, s1->T1, s);</div> -<div>@@ -1872,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)</div> -<div>+static void gen_shifti(DisasContext *s1, int op, MemOp ot, int d, int c)</div> -<div> {</div> -<div> switch(op) {</div> -<div> case OP_ROL:</div> -<div>@@ -2149,7 +2149,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)</div> -<div> /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==</div> -<div> OR_TMP0 */</div> -<div> static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,</div> -<div>- TCGMemOp ot, int reg, int is_store)</div> -<div>+ MemOp ot, int reg, int is_store)</div> -<div> {</div> -<div> int mod, rm;</div> -<div> </div> -<div>@@ -2179,7 +2179,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div>+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> uint32_t ret;</div> -<div> </div> -<div>@@ -2202,7 +2202,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div> -<div> return ret;</div> -<div> }</div> -<div> </div> -<div>-static inline int insn_const_size(TCGMemOp ot)</div> -<div>+static inline int insn_const_size(MemOp ot)</div> -<div> {</div> -<div> if (ot <= MO_32) {</div> -<div> return 1 << ot;</div> -<div>@@ -2266,7 +2266,7 @@ static inline void gen_jcc(DisasContext *s, int b,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,</div> -<div>+static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,</div> -<div> int modrm, int reg)</div> -<div> {</div> -<div> CCPrepare cc;</div> -<div>@@ -2363,8 +2363,8 @@ static inline void gen_stack_update(DisasContext *s, int addend)</div> -<div> /* Generate a push. It depends on ss32, addseg and dflag. */</div> -<div> static void gen_push_v(DisasContext *s, TCGv val)</div> -<div> {</div> -<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = mo_stacksize(s);</div> -<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>+ MemOp a_ot = mo_stacksize(s);</div> -<div> int size = 1 << d_ot;</div> -<div> TCGv new_esp = s->A0;</div> -<div> </div> -<div>@@ -2383,9 +2383,9 @@ static void gen_push_v(DisasContext *s, TCGv val)</div> -<div> }</div> -<div> </div> -<div> /* two step pop is necessary for precise exceptions */</div> -<div>-static TCGMemOp gen_pop_T0(DisasContext *s)</div> -<div>+static MemOp gen_pop_T0(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div> </div> -<div> gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1);</div> -<div> gen_op_ld_v(s, d_ot, s->T0, s->A0);</div> -<div>@@ -2393,7 +2393,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s)</div> -<div> return d_ot;</div> -<div> }</div> -<div> </div> -<div>-static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div> -<div>+static inline void gen_pop_update(DisasContext *s, MemOp ot)</div> -<div> {</div> -<div> gen_stack_update(s, 1 << ot);</div> -<div> }</div> -<div>@@ -2405,8 +2405,8 @@ static inline void gen_stack_A0(DisasContext *s)</div> -<div> </div> -<div> static void gen_pusha(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>- TCGMemOp d_ot = s->dflag;</div> -<div>+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>+ MemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div> </div> -<div>@@ -2421,8 +2421,8 @@ static void gen_pusha(DisasContext *s)</div> -<div> </div> -<div> static void gen_popa(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>- TCGMemOp d_ot = s->dflag;</div> -<div>+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;</div> -<div>+ MemOp d_ot = s->dflag;</div> -<div> int size = 1 << d_ot;</div> -<div> int i;</div> -<div> </div> -<div>@@ -2442,8 +2442,8 @@ static void gen_popa(DisasContext *s)</div> -<div> </div> -<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div> -<div> {</div> -<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div> -<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>+ MemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div> -<div> int size = 1 << d_ot;</div> -<div> </div> -<div> /* Push BP; compute FrameTemp into T1. */</div> -<div>@@ -2482,8 +2482,8 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)</div> -<div> </div> -<div> static void gen_leave(DisasContext *s)</div> -<div> {</div> -<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>- TCGMemOp a_ot = mo_stacksize(s);</div> -<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div> -<div>+ MemOp a_ot = mo_stacksize(s);</div> -<div> </div> -<div> gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1);</div> -<div> gen_op_ld_v(s, d_ot, s->T0, s->A0);</div> -<div>@@ -3045,7 +3045,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div> -<div> SSEFunc_0_eppi sse_fn_eppi;</div> -<div> SSEFunc_0_ppi sse_fn_ppi;</div> -<div> SSEFunc_0_eppt sse_fn_eppt;</div> -<div>- TCGMemOp ot;</div> -<div>+ MemOp ot;</div> -<div> </div> -<div> b &= 0xff;</div> -<div> if (s->prefix & PREFIX_DATA)</div> -<div>@@ -4488,7 +4488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> CPUX86State *env = cpu->env_ptr;</div> -<div> int b, prefixes;</div> -<div> int shift;</div> -<div>- TCGMemOp ot, aflag, dflag;</div> -<div>+ MemOp ot, aflag, dflag;</div> -<div> int modrm, reg, rm, mod, op, opreg, val;</div> -<div> target_ulong next_eip, tval;</div> -<div> int rex_w, rex_r;</div> -<div>@@ -5567,8 +5567,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div> -<div> case 0x1be: /* movsbS Gv, Eb */</div> -<div> case 0x1bf: /* movswS Gv, Eb */</div> -<div> {</div> -<div>- TCGMemOp d_ot;</div> -<div>- TCGMemOp s_ot;</div> -<div>+ MemOp d_ot;</div> -<div>+ MemOp s_ot;</div> -<div> </div> -<div> /* d_ot is the size of destination */</div> -<div> d_ot = dflag;</div> -<div>diff --git a/target/m68k/translate.c b/target/m68k/translate.c</div> -<div>index 60bcfb7..24c1dd3 100644</div> -<div>--- a/target/m68k/translate.c</div> -<div>+++ b/target/m68k/translate.c</div> -<div>@@ -2414,7 +2414,7 @@ DISAS_INSN(cas)</div> -<div> uint16_t ext;</div> -<div> TCGv load;</div> -<div> TCGv cmp;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> </div> -<div> switch ((insn >> 9) & 3) {</div> -<div> case 1:</div> -<div>diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c</div> -<div>index 9ce65f3..41d1b8b 100644</div> -<div>--- a/target/microblaze/translate.c</div> -<div>+++ b/target/microblaze/translate.c</div> -<div>@@ -919,7 +919,7 @@ static void dec_load(DisasContext *dc)</div> -<div> unsigned int size;</div> -<div> bool rev = false, ex = false, ea = false;</div> -<div> int mem_index = cpu_mmu_index(&dc->cpu->env, false);</div> -<div>- TCGMemOp mop;</div> -<div>+ MemOp mop;</div> -<div> </div> -<div> mop = dc->opcode & 3;</div> -<div> size = 1 << mop;</div> -<div>@@ -1035,7 +1035,7 @@ static void dec_store(DisasContext *dc)</div> -<div> unsigned int size;</div> -<div> bool rev = false, ex = false, ea = false;</div> -<div> int mem_index = cpu_mmu_index(&dc->cpu->env, false);</div> -<div>- TCGMemOp mop;</div> -<div>+ MemOp mop;</div> -<div> </div> -<div> mop = dc->opcode & 3;</div> -<div> size = 1 << mop;</div> -<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div> -<div>index ca62800..59b5d85 100644</div> -<div>--- a/target/mips/translate.c</div> -<div>+++ b/target/mips/translate.c</div> -<div>@@ -2526,7 +2526,7 @@ typedef struct DisasContext {</div> -<div> int32_t CP0_Config5;</div> -<div> /* Routine used to access memory */</div> -<div> int mem_idx;</div> -<div>- TCGMemOp default_tcg_memop_mask;</div> -<div>+ MemOp default_tcg_memop_mask;</div> -<div> uint32_t hflags, saved_hflags;</div> -<div> target_ulong btarget;</div> -<div> bool ulri;</div> -<div>@@ -3706,7 +3706,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,</div> -<div> </div> -<div> /* Store conditional */</div> -<div> static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,</div> -<div>- TCGMemOp tcg_mo, bool eva)</div> -<div>+ MemOp tcg_mo, bool eva)</div> -<div> {</div> -<div> TCGv addr, t0, val;</div> -<div> TCGLabel *l1 = gen_new_label();</div> -<div>@@ -4546,7 +4546,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)</div> -<div> }</div> -<div> </div> -<div> static inline void gen_r6_ld(target_long addr, int reg, int memidx,</div> -<div>- TCGMemOp memop)</div> -<div>+ MemOp memop)</div> -<div> {</div> -<div> TCGv t0 = tcg_const_tl(addr);</div> -<div> tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);</div> -<div>@@ -21828,7 +21828,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)</div> -<div> extract32(ctx->opcode, 0, 8);</div> -<div> TCGv va = tcg_temp_new();</div> -<div> TCGv t1 = tcg_temp_new();</div> -<div>- TCGMemOp memop = (extract32(ctx->opcode, 8, 3)) ==</div> -<div>+ MemOp memop = (extract32(ctx->opcode, 8, 3)) ==</div> -<div> NM_P_LS_UAWM ? MO_UNALN : 0;</div> -<div> </div> -<div> count = (count == 0) ? 8 : count;</div> -<div>diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c</div> -<div>index 4360ce4..b189c50 100644</div> -<div>--- a/target/openrisc/translate.c</div> -<div>+++ b/target/openrisc/translate.c</div> -<div>@@ -681,7 +681,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)</div> -<div> return true;</div> -<div> }</div> -<div> </div> -<div>-static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)</div> -<div>+static void do_load(DisasContext *dc, arg_load *a, MemOp mop)</div> -<div> {</div> -<div> TCGv ea;</div> -<div> </div> -<div>@@ -763,7 +763,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)</div> -<div> return true;</div> -<div> }</div> -<div> </div> -<div>-static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)</div> -<div>+static void do_store(DisasContext *dc, arg_store *a, MemOp mop)</div> -<div> {</div> -<div> TCGv t0 = tcg_temp_new();</div> -<div> tcg_gen_addi_tl(t0, cpu_R[a->a], a->i);</div> -<div>diff --git a/target/ppc/translate.c b/target/ppc/translate.c</div> -<div>index 4a5de28..31800ed 100644</div> -<div>--- a/target/ppc/translate.c</div> -<div>+++ b/target/ppc/translate.c</div> -<div>@@ -162,7 +162,7 @@ struct DisasContext {</div> -<div> int mem_idx;</div> -<div> int access_type;</div> -<div> /* Translation flags */</div> -<div>- TCGMemOp default_tcg_memop_mask;</div> -<div>+ MemOp default_tcg_memop_mask;</div> -<div> #if defined(TARGET_PPC64)</div> -<div> bool sf_mode;</div> -<div> bool has_cfar;</div> -<div>@@ -3142,7 +3142,7 @@ static void gen_isync(DisasContext *ctx)</div> -<div> </div> -<div> #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))</div> -<div> </div> -<div>-static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)</div> -<div>+static void gen_load_locked(DisasContext *ctx, MemOp memop)</div> -<div> {</div> -<div> TCGv gpr = cpu_gpr[rD(ctx->opcode)];</div> -<div> TCGv t0 = tcg_temp_new();</div> -<div>@@ -3167,7 +3167,7 @@ LARX(lbarx, DEF_MEMOP(MO_UB))</div> -<div> LARX(lharx, DEF_MEMOP(MO_UW))</div> -<div> LARX(lwarx, DEF_MEMOP(MO_UL))</div> -<div> </div> -<div>-static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,</div> -<div>+static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,</div> -<div> TCGv EA, TCGCond cond, int addend)</div> -<div> {</div> -<div> TCGv t = tcg_temp_new();</div> -<div>@@ -3193,7 +3193,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,</div> -<div> tcg_temp_free(u);</div> -<div> }</div> -<div> </div> -<div>-static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)</div> -<div>+static void gen_ld_atomic(DisasContext *ctx, MemOp memop)</div> -<div> {</div> -<div> uint32_t gpr_FC = FC(ctx->opcode);</div> -<div> TCGv EA = tcg_temp_new();</div> -<div>@@ -3306,7 +3306,7 @@ static void gen_ldat(DisasContext *ctx)</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>-static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)</div> -<div>+static void gen_st_atomic(DisasContext *ctx, MemOp memop)</div> -<div> {</div> -<div> uint32_t gpr_FC = FC(ctx->opcode);</div> -<div> TCGv EA = tcg_temp_new();</div> -<div>@@ -3389,7 +3389,7 @@ static void gen_stdat(DisasContext *ctx)</div> -<div> }</div> -<div> #endif</div> -<div> </div> -<div>-static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)</div> -<div>+static void gen_conditional_store(DisasContext *ctx, MemOp memop)</div> -<div> {</div> -<div> TCGLabel *l1 = gen_new_label();</div> -<div> TCGLabel *l2 = gen_new_label();</div> -<div>diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c</div> -<div>index fadd888..be8a9f0 100644</div> -<div>--- a/target/riscv/insn_trans/trans_rva.inc.c</div> -<div>+++ b/target/riscv/insn_trans/trans_rva.inc.c</div> -<div>@@ -18,7 +18,7 @@</div> -<div> * this program. If not, see <http://www.gnu.org/licenses/>.</div> -<div> */</div> -<div> </div> -<div>-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div> -<div>+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)</div> -<div> {</div> -<div> TCGv src1 = tcg_temp_new();</div> -<div> /* Put addr in load_res, data in load_val. */</div> -<div>@@ -37,7 +37,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div> -<div> return true;</div> -<div> }</div> -<div> </div> -<div>-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div> -<div>+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)</div> -<div> {</div> -<div> TCGv src1 = tcg_temp_new();</div> -<div> TCGv src2 = tcg_temp_new();</div> -<div>@@ -82,8 +82,8 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div> -<div> }</div> -<div> </div> -<div> static bool gen_amo(DisasContext *ctx, arg_atomic *a,</div> -<div>- void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),</div> -<div>- TCGMemOp mop)</div> -<div>+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),</div> -<div>+ MemOp mop)</div> -<div> {</div> -<div> TCGv src1 = tcg_temp_new();</div> -<div> TCGv src2 = tcg_temp_new();</div> -<div>diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c</div> -<div>index ea64731..cf440d1 100644</div> -<div>--- a/target/riscv/insn_trans/trans_rvi.inc.c</div> -<div>+++ b/target/riscv/insn_trans/trans_rvi.inc.c</div> -<div>@@ -135,7 +135,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)</div> -<div> return gen_branch(ctx, a, TCG_COND_GEU);</div> -<div> }</div> -<div> </div> -<div>-static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)</div> -<div>+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)</div> -<div> {</div> -<div> TCGv t0 = tcg_temp_new();</div> -<div> TCGv t1 = tcg_temp_new();</div> -<div>@@ -174,7 +174,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)</div> -<div> return gen_load(ctx, a, MO_TEUW);</div> -<div> }</div> -<div> </div> -<div>-static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)</div> -<div>+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)</div> -<div> {</div> -<div> TCGv t0 = tcg_temp_new();</div> -<div> TCGv dat = tcg_temp_new();</div> -<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div> -<div>index ac0d8b6..2927247 100644</div> -<div>--- a/target/s390x/translate.c</div> -<div>+++ b/target/s390x/translate.c</div> -<div>@@ -152,7 +152,7 @@ static inline int vec_full_reg_offset(uint8_t reg)</div> -<div> return offsetof(CPUS390XState, vregs[reg][0]);</div> -<div> }</div> -<div> </div> -<div>-static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div> -<div>+static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es)</div> -<div> {</div> -<div> /* Convert element size (es) - e.g. MO_8 - to bytes */</div> -<div> const uint8_t bytes = 1 << es;</div> -<div>@@ -2262,7 +2262,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)</div> -<div> #ifndef CONFIG_USER_ONLY</div> -<div> static DisasJumpType op_csp(DisasContext *s, DisasOps *o)</div> -<div> {</div> -<div>- TCGMemOp mop = s->insn->data;</div> -<div>+ MemOp mop = s->insn->data;</div> -<div> TCGv_i64 addr, old, cc;</div> -<div> TCGLabel *lab = gen_new_label();</div> -<div> </div> -<div>@@ -3228,7 +3228,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)</div> -<div> static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)</div> -<div> {</div> -<div> TCGv_i64 a1, a2;</div> -<div>- TCGMemOp mop = s->insn->data;</div> -<div>+ MemOp mop = s->insn->data;</div> -<div> </div> -<div> /* In a parallel context, stop the world and single step. */</div> -<div> if (tb_cflags(s->base.tb) & CF_PARALLEL) {</div> -<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div> -<div>index 41d5cf8..4c56bbb 100644</div> -<div>--- a/target/s390x/translate_vx.inc.c</div> -<div>+++ b/target/s390x/translate_vx.inc.c</div> -<div>@@ -57,13 +57,13 @@</div> -<div> #define FPF_LONG 3</div> -<div> #define FPF_EXT 4</div> -<div> </div> -<div>-static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)</div> -<div>+static inline bool valid_vec_element(uint8_t enr, MemOp es)</div> -<div> {</div> -<div> return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));</div> -<div> }</div> -<div> </div> -<div> static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,</div> -<div>- TCGMemOp memop)</div> -<div>+ MemOp memop)</div> -<div> {</div> -<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div> -<div> </div> -<div>@@ -96,7 +96,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,</div> -<div> }</div> -<div> </div> -<div> static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,</div> -<div>- TCGMemOp memop)</div> -<div>+ MemOp memop)</div> -<div> {</div> -<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div> -<div> </div> -<div>@@ -123,7 +123,7 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,</div> -<div> }</div> -<div> </div> -<div> static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,</div> -<div>- TCGMemOp memop)</div> -<div>+ MemOp memop)</div> -<div> {</div> -<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div> -<div> </div> -<div>@@ -146,7 +146,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,</div> -<div> }</div> -<div> </div> -<div> static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,</div> -<div>- TCGMemOp memop)</div> -<div>+ MemOp memop)</div> -<div> {</div> -<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div> -<div> </div> -<div>diff --git a/target/sparc/translate.c b/target/sparc/translate.c</div> -<div>index 091bab5..bef9ce6 100644</div> -<div>--- a/target/sparc/translate.c</div> -<div>+++ b/target/sparc/translate.c</div> -<div>@@ -2019,7 +2019,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,</div> -<div> }</div> -<div> </div> -<div> static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,</div> -<div>- TCGv addr, int mmu_idx, TCGMemOp memop)</div> -<div>+ TCGv addr, int mmu_idx, MemOp memop)</div> -<div> {</div> -<div> gen_address_mask(dc, addr);</div> -<div> tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);</div> -<div>@@ -2050,10 +2050,10 @@ typedef struct {</div> -<div> ASIType type;</div> -<div> int asi;</div> -<div> int mem_idx;</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> } DisasASI;</div> -<div> </div> -<div>-static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)</div> -<div>+static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)</div> -<div> {</div> -<div> int asi = GET_FIELD(insn, 19, 26);</div> -<div> ASIType type = GET_ASI_HELPER;</div> -<div>@@ -2267,7 +2267,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)</div> -<div> }</div> -<div> </div> -<div> static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,</div> -<div>- int insn, TCGMemOp memop)</div> -<div>+ int insn, MemOp memop)</div> -<div> {</div> -<div> DisasASI da = get_asi(dc, insn, memop);</div> -<div> </div> -<div>@@ -2305,7 +2305,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,</div> -<div> }</div> -<div> </div> -<div> static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,</div> -<div>- int insn, TCGMemOp memop)</div> -<div>+ int insn, MemOp memop)</div> -<div> {</div> -<div> DisasASI da = get_asi(dc, insn, memop);</div> -<div> </div> -<div>@@ -2511,7 +2511,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,</div> -<div> case GET_ASI_BLOCK:</div> -<div> /* Valid for lddfa on aligned registers only. */</div> -<div> if (size == 8 && (rd & 7) == 0) {</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> TCGv eight;</div> -<div> int i;</div> -<div> </div> -<div>@@ -2625,7 +2625,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,</div> -<div> case GET_ASI_BLOCK:</div> -<div> /* Valid for stdfa on aligned registers only. */</div> -<div> if (size == 8 && (rd & 7) == 0) {</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> TCGv eight;</div> -<div> int i;</div> -<div> </div> -<div>diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c</div> -<div>index c46a4ab..68dd4aa 100644</div> -<div>--- a/target/tilegx/translate.c</div> -<div>+++ b/target/tilegx/translate.c</div> -<div>@@ -290,7 +290,7 @@ static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)</div> -<div> }</div> -<div> </div> -<div> static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,</div> -<div>- unsigned srcb, TCGMemOp memop, const char *name)</div> -<div>+ unsigned srcb, MemOp memop, const char *name)</div> -<div> {</div> -<div> if (dest) {</div> -<div> return TILEGX_EXCP_OPCODE_UNKNOWN;</div> -<div>@@ -305,7 +305,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,</div> -<div> }</div> -<div> </div> -<div> static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,</div> -<div>- int imm, TCGMemOp memop, const char *name)</div> -<div>+ int imm, MemOp memop, const char *name)</div> -<div> {</div> -<div> TCGv tsrca = load_gr(dc, srca);</div> -<div> TCGv tsrcb = load_gr(dc, srcb);</div> -<div>@@ -496,7 +496,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,</div> -<div> {</div> -<div> TCGv tdest, tsrca;</div> -<div> const char *mnemonic;</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> TileExcp ret = TILEGX_EXCP_NONE;</div> -<div> bool prefetch_nofault = false;</div> -<div> </div> -<div>@@ -1478,7 +1478,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,</div> -<div> TCGv tsrca = load_gr(dc, srca);</div> -<div> bool prefetch_nofault = false;</div> -<div> const char *mnemonic;</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> int i2, i3;</div> -<div> TCGv t0;</div> -<div> </div> -<div>@@ -2106,7 +2106,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)</div> -<div> unsigned srca = get_SrcA_Y2(bundle);</div> -<div> unsigned srcbdest = get_SrcBDest_Y2(bundle);</div> -<div> const char *mnemonic;</div> -<div>- TCGMemOp memop;</div> -<div>+ MemOp memop;</div> -<div> bool prefetch_nofault = false;</div> -<div> </div> -<div> switch (OEY2(opc, mode)) {</div> -<div>diff --git a/target/tricore/translate.c b/target/tricore/translate.c</div> -<div>index dc2a65f..87a5f50 100644</div> -<div>--- a/target/tricore/translate.c</div> -<div>+++ b/target/tricore/translate.c</div> -<div>@@ -227,7 +227,7 @@ static inline void generate_trap(DisasContext *ctx, int class, int tin);</div> -<div> /* Functions for load/save to/from memory */</div> -<div> </div> -<div> static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,</div> -<div>- int16_t con, TCGMemOp mop)</div> -<div>+ int16_t con, MemOp mop)</div> -<div> {</div> -<div> TCGv temp = tcg_temp_new();</div> -<div> tcg_gen_addi_tl(temp, r2, con);</div> -<div>@@ -236,7 +236,7 @@ static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,</div> -<div> }</div> -<div> </div> -<div> static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,</div> -<div>- int16_t con, TCGMemOp mop)</div> -<div>+ int16_t con, MemOp mop)</div> -<div> {</div> -<div> TCGv temp = tcg_temp_new();</div> -<div> tcg_gen_addi_tl(temp, r2, con);</div> -<div>@@ -284,7 +284,7 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,</div> -<div> }</div> -<div> </div> -<div> static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div> -<div>- TCGMemOp mop)</div> -<div>+ MemOp mop)</div> -<div> {</div> -<div> TCGv temp = tcg_temp_new();</div> -<div> tcg_gen_addi_tl(temp, r2, off);</div> -<div>@@ -294,7 +294,7 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div> -<div> }</div> -<div> </div> -<div> static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div> -<div>- TCGMemOp mop)</div> -<div>+ MemOp mop)</div> -<div> {</div> -<div> TCGv temp = tcg_temp_new();</div> -<div> tcg_gen_addi_tl(temp, r2, off);</div> -<div>diff --git a/tcg/README b/tcg/README</div> -<div>index 21fcdf7..b4382fa 100644</div> -<div>--- a/tcg/README</div> -<div>+++ b/tcg/README</div> -<div>@@ -512,7 +512,7 @@ Both t0 and t1 may be split into little-endian ordered pairs of registers</div> -<div> if dealing with 64-bit quantities on a 32-bit host.</div> -<div> </div> -<div> The memidx selects the qemu tlb index to use (e.g. user or kernel access).</div> -<div>-The flags are the TCGMemOp bits, selecting the sign, width, and endianness</div> -<div>+The flags are the MemOp bits, selecting the sign, width, and endianness</div> -<div> of the memory access.</div> -<div> </div> -<div> For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a</div> -<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div> -<div>index 0713448..3f92101 100644</div> -<div>--- a/tcg/aarch64/tcg-target.inc.c</div> -<div>+++ b/tcg/aarch64/tcg-target.inc.c</div> -<div>@@ -1423,7 +1423,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)</div> -<div> tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);</div> -<div> }</div> -<div> </div> -<div>-static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,</div> -<div>+static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,</div> -<div> TCGReg rd, TCGReg rn)</div> -<div> {</div> -<div> /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */</div> -<div>@@ -1431,7 +1431,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,</div> -<div> tcg_out_sbfm(s, ext, rd, rn, 0, bits);</div> -<div> }</div> -<div> </div> -<div>-static inline void tcg_out_uxt(TCGContext *s, TCGMemOp s_bits,</div> -<div>+static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,</div> -<div> TCGReg rd, TCGReg rn)</div> -<div> {</div> -<div> /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */</div> -<div>@@ -1580,8 +1580,8 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)</div> -<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp size = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp size = opc & MO_SIZE;</div> -<div> </div> -<div> if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {</div> -<div> return false;</div> -<div>@@ -1605,8 +1605,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp size = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp size = opc & MO_SIZE;</div> -<div> </div> -<div> if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {</div> -<div> return false;</div> -<div>@@ -1649,7 +1649,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);</div> -<div> slow path for the failure case, which will be patched later when finalizing</div> -<div> the slow path. Generated code returns the host addend in X1,</div> -<div> clobbers X0,X2,X3,TMP. */</div> -<div>-static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,</div> -<div>+static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,</div> -<div> tcg_insn_unit **label_ptr, int mem_index,</div> -<div> bool is_read)</div> -<div> {</div> -<div>@@ -1709,11 +1709,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,</div> -<div> </div> -<div> #endif /* CONFIG_SOFTMMU */</div> -<div> </div> -<div>-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div> -<div>+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,</div> -<div> TCGReg data_r, TCGReg addr_r,</div> -<div> TCGType otype, TCGReg off_r)</div> -<div> {</div> -<div>- const TCGMemOp bswap = memop & MO_BSWAP;</div> -<div>+ const MemOp bswap = memop & MO_BSWAP;</div> -<div> </div> -<div> switch (memop & MO_SSIZE) {</div> -<div> case MO_UB:</div> -<div>@@ -1765,11 +1765,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div>+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,</div> -<div> TCGReg data_r, TCGReg addr_r,</div> -<div> TCGType otype, TCGReg off_r)</div> -<div> {</div> -<div>- const TCGMemOp bswap = memop & MO_BSWAP;</div> -<div>+ const MemOp bswap = memop & MO_BSWAP;</div> -<div> </div> -<div> switch (memop & MO_SIZE) {</div> -<div> case MO_8:</div> -<div>@@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div> -<div> static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> TCGMemOpIdx oi, TCGType ext)</div> -<div> {</div> -<div>- TCGMemOp memop = get_memop(oi);</div> -<div>+ MemOp memop = get_memop(oi);</div> -<div> const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned mem_index = get_mmuidx(oi);</div> -<div>@@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> TCGMemOpIdx oi)</div> -<div> {</div> -<div>- TCGMemOp memop = get_memop(oi);</div> -<div>+ MemOp memop = get_memop(oi);</div> -<div> const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned mem_index = get_mmuidx(oi);</div> -<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div> -<div>index ece88dc..94d80d7 100644</div> -<div>--- a/tcg/arm/tcg-target.inc.c</div> -<div>+++ b/tcg/arm/tcg-target.inc.c</div> -<div>@@ -1233,7 +1233,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);</div> -<div> containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */</div> -<div> </div> -<div> static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,</div> -<div>- TCGMemOp opc, int mem_index, bool is_load)</div> -<div>+ MemOp opc, int mem_index, bool is_load)</div> -<div> {</div> -<div> int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)</div> -<div> : offsetof(CPUTLBEntry, addr_write));</div> -<div>@@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGReg argreg, datalo, datahi;</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> void *func;</div> -<div> </div> -<div> if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {</div> -<div>@@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGReg argreg, datalo, datahi;</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> </div> -<div> if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {</div> -<div> return false;</div> -<div>@@ -1453,11 +1453,11 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> }</div> -<div> #endif /* SOFTMMU */</div> -<div> </div> -<div>-static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div> -<div>+static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,</div> -<div> TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg addrlo, TCGReg addend)</div> -<div> {</div> -<div>- TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SSIZE) {</div> -<div> case MO_UB:</div> -<div>@@ -1514,11 +1514,11 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,</div> -<div>+static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,</div> -<div> TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg addrlo)</div> -<div> {</div> -<div>- TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SSIZE) {</div> -<div> case MO_UB:</div> -<div>@@ -1577,7 +1577,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> {</div> -<div> TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> int mem_index;</div> -<div> TCGReg addend;</div> -<div>@@ -1614,11 +1614,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> #endif</div> -<div> }</div> -<div> </div> -<div>-static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div>+static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,</div> -<div> TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg addrlo, TCGReg addend)</div> -<div> {</div> -<div>- TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SIZE) {</div> -<div> case MO_8:</div> -<div>@@ -1659,11 +1659,11 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div> -<div>+static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,</div> -<div> TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg addrlo)</div> -<div> {</div> -<div>- TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> switch (opc & MO_SIZE) {</div> -<div> case MO_8:</div> -<div>@@ -1708,7 +1708,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> {</div> -<div> TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> int mem_index;</div> -<div> TCGReg addend;</div> -<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div> -<div>index 6ddeebf..9d8ed97 100644</div> -<div>--- a/tcg/i386/tcg-target.inc.c</div> -<div>+++ b/tcg/i386/tcg-target.inc.c</div> -<div>@@ -1697,7 +1697,7 @@ static void * const qemu_st_helpers[16] = {</div> -<div> First argument register is clobbered. */</div> -<div> </div> -<div> static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,</div> -<div>- int mem_index, TCGMemOp opc,</div> -<div>+ int mem_index, MemOp opc,</div> -<div> tcg_insn_unit **label_ptr, int which)</div> -<div> {</div> -<div> const TCGReg r0 = TCG_REG_L0;</div> -<div>@@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,</div> -<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> TCGReg data_reg;</div> -<div> tcg_insn_unit **label_ptr = &l->label_ptr[0];</div> -<div> int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);</div> -<div>@@ -1895,8 +1895,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp s_bits = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp s_bits = opc & MO_SIZE;</div> -<div> tcg_insn_unit **label_ptr = &l->label_ptr[0];</div> -<div> TCGReg retaddr;</div> -<div> </div> -<div>@@ -1995,10 +1995,10 @@ static inline int setup_guest_base_seg(void)</div> -<div> </div> -<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg base, int index, intptr_t ofs,</div> -<div>- int seg, bool is64, TCGMemOp memop)</div> -<div>+ int seg, bool is64, MemOp memop)</div> -<div> {</div> -<div>- const TCGMemOp real_bswap = memop & MO_BSWAP;</div> -<div>- TCGMemOp bswap = real_bswap;</div> -<div>+ const MemOp real_bswap = memop & MO_BSWAP;</div> -<div>+ MemOp bswap = real_bswap;</div> -<div> int rexw = is64 * P_REXW;</div> -<div> int movop = OPC_MOVL_GvEv;</div> -<div> </div> -<div>@@ -2103,7 +2103,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> TCGReg datalo, datahi, addrlo;</div> -<div> TCGReg addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> int mem_index;</div> -<div> tcg_insn_unit *label_ptr[2];</div> -<div>@@ -2137,15 +2137,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> </div> -<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div> -<div> TCGReg base, int index, intptr_t ofs,</div> -<div>- int seg, TCGMemOp memop)</div> -<div>+ int seg, MemOp memop)</div> -<div> {</div> -<div> /* ??? Ideally we wouldn't need a scratch register. For user-only,</div> -<div> we could perform the bswap twice to restore the original value</div> -<div> instead of moving to the scratch. But as it is, the L constraint</div> -<div> means that TCG_REG_L0 is definitely free here. */</div> -<div> const TCGReg scratch = TCG_REG_L0;</div> -<div>- const TCGMemOp real_bswap = memop & MO_BSWAP;</div> -<div>- TCGMemOp bswap = real_bswap;</div> -<div>+ const MemOp real_bswap = memop & MO_BSWAP;</div> -<div>+ MemOp bswap = real_bswap;</div> -<div> int movop = OPC_MOVL_EvGv;</div> -<div> </div> -<div> if (have_movbe && real_bswap) {</div> -<div>@@ -2221,7 +2221,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)</div> -<div> TCGReg datalo, datahi, addrlo;</div> -<div> TCGReg addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> int mem_index;</div> -<div> tcg_insn_unit *label_ptr[2];</div> -<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div> -<div>index 41bff32..5442167 100644</div> -<div>--- a/tcg/mips/tcg-target.inc.c</div> -<div>+++ b/tcg/mips/tcg-target.inc.c</div> -<div>@@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,</div> -<div> TCGReg addrh, TCGMemOpIdx oi,</div> -<div> tcg_insn_unit *label_ptr[2], bool is_load)</div> -<div> {</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> unsigned s_bits = opc & MO_SIZE;</div> -<div> unsigned a_bits = get_alignment_bits(opc);</div> -<div> int mem_index = get_mmuidx(oi);</div> -<div>@@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,</div> -<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> TCGReg v0;</div> -<div> int i;</div> -<div> </div> -<div>@@ -1363,8 +1363,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp s_bits = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp s_bits = opc & MO_SIZE;</div> -<div> int i;</div> -<div> </div> -<div> /* resolve label address */</div> -<div>@@ -1413,7 +1413,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> #endif</div> -<div> </div> -<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div>- TCGReg base, TCGMemOp opc, bool is_64)</div> -<div>+ TCGReg base, MemOp opc, bool is_64)</div> -<div> {</div> -<div> switch (opc & (MO_SSIZE | MO_BSWAP)) {</div> -<div> case MO_UB:</div> -<div>@@ -1521,7 +1521,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div> -<div> TCGReg data_regl, data_regh;</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> tcg_insn_unit *label_ptr[2];</div> -<div> #endif</div> -<div>@@ -1558,7 +1558,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> }</div> -<div> </div> -<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div>- TCGReg base, TCGMemOp opc)</div> -<div>+ TCGReg base, MemOp opc)</div> -<div> {</div> -<div> /* Don't clutter the code below with checks to avoid bswapping ZERO. */</div> -<div> if ((lo | hi) == 0) {</div> -<div>@@ -1624,7 +1624,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div> -<div> TCGReg data_regl, data_regh;</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> tcg_insn_unit *label_ptr[2];</div> -<div> #endif</div> -<div>diff --git a/tcg/optimize.c b/tcg/optimize.c</div> -<div>index d2424de..a89ffda 100644</div> -<div>--- a/tcg/optimize.c</div> -<div>+++ b/tcg/optimize.c</div> -<div>@@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s)</div> -<div> CASE_OP_32_64(qemu_ld):</div> -<div> {</div> -<div> TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];</div> -<div>- TCGMemOp mop = get_memop(oi);</div> -<div>+ MemOp mop = get_memop(oi);</div> -<div> if (!(mop & MO_SIGN)) {</div> -<div> mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;</div> -<div> }</div> -<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div> -<div>index 852b894..815edac 100644</div> -<div>--- a/tcg/ppc/tcg-target.inc.c</div> -<div>+++ b/tcg/ppc/tcg-target.inc.c</div> -<div>@@ -1506,7 +1506,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);</div> -<div> in CR7, loads the addend of the TLB into R3, and returns the register</div> -<div> containing the guest address (zero-extended into R4). Clobbers R0 and R2. */</div> -<div> </div> -<div>-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,</div> -<div>+static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,</div> -<div> TCGReg addrlo, TCGReg addrhi,</div> -<div> int mem_index, bool is_read)</div> -<div> {</div> -<div>@@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,</div> -<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> TCGReg hi, lo, arg = TCG_REG_R3;</div> -<div> </div> -<div> if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {</div> -<div>@@ -1680,8 +1680,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> {</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp s_bits = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp s_bits = opc & MO_SIZE;</div> -<div> TCGReg hi, lo, arg = TCG_REG_R3;</div> -<div> </div> -<div> if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {</div> -<div>@@ -1744,7 +1744,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg datalo, datahi, addrlo, rbase;</div> -<div> TCGReg addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc, s_bits;</div> -<div>+ MemOp opc, s_bits;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> int mem_index;</div> -<div> tcg_insn_unit *label_ptr;</div> -<div>@@ -1819,7 +1819,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg datalo, datahi, addrlo, rbase;</div> -<div> TCGReg addrhi __attribute__((unused));</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc, s_bits;</div> -<div>+ MemOp opc, s_bits;</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> int mem_index;</div> -<div> tcg_insn_unit *label_ptr;</div> -<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div> -<div>index 3e76bf5..7018509 100644</div> -<div>--- a/tcg/riscv/tcg-target.inc.c</div> -<div>+++ b/tcg/riscv/tcg-target.inc.c</div> -<div>@@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,</div> -<div> TCGReg addrh, TCGMemOpIdx oi,</div> -<div> tcg_insn_unit **label_ptr, bool is_load)</div> -<div> {</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> unsigned s_bits = opc & MO_SIZE;</div> -<div> unsigned a_bits = get_alignment_bits(opc);</div> -<div> tcg_target_long compare_mask;</div> -<div>@@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,</div> -<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> TCGReg a0 = tcg_target_call_iarg_regs[0];</div> -<div> TCGReg a1 = tcg_target_call_iarg_regs[1];</div> -<div> TCGReg a2 = tcg_target_call_iarg_regs[2];</div> -<div>@@ -1077,8 +1077,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> {</div> -<div> TCGMemOpIdx oi = l->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>- TCGMemOp s_bits = opc & MO_SIZE;</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div>+ MemOp s_bits = opc & MO_SIZE;</div> -<div> TCGReg a0 = tcg_target_call_iarg_regs[0];</div> -<div> TCGReg a1 = tcg_target_call_iarg_regs[1];</div> -<div> TCGReg a2 = tcg_target_call_iarg_regs[2];</div> -<div>@@ -1121,9 +1121,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div> -<div> #endif /* CONFIG_SOFTMMU */</div> -<div> </div> -<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div>- TCGReg base, TCGMemOp opc, bool is_64)</div> -<div>+ TCGReg base, MemOp opc, bool is_64)</div> -<div> {</div> -<div>- const TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ const MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> /* We don't yet handle byteswapping, assert */</div> -<div> g_assert(!bswap);</div> -<div>@@ -1172,7 +1172,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div> -<div> TCGReg data_regl, data_regh;</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> tcg_insn_unit *label_ptr[1];</div> -<div> #endif</div> -<div>@@ -1208,9 +1208,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> }</div> -<div> </div> -<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div> -<div>- TCGReg base, TCGMemOp opc)</div> -<div>+ TCGReg base, MemOp opc)</div> -<div> {</div> -<div>- const TCGMemOp bswap = opc & MO_BSWAP;</div> -<div>+ const MemOp bswap = opc & MO_BSWAP;</div> -<div> </div> -<div> /* We don't yet handle byteswapping, assert */</div> -<div> g_assert(!bswap);</div> -<div>@@ -1243,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div> -<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div> -<div> TCGReg data_regl, data_regh;</div> -<div> TCGMemOpIdx oi;</div> -<div>- TCGMemOp opc;</div> -<div>+ MemOp opc;</div> -<div> #if defined(CONFIG_SOFTMMU)</div> -<div> tcg_insn_unit *label_ptr[1];</div> -<div> #endif</div> -<div>diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c</div> -<div>index fe42939..8aaa4ce 100644</div> -<div>--- a/tcg/s390/tcg-target.inc.c</div> -<div>+++ b/tcg/s390/tcg-target.inc.c</div> -<div>@@ -1430,7 +1430,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div> -<div>+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,</div> -<div> TCGReg base, TCGReg index, int disp)</div> -<div> {</div> -<div> switch (opc & (MO_SSIZE | MO_BSWAP)) {</div> -<div>@@ -1489,7 +1489,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div> -<div>+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,</div> -<div> TCGReg base, TCGReg index, int disp)</div> -<div> {</div> -<div> switch (opc & (MO_SIZE | MO_BSWAP)) {</div> -<div>@@ -1544,7 +1544,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));</div> -<div> </div> -<div> /* Load and compare a TLB entry, leaving the flags set. Loads the TLB</div> -<div> addend into R2. Returns a register with the santitized guest address. */</div> -<div>-static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,</div> -<div>+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,</div> -<div> int mem_index, bool is_ld)</div> -<div> {</div> -<div> unsigned s_bits = opc & MO_SIZE;</div> -<div>@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> TCGReg addr_reg = lb->addrlo_reg;</div> -<div> TCGReg data_reg = lb->datalo_reg;</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> </div> -<div> if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,</div> -<div> (intptr_t)s->code_ptr, 2)) {</div> -<div>@@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div> -<div> TCGReg addr_reg = lb->addrlo_reg;</div> -<div> TCGReg data_reg = lb->datalo_reg;</div> -<div> TCGMemOpIdx oi = lb->oi;</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> </div> -<div> if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,</div> -<div> (intptr_t)s->code_ptr, 2)) {</div> -<div>@@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,</div> -<div> static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> TCGMemOpIdx oi)</div> -<div> {</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned mem_index = get_mmuidx(oi);</div> -<div> tcg_insn_unit *label_ptr;</div> -<div>@@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div> -<div> TCGMemOpIdx oi)</div> -<div> {</div> -<div>- TCGMemOp opc = get_memop(oi);</div> -<div>+ MemOp opc = get_memop(oi);</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned mem_index = get_mmuidx(oi);</div> -<div> tcg_insn_unit *label_ptr;</div> -<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div> -<div>index 10b1cea..d7986cd 100644</div> -<div>--- a/tcg/sparc/tcg-target.inc.c</div> -<div>+++ b/tcg/sparc/tcg-target.inc.c</div> -<div>@@ -1081,7 +1081,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));</div> -<div> is in the returned register, maybe %o0. The TLB addend is in %o1. */</div> -<div> </div> -<div> static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,</div> -<div>- TCGMemOp opc, int which)</div> -<div>+ MemOp opc, int which)</div> -<div> {</div> -<div> int fast_off = TLB_MASK_TABLE_OFS(mem_index);</div> -<div> int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);</div> -<div>@@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] = {</div> -<div> static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div> -<div> TCGMemOpIdx oi, bool is_64)</div> -<div> {</div> -<div>- TCGMemOp memop = get_memop(oi);</div> -<div>+ MemOp memop = get_memop(oi);</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned memi = get_mmuidx(oi);</div> -<div> TCGReg addrz, param;</div> -<div>@@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div> -<div> static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,</div> -<div> TCGMemOpIdx oi)</div> -<div> {</div> -<div>- TCGMemOp memop = get_memop(oi);</div> -<div>+ MemOp memop = get_memop(oi);</div> -<div> #ifdef CONFIG_SOFTMMU</div> -<div> unsigned memi = get_mmuidx(oi);</div> -<div> TCGReg addrz, param;</div> -<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div> -<div>index 587d092..e87c327 100644</div> -<div>--- a/tcg/tcg-op.c</div> -<div>+++ b/tcg/tcg-op.c</div> -<div>@@ -2714,7 +2714,7 @@ void tcg_gen_lookup_and_goto_ptr(void)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div>+static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)</div> -<div> {</div> -<div> /* Trigger the asserts within as early as possible. */</div> -<div> (void)get_alignment_bits(op);</div> -<div>@@ -2743,7 +2743,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div> -<div> }</div> -<div> </div> -<div> static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,</div> -<div>- TCGMemOp memop, TCGArg idx)</div> -<div>+ MemOp memop, TCGArg idx)</div> -<div> {</div> -<div> TCGMemOpIdx oi = make_memop_idx(memop, idx);</div> -<div> #if TARGET_LONG_BITS == 32</div> -<div>@@ -2758,7 +2758,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,</div> -<div> }</div> -<div> </div> -<div> static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,</div> -<div>- TCGMemOp memop, TCGArg idx)</div> -<div>+ MemOp memop, TCGArg idx)</div> -<div> {</div> -<div> TCGMemOpIdx oi = make_memop_idx(memop, idx);</div> -<div> #if TARGET_LONG_BITS == 32</div> -<div>@@ -2788,9 +2788,9 @@ static void tcg_gen_req_mo(TCGBar type)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div>+void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div>- TCGMemOp orig_memop;</div> -<div>+ MemOp orig_memop;</div> -<div> </div> -<div> tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);</div> -<div> memop = tcg_canonicalize_memop(memop, 0, 0);</div> -<div>@@ -2825,7 +2825,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div>+void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div> TCGv_i32 swap = NULL;</div> -<div> </div> -<div>@@ -2858,9 +2858,9 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div>+void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div>- TCGMemOp orig_memop;</div> -<div>+ MemOp orig_memop;</div> -<div> </div> -<div> if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div> -<div> tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);</div> -<div>@@ -2911,7 +2911,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div>+void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div> TCGv_i64 swap = NULL;</div> -<div> </div> -<div>@@ -2953,7 +2953,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)</div> -<div>+static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc)</div> -<div> {</div> -<div> switch (opc & MO_SSIZE) {</div> -<div> case MO_SB:</div> -<div>@@ -2974,7 +2974,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)</div> -<div> }</div> -<div> }</div> -<div> </div> -<div>-static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc)</div> -<div>+static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc)</div> -<div> {</div> -<div> switch (opc & MO_SSIZE) {</div> -<div> case MO_SB:</div> -<div>@@ -3034,7 +3034,7 @@ static void * const table_cmpxchg[16] = {</div> -<div> };</div> -<div> </div> -<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div> -<div>- TCGv_i32 newv, TCGArg idx, TCGMemOp memop)</div> -<div>+ TCGv_i32 newv, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div> memop = tcg_canonicalize_memop(memop, 0, 0);</div> -<div> </div> -<div>@@ -3078,7 +3078,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div> -<div>- TCGv_i64 newv, TCGArg idx, TCGMemOp memop)</div> -<div>+ TCGv_i64 newv, TCGArg idx, MemOp memop)</div> -<div> {</div> -<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div> -<div> </div> -<div>@@ -3142,7 +3142,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div> -<div> }</div> -<div> </div> -<div> static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div> -<div>- TCGArg idx, TCGMemOp memop, bool new_val,</div> -<div>+ TCGArg idx, MemOp memop, bool new_val,</div> -<div> void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))</div> -<div> {</div> -<div> TCGv_i32 t1 = tcg_temp_new_i32();</div> -<div>@@ -3160,7 +3160,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div> -<div> }</div> -<div> </div> -<div> static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div> -<div>- TCGArg idx, TCGMemOp memop, void * const table[])</div> -<div>+ TCGArg idx, MemOp memop, void * const table[])</div> -<div> {</div> -<div> gen_atomic_op_i32 gen;</div> -<div> </div> -<div>@@ -3185,7 +3185,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div> -<div> }</div> -<div> </div> -<div> static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div>- TCGArg idx, TCGMemOp memop, bool new_val,</div> -<div>+ TCGArg idx, MemOp memop, bool new_val,</div> -<div> void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))</div> -<div> {</div> -<div> TCGv_i64 t1 = tcg_temp_new_i64();</div> -<div>@@ -3203,7 +3203,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div> }</div> -<div> </div> -<div> static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div> -<div>- TCGArg idx, TCGMemOp memop, void * const table[])</div> -<div>+ TCGArg idx, MemOp memop, void * const table[])</div> -<div> {</div> -<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div> -<div> </div> -<div>@@ -3257,7 +3257,7 @@ static void * const table_##NAME[16] = { \</div> -<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \</div> -<div> }; \</div> -<div> void tcg_gen_atomic_##NAME##_i32 \</div> -<div>- (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \</div> -<div>+ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \</div> -<div> { \</div> -<div> if (tcg_ctx->tb_cflags & CF_PARALLEL) { \</div> -<div> do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \</div> -<div>@@ -3267,7 +3267,7 @@ void tcg_gen_atomic_##NAME##_i32 \</div> -<div> } \</div> -<div> } \</div> -<div> void tcg_gen_atomic_##NAME##_i64 \</div> -<div>- (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \</div> -<div>+ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \</div> -<div> { \</div> -<div> if (tcg_ctx->tb_cflags & CF_PARALLEL) { \</div> -<div> do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \</div> -<div>diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h</div> -<div>index 2d4dd5c..e9cf172 100644</div> -<div>--- a/tcg/tcg-op.h</div> -<div>+++ b/tcg/tcg-op.h</div> -<div>@@ -851,10 +851,10 @@ void tcg_gen_lookup_and_goto_ptr(void);</div> -<div> #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64</div> -<div> #endif</div> -<div> </div> -<div>-void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);</div> -<div>+void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);</div> -<div>+void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);</div> -<div>+void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);</div> -<div>+void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);</div> -<div> </div> -<div> static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)</div> -<div> {</div> -<div>@@ -912,46 +912,46 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)</div> -<div> }</div> -<div> </div> -<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,</div> -<div>- TCGArg, TCGMemOp);</div> -<div>+ TCGArg, MemOp);</div> -<div> void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,</div> -<div>- TCGArg, TCGMemOp);</div> -<div>-</div> -<div>-void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-</div> -<div>-void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-</div> -<div>-void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div> -<div>-void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div> -<div>+ TCGArg, MemOp);</div> -<div>+</div> -<div>+void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+</div> -<div>+void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+</div> -<div>+void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div> -<div>+void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div> -<div> </div> -<div> void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);</div> -<div> void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);</div> -<div>diff --git a/tcg/tcg.c b/tcg/tcg.c</div> -<div>index 8d23fb0..0dff196 100644</div> -<div>--- a/tcg/tcg.c</div> -<div>+++ b/tcg/tcg.c</div> -<div>@@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)</div> -<div> case INDEX_op_qemu_st_i64:</div> -<div> {</div> -<div> TCGMemOpIdx oi = op->args[k++];</div> -<div>- TCGMemOp op = get_memop(oi);</div> -<div>+ MemOp op = get_memop(oi);</div> -<div> unsigned ix = get_mmuidx(oi);</div> -<div> </div> -<div> if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {</div> -<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div> -<div>index 529acb2..a37181c 100644</div> -<div>--- a/tcg/tcg.h</div> -<div>+++ b/tcg/tcg.h</div> -<div>@@ -26,6 +26,7 @@</div> -<div> #define TCG_H</div> -<div> </div> -<div> #include "cpu.h"</div> -<div>+#include "exec/memop.h"</div> -<div> #include "exec/tb-context.h"</div> -<div> #include "qemu/bitops.h"</div> -<div> #include "qemu/queue.h"</div> -<div>@@ -309,103 +310,13 @@ typedef enum TCGType {</div> -<div> #endif</div> -<div> } TCGType;</div> -<div> </div> -<div>-/* Constants for qemu_ld and qemu_st for the Memory Operation field. */</div> -<div>-typedef enum TCGMemOp {</div> -<div>- MO_8 = 0,</div> -<div>- MO_16 = 1,</div> -<div>- MO_32 = 2,</div> -<div>- MO_64 = 3,</div> -<div>- MO_SIZE = 3, /* Mask for the above. */</div> -<div>-</div> -<div>- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */</div> -<div>-</div> -<div>- MO_BSWAP = 8, /* Host reverse endian. */</div> -<div>-#ifdef HOST_WORDS_BIGENDIAN</div> -<div>- MO_LE = MO_BSWAP,</div> -<div>- MO_BE = 0,</div> -<div>-#else</div> -<div>- MO_LE = 0,</div> -<div>- MO_BE = MO_BSWAP,</div> -<div>-#endif</div> -<div>-#ifdef TARGET_WORDS_BIGENDIAN</div> -<div>- MO_TE = MO_BE,</div> -<div>-#else</div> -<div>- MO_TE = MO_LE,</div> -<div>-#endif</div> -<div>-</div> -<div>- /*</div> -<div>- * MO_UNALN accesses are never checked for alignment.</div> -<div>- * MO_ALIGN accesses will result in a call to the CPU's</div> -<div>- * do_unaligned_access hook if the guest address is not aligned.</div> -<div>- * The default depends on whether the target CPU defines</div> -<div>- * TARGET_ALIGNED_ONLY.</div> -<div>- *</div> -<div>- * Some architectures (e.g. ARMv8) need the address which is aligned</div> -<div>- * to a size more than the size of the memory access.</div> -<div>- * Some architectures (e.g. SPARCv9) need an address which is aligned,</div> -<div>- * but less strictly than the natural alignment.</div> -<div>- *</div> -<div>- * MO_ALIGN supposes the alignment size is the size of a memory access.</div> -<div>- *</div> -<div>- * There are three options:</div> -<div>- * - unaligned access permitted (MO_UNALN).</div> -<div>- * - an alignment to the size of an access (MO_ALIGN);</div> -<div>- * - an alignment to a specified size, which may be more or less than</div> -<div>- * the access size (MO_ALIGN_x where 'x' is a size in bytes);</div> -<div>- */</div> -<div>- MO_ASHIFT = 4,</div> -<div>- MO_AMASK = 7 << MO_ASHIFT,</div> -<div>-#ifdef TARGET_ALIGNED_ONLY</div> -<div>- MO_ALIGN = 0,</div> -<div>- MO_UNALN = MO_AMASK,</div> -<div>-#else</div> -<div>- MO_ALIGN = MO_AMASK,</div> -<div>- MO_UNALN = 0,</div> -<div>-#endif</div> -<div>- MO_ALIGN_2 = 1 << MO_ASHIFT,</div> -<div>- MO_ALIGN_4 = 2 << MO_ASHIFT,</div> -<div>- MO_ALIGN_8 = 3 << MO_ASHIFT,</div> -<div>- MO_ALIGN_16 = 4 << MO_ASHIFT,</div> -<div>- MO_ALIGN_32 = 5 << MO_ASHIFT,</div> -<div>- MO_ALIGN_64 = 6 << MO_ASHIFT,</div> -<div>-</div> -<div>- /* Combinations of the above, for ease of use. */</div> -<div>- MO_UB = MO_8,</div> -<div>- MO_UW = MO_16,</div> -<div>- MO_UL = MO_32,</div> -<div>- MO_SB = MO_SIGN | MO_8,</div> -<div>- MO_SW = MO_SIGN | MO_16,</div> -<div>- MO_SL = MO_SIGN | MO_32,</div> -<div>- MO_Q = MO_64,</div> -<div>-</div> -<div>- MO_LEUW = MO_LE | MO_UW,</div> -<div>- MO_LEUL = MO_LE | MO_UL,</div> -<div>- MO_LESW = MO_LE | MO_SW,</div> -<div>- MO_LESL = MO_LE | MO_SL,</div> -<div>- MO_LEQ = MO_LE | MO_Q,</div> -<div>-</div> -<div>- MO_BEUW = MO_BE | MO_UW,</div> -<div>- MO_BEUL = MO_BE | MO_UL,</div> -<div>- MO_BESW = MO_BE | MO_SW,</div> -<div>- MO_BESL = MO_BE | MO_SL,</div> -<div>- MO_BEQ = MO_BE | MO_Q,</div> -<div>-</div> -<div>- MO_TEUW = MO_TE | MO_UW,</div> -<div>- MO_TEUL = MO_TE | MO_UL,</div> -<div>- MO_TESW = MO_TE | MO_SW,</div> -<div>- MO_TESL = MO_TE | MO_SL,</div> -<div>- MO_TEQ = MO_TE | MO_Q,</div> -<div>-</div> -<div>- MO_SSIZE = MO_SIZE | MO_SIGN,</div> -<div>-} TCGMemOp;</div> -<div>-</div> -<div> /**</div> -<div> * get_alignment_bits</div> -<div>- * @memop: TCGMemOp value</div> -<div>+ * @memop: MemOp value</div> -<div> *</div> -<div> * Extract the alignment size from the memop.</div> -<div> */</div> -<div>-static inline unsigned get_alignment_bits(TCGMemOp memop)</div> -<div>+static inline unsigned get_alignment_bits(MemOp memop)</div> -<div> {</div> -<div> unsigned a = memop & MO_AMASK;</div> -<div> </div> -<div>@@ -1186,7 +1097,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)</div> -<div> return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);</div> -<div> }</div> -<div> </div> -<div>-/* Combine the TCGMemOp and mmu_idx parameters into a single value. */</div> -<div>+/* Combine the MemOp and mmu_idx parameters into a single value. */</div> -<div> typedef uint32_t TCGMemOpIdx;</div> -<div> </div> -<div> /**</div> -<div>@@ -1196,7 +1107,7 @@ typedef uint32_t TCGMemOpIdx;</div> -<div> *</div> -<div> * Encode these values into a single parameter.</div> -<div> */</div> -<div>-static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)</div> -<div>+static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)</div> -<div> {</div> -<div> tcg_debug_assert(idx <= 15);</div> -<div> return (op << 4) | idx;</div> -<div>@@ -1208,7 +1119,7 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)</div> -<div> *</div> -<div> * Extract the memory operation from the combined value.</div> -<div> */</div> -<div>-static inline TCGMemOp get_memop(TCGMemOpIdx oi)</div> -<div>+static inline MemOp get_memop(TCGMemOpIdx oi)</div> -<div> {</div> -<div> return oi >> 4;</div> -<div> }</div> -<div>diff --git a/trace/mem-internal.h b/trace/mem-internal.h</div> -<div>index f6efaf6..3444fbc 100644</div> -<div>--- a/trace/mem-internal.h</div> -<div>+++ b/trace/mem-internal.h</div> -<div>@@ -16,7 +16,7 @@</div> -<div> #define TRACE_MEM_ST (1ULL << 5) /* store (y/n) */</div> -<div> </div> -<div> static inline uint8_t trace_mem_build_info(</div> -<div>- int size_shift, bool sign_extend, TCGMemOp endianness, bool store)</div> -<div>+ int size_shift, bool sign_extend, MemOp endianness, bool store)</div> -<div> {</div> -<div> uint8_t res;</div> -<div> </div> -<div>@@ -33,7 +33,7 @@ static inline uint8_t trace_mem_build_info(</div> -<div> return res;</div> -<div> }</div> -<div> </div> -<div>-static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)</div> -<div>+static inline uint8_t trace_mem_get_info(MemOp op, bool store)</div> -<div> {</div> -<div> return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),</div> -<div> op & MO_BSWAP, store);</div> -<div>diff --git a/trace/mem.h b/trace/mem.h</div> -<div>index 2b58196..8cf213d 100644</div> -<div>--- a/trace/mem.h</div> -<div>+++ b/trace/mem.h</div> -<div>@@ -18,7 +18,7 @@</div> -<div> *</div> -<div> * Return a value for the 'info' argument in guest memory access traces.</div> -<div> */</div> -<div>-static uint8_t trace_mem_get_info(TCGMemOp op, bool store);</div> -<div>+static uint8_t trace_mem_get_info(MemOp op, bool store);</div> -<div> </div> -<div> /**</div> -<div> * trace_mem_build_info:</div> -<div>@@ -26,7 +26,7 @@ static uint8_t trace_mem_get_info(TCGMemOp op, bool store);</div> -<div> * Return a value for the 'info' argument in guest memory access traces.</div> -<div> */</div> -<div> static uint8_t trace_mem_build_info(int size_shift, bool sign_extend,</div> -<div>- TCGMemOp endianness, bool store);</div> -<div>+ MemOp endianness, bool store);</div> -<div> </div> -<div> </div> -<div> #include "trace/mem-internal.h"</div> -<div>-- </div> -<div>1.8.3.1</div> -<div><br> -​<br> -</div> -<p><br> -</p> -</body> -</html> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e54d0ae..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/html; charset="iso-8859-1" -Content-Transfer-Encoding: quoted-printable diff --git a/a/content_digest b/N3/content_digest index 3f3745a..3597a15 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,96 +1,93 @@ "ref\043bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net\0" "From\0<tony.nguyen@bt.com>\0" - "Subject\0[Qemu-riscv] [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" + "Subject\0[Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp\0" "Date\0Fri, 16 Aug 2019 07:26:59 +0000\0" "To\0<qemu-devel@nongnu.org>\0" - "Cc\0<rth@twiddle.net>" - <pbonzini@redhat.com> - <mst@redhat.com> - <imammedo@redhat.com> - <marcel.apfelbaum@gmail.com> - <xiaoguangrong.eric@gmail.com> - <alistair@alistair23.me> - <peter.maydell@linaro.org> - <b.galvani@gmail.com> - <clg@kaod.org> - <andrew@aj.id.au> - <joel@jms.id.au> - <i.mitsyanko@gmail.com> - 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<andrew.smirnov@gmail.com> - <green@moxielogic.com> - <jasowang@redhat.com> - <dmitry.fleytman@gmail.com> - <sw@weilnetz.de> - <jiri@resnulli.us> - <crwulff@gmail.com> - <marex@denx.de> - <lersek@redhat.com> - <proljc@gmail.com> - <shorne@gmail.com> - <yuval.shaia@oracle.com> - <palmer@sifive.com> - <sagark@eecs.berkeley.edu> - <kbastian@mail.uni-paderborn.de> - <walling@linux.ibm.com> - <cohuck@redhat.com> - <david@redhat.com> - <pasic@linux.ibm.com> - <borntraeger@de.ibm.com> - <fam@euphon.net> - <hare@suse.com> - <atar4qemu@gmail.com> - <stefanb@linux.ibm.com> - <alex.williamson@redhat.com> - <jcmvbkbc@gmail.com> - <laurent@vivier.eu> - <claudio.fontana@suse.com> - <stefanha@redhat.com> - <qemu-arm@nongnu.org> - <qemu-block@nongnu.org> - <qemu-ppc@nongnu.org> - <xen-devel@lists.xenproject.org> - <qemu-riscv@nongnu.org> - " <qemu-s390x@nongnu.org>\0" - "\01:1\0" + "Cc\0frederic.konrad@adacore.com" + berto@igalia.com + qemu-block@nongnu.org + arikalo@wavecomp.com + pasic@linux.ibm.com + hpoussin@reactos.org + anthony.perard@citrix.com + xen-devel@lists.xenproject.org + lersek@redhat.com + jasowang@redhat.com + jiri@resnulli.us + ehabkost@redhat.com + b.galvani@gmail.com + eric.auger@redhat.com + alex.williamson@redhat.com + stefanha@redhat.com + jsnow@redhat.com + rth@twiddle.net + kwolf@redhat.com + andrew@aj.id.au + claudio.fontana@suse.com + crwulff@gmail.com + laurent@vivier.eu + sundeep.lkml@gmail.com + michael@walle.cc + qemu-ppc@nongnu.org + kbastian@mail.uni-paderborn.de + imammedo@redhat.com + fam@euphon.net + peter.maydell@linaro.org + david@redhat.com + palmer@sifive.com + keith.busch@intel.com + jcmvbkbc@gmail.com + hare@suse.com + sstabellini@kernel.org + andrew.smirnov@gmail.com + deller@gmx.de + magnus.damm@gmail.com + atar4qemu@gmail.com + minyard@acm.org + sw@weilnetz.de + yuval.shaia@oracle.com + qemu-s390x@nongnu.org + qemu-arm@nongnu.org + jan.kiszka@web.de + clg@kaod.org + shorne@gmail.com + qemu-riscv@nongnu.org + i.mitsyanko@gmail.com + cohuck@redhat.com + philmd@redhat.com + amarkovic@wavecomp.com + peter.chubb@nicta.com.au + aurelien@aurel32.net + pburton@wavecomp.com + sagark@eecs.berkeley.edu + green@moxielogic.com + kraxel@redhat.com + edgar.iglesias@gmail.com + gxt@mprc.pku.edu.cn + robh@kernel.org + borntraeger@de.ibm.com + joel@jms.id.au + antonynpavlov@gmail.com + chouteau@adacore.com + Andrew.Baumann@microsoft.com + mreitz@redhat.com + walling@linux.ibm.com + dmitry.fleytman@gmail.com + mst@redhat.com + mark.cave-ayland@ilande.co.uk + jslaby@suse.cz + marex@denx.de + proljc@gmail.com + marcandre.lureau@redhat.com + alistair@alistair23.me + paul.durrant@citrix.com + david@gibson.dropbear.id.au + xiaoguangrong.eric@gmail.com + huth@tuxfamily.org + jcd@tribudubois.net + pbonzini@redhat.com + " stefanb@linux.ibm.com\0" + "\00:1\0" "b\0" "Preparation for collapsing the two byte swaps, adjust_endianness and\n" "handle_bswap, along the I/O path.\n" @@ -2819,2750 +2816,5 @@ "1.8.3.1\n" "\n" ? - "\01:2\0" - "b\0" - "<html>\r\n" - "<head>\r\n" - "<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\">\r\n" - "<style type=\"text/css\" style=\"display:none\"><!-- P { margin-top: 0px; margin-bottom: 0px; } .EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left-width: 2px; border-left-style: solid; border-left-color: rgb(128, 0, 0); }--></style>\r\n" - "</head>\r\n" - "<body dir=\"ltr\" style=\"font-size:12pt;color:#000000;background-color:#FFFFFF;font-family:Calibri,Arial,Helvetica,sans-serif;\">\r\n" - "<p></p>\r\n" - "<div><span style=\"font-size: 12pt;\">Preparation for collapsing the two byte swaps, adjust_endianness and</span><br>\r\n" - "</div>\r\n" - "<div>handle_bswap, along the I/O path.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Target dependant attributes are conditionalized upon NEED_CPU_H.</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>Signed-off-by: Tony Nguyen <tony.nguyen@bt.com></div>\r\n" - "<div>Acked-by: David Gibson <david@gibson.dropbear.id.au></div>\r\n" - "<div>Reviewed-by: Richard Henderson <richard.henderson@linaro.org></div>\r\n" - "<div>Acked-by: Cornelia Huck <cohuck@redhat.com></div>\r\n" - "<div>---</div>\r\n" - "<div> MAINTAINERS | 1 +</div>\r\n" - "<div> accel/tcg/cputlb.c | 2 +-</div>\r\n" - "<div> include/exec/memop.h | 110 ++++++++++++++++++++++++++</div>\r\n" - "<div> target/alpha/translate.c | 2 +-</div>\r\n" - "<div> target/arm/translate-a64.c | 48 ++++++------</div>\r\n" - "<div> target/arm/translate-a64.h | 2 +-</div>\r\n" - "<div> target/arm/translate-sve.c | 2 +-</div>\r\n" - "<div> target/arm/translate.c | 32 ++++----</div>\r\n" - "<div> target/arm/translate.h | 2 +-</div>\r\n" - "<div> target/hppa/translate.c | 14 ++--</div>\r\n" - "<div> target/i386/translate.c | 132 ++++++++++++++++----------------</div>\r\n" - "<div> target/m68k/translate.c | 2 +-</div>\r\n" - "<div> target/microblaze/translate.c | 4 +-</div>\r\n" - "<div> target/mips/translate.c | 8 +-</div>\r\n" - "<div> target/openrisc/translate.c | 4 +-</div>\r\n" - "<div> target/ppc/translate.c | 12 +--</div>\r\n" - "<div> target/riscv/insn_trans/trans_rva.inc.c | 8 +-</div>\r\n" - "<div> target/riscv/insn_trans/trans_rvi.inc.c | 4 +-</div>\r\n" - "<div> target/s390x/translate.c | 6 +-</div>\r\n" - "<div> target/s390x/translate_vx.inc.c | 10 +--</div>\r\n" - "<div> target/sparc/translate.c | 14 ++--</div>\r\n" - "<div> target/tilegx/translate.c | 10 +--</div>\r\n" - "<div> target/tricore/translate.c | 8 +-</div>\r\n" - "<div> tcg/README | 2 +-</div>\r\n" - "<div> tcg/aarch64/tcg-target.inc.c | 26 +++----</div>\r\n" - "<div> tcg/arm/tcg-target.inc.c | 26 +++----</div>\r\n" - "<div> tcg/i386/tcg-target.inc.c | 24 +++---</div>\r\n" - "<div> tcg/mips/tcg-target.inc.c | 16 ++--</div>\r\n" - "<div> tcg/optimize.c | 2 +-</div>\r\n" - "<div> tcg/ppc/tcg-target.inc.c | 12 +--</div>\r\n" - "<div> tcg/riscv/tcg-target.inc.c | 20 ++---</div>\r\n" - "<div> tcg/s390/tcg-target.inc.c | 14 ++--</div>\r\n" - "<div> tcg/sparc/tcg-target.inc.c | 6 +-</div>\r\n" - "<div> tcg/tcg-op.c | 38 ++++-----</div>\r\n" - "<div> tcg/tcg-op.h | 86 ++++++++++-----------</div>\r\n" - "<div> tcg/tcg.c | 2 +-</div>\r\n" - "<div> tcg/tcg.h | 101 ++----------------------</div>\r\n" - "<div> trace/mem-internal.h | 4 +-</div>\r\n" - "<div> trace/mem.h | 4 +-</div>\r\n" - "<div> 39 files changed, 421 insertions(+), 399 deletions(-)</div>\r\n" - "<div> create mode 100644 include/exec/memop.h</div>\r\n" - "<div><br>\r\n" - "</div>\r\n" - "<div>diff --git a/MAINTAINERS b/MAINTAINERS</div>\r\n" - "<div>index d6de200..c7cf84a 100644</div>\r\n" - "<div>--- a/MAINTAINERS</div>\r\n" - "<div>+++ b/MAINTAINERS</div>\r\n" - "<div>@@ -1889,6 +1889,7 @@ M: Paolo Bonzini <pbonzini@redhat.com></div>\r\n" - "<div> S: Supported</div>\r\n" - "<div> F: include/exec/ioport.h</div>\r\n" - "<div> F: ioport.c</div>\r\n" - "<div>+F: include/exec/memop.h</div>\r\n" - "<div> F: include/exec/memory.h</div>\r\n" - "<div> F: include/exec/ram_addr.h</div>\r\n" - "<div> F: memory.c</div>\r\n" - "<div>diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c</div>\r\n" - "<div>index bb9897b..523be4c 100644</div>\r\n" - "<div>--- a/accel/tcg/cputlb.c</div>\r\n" - "<div>+++ b/accel/tcg/cputlb.c</div>\r\n" - "<div>@@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,</div>\r\n" - "<div> uintptr_t index = tlb_index(env, mmu_idx, addr);</div>\r\n" - "<div> CPUTLBEntry *tlbe = tlb_entry(env, mmu_idx, addr);</div>\r\n" - "<div> target_ulong tlb_addr = tlb_addr_write(tlbe);</div>\r\n" - "<div>- TCGMemOp mop = get_memop(oi);</div>\r\n" - "<div>+ MemOp mop = get_memop(oi);</div>\r\n" - "<div> int a_bits = get_alignment_bits(mop);</div>\r\n" - "<div> int s_bits = mop & MO_SIZE;</div>\r\n" - "<div> void *hostaddr;</div>\r\n" - "<div>diff --git a/include/exec/memop.h b/include/exec/memop.h</div>\r\n" - "<div>new file mode 100644</div>\r\n" - "<div>index 0000000..7262ca3</div>\r\n" - "<div>--- /dev/null</div>\r\n" - "<div>+++ b/include/exec/memop.h</div>\r\n" - "<div>@@ -0,0 +1,110 @@</div>\r\n" - "<div>+/*</div>\r\n" - "<div>+ * Constants for memory operations</div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ * Authors:</div>\r\n" - "<div>+ * Richard Henderson <rth@twiddle.net></div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ * This work is licensed under the terms of the GNU GPL, version 2 or later.</div>\r\n" - "<div>+ * See the COPYING file in the top-level directory.</div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ */</div>\r\n" - "<div>+</div>\r\n" - "<div>+#ifndef MEMOP_H</div>\r\n" - "<div>+#define MEMOP_H</div>\r\n" - "<div>+</div>\r\n" - "<div>+typedef enum MemOp {</div>\r\n" - "<div>+ MO_8 = 0,</div>\r\n" - "<div>+ MO_16 = 1,</div>\r\n" - "<div>+ MO_32 = 2,</div>\r\n" - "<div>+ MO_64 = 3,</div>\r\n" - "<div>+ MO_SIZE = 3, /* Mask for the above. */</div>\r\n" - "<div>+</div>\r\n" - "<div>+ MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */</div>\r\n" - "<div>+</div>\r\n" - "<div>+ MO_BSWAP = 8, /* Host reverse endian. */</div>\r\n" - "<div>+#ifdef HOST_WORDS_BIGENDIAN</div>\r\n" - "<div>+ MO_LE = MO_BSWAP,</div>\r\n" - "<div>+ MO_BE = 0,</div>\r\n" - "<div>+#else</div>\r\n" - "<div>+ MO_LE = 0,</div>\r\n" - "<div>+ MO_BE = MO_BSWAP,</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+#ifdef NEED_CPU_H</div>\r\n" - "<div>+#ifdef TARGET_WORDS_BIGENDIAN</div>\r\n" - "<div>+ MO_TE = MO_BE,</div>\r\n" - "<div>+#else</div>\r\n" - "<div>+ MO_TE = MO_LE,</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+</div>\r\n" - "<div>+ /*</div>\r\n" - "<div>+ * MO_UNALN accesses are never checked for alignment.</div>\r\n" - "<div>+ * MO_ALIGN accesses will result in a call to the CPU's</div>\r\n" - "<div>+ * do_unaligned_access hook if the guest address is not aligned.</div>\r\n" - "<div>+ * The default depends on whether the target CPU defines</div>\r\n" - "<div>+ * TARGET_ALIGNED_ONLY.</div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ * Some architectures (e.g. ARMv8) need the address which is aligned</div>\r\n" - "<div>+ * to a size more than the size of the memory access.</div>\r\n" - "<div>+ * Some architectures (e.g. SPARCv9) need an address which is aligned,</div>\r\n" - "<div>+ * but less strictly than the natural alignment.</div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ * MO_ALIGN supposes the alignment size is the size of a memory access.</div>\r\n" - "<div>+ *</div>\r\n" - "<div>+ * There are three options:</div>\r\n" - "<div>+ * - unaligned access permitted (MO_UNALN).</div>\r\n" - "<div>+ * - an alignment to the size of an access (MO_ALIGN);</div>\r\n" - "<div>+ * - an alignment to a specified size, which may be more or less than</div>\r\n" - "<div>+ * the access size (MO_ALIGN_x where 'x' is a size in bytes);</div>\r\n" - "<div>+ */</div>\r\n" - "<div>+ MO_ASHIFT = 4,</div>\r\n" - "<div>+ MO_AMASK = 7 << MO_ASHIFT,</div>\r\n" - "<div>+#ifdef NEED_CPU_H</div>\r\n" - "<div>+#ifdef TARGET_ALIGNED_ONLY</div>\r\n" - "<div>+ MO_ALIGN = 0,</div>\r\n" - "<div>+ MO_UNALN = MO_AMASK,</div>\r\n" - "<div>+#else</div>\r\n" - "<div>+ MO_ALIGN = MO_AMASK,</div>\r\n" - "<div>+ MO_UNALN = 0,</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+ MO_ALIGN_2 = 1 << MO_ASHIFT,</div>\r\n" - "<div>+ MO_ALIGN_4 = 2 << MO_ASHIFT,</div>\r\n" - "<div>+ MO_ALIGN_8 = 3 << MO_ASHIFT,</div>\r\n" - "<div>+ MO_ALIGN_16 = 4 << MO_ASHIFT,</div>\r\n" - "<div>+ MO_ALIGN_32 = 5 << MO_ASHIFT,</div>\r\n" - "<div>+ MO_ALIGN_64 = 6 << MO_ASHIFT,</div>\r\n" - "<div>+</div>\r\n" - "<div>+ /* Combinations of the above, for ease of use. */</div>\r\n" - "<div>+ MO_UB = MO_8,</div>\r\n" - "<div>+ MO_UW = MO_16,</div>\r\n" - "<div>+ MO_UL = MO_32,</div>\r\n" - "<div>+ MO_SB = MO_SIGN | MO_8,</div>\r\n" - "<div>+ MO_SW = MO_SIGN | MO_16,</div>\r\n" - "<div>+ MO_SL = MO_SIGN | MO_32,</div>\r\n" - "<div>+ MO_Q = MO_64,</div>\r\n" - "<div>+</div>\r\n" - "<div>+ MO_LEUW = MO_LE | MO_UW,</div>\r\n" - "<div>+ MO_LEUL = MO_LE | MO_UL,</div>\r\n" - "<div>+ MO_LESW = MO_LE | MO_SW,</div>\r\n" - "<div>+ MO_LESL = MO_LE | MO_SL,</div>\r\n" - "<div>+ MO_LEQ = MO_LE | MO_Q,</div>\r\n" - "<div>+</div>\r\n" - "<div>+ MO_BEUW = MO_BE | MO_UW,</div>\r\n" - "<div>+ MO_BEUL = MO_BE | MO_UL,</div>\r\n" - "<div>+ MO_BESW = MO_BE | MO_SW,</div>\r\n" - "<div>+ MO_BESL = MO_BE | MO_SL,</div>\r\n" - "<div>+ MO_BEQ = MO_BE | MO_Q,</div>\r\n" - "<div>+</div>\r\n" - "<div>+#ifdef NEED_CPU_H</div>\r\n" - "<div>+ MO_TEUW = MO_TE | MO_UW,</div>\r\n" - "<div>+ MO_TEUL = MO_TE | MO_UL,</div>\r\n" - "<div>+ MO_TESW = MO_TE | MO_SW,</div>\r\n" - "<div>+ MO_TESL = MO_TE | MO_SL,</div>\r\n" - "<div>+ MO_TEQ = MO_TE | MO_Q,</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>+</div>\r\n" - "<div>+ MO_SSIZE = MO_SIZE | MO_SIGN,</div>\r\n" - "<div>+} MemOp;</div>\r\n" - "<div>+</div>\r\n" - "<div>+#endif</div>\r\n" - "<div>diff --git a/target/alpha/translate.c b/target/alpha/translate.c</div>\r\n" - "<div>index 2c9cccf..d5d4888 100644</div>\r\n" - "<div>--- a/target/alpha/translate.c</div>\r\n" - "<div>+++ b/target/alpha/translate.c</div>\r\n" - "<div>@@ -403,7 +403,7 @@ static inline void gen_store_mem(DisasContext *ctx,</div>\r\n" - "<div> </div>\r\n" - "<div> static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,</div>\r\n" - "<div> int32_t disp16, int mem_idx,</div>\r\n" - "<div>- TCGMemOp op)</div>\r\n" - "<div>+ MemOp op)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGLabel *lab_fail, *lab_done;</div>\r\n" - "<div> TCGv addr, val;</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c</div>\r\n" - "<div>index d323147..b6c07d6 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.c</div>\r\n" - "<div>+++ b/target/arm/translate-a64.c</div>\r\n" - "<div>@@ -85,7 +85,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);</div>\r\n" - "<div> typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);</div>\r\n" - "<div> typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);</div>\r\n" - "<div> typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);</div>\r\n" - "<div>-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div> </div>\r\n" - "<div> /* initialize TCG globals. */</div>\r\n" - "<div> void a64_translate_init(void)</div>\r\n" - "<div>@@ -455,7 +455,7 @@ TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)</div>\r\n" - "<div> * Dn, Sn, Hn or Bn).</div>\r\n" - "<div> * (Note that this is not the same mapping as for A32; see cpu.h)</div>\r\n" - "<div> */</div>\r\n" - "<div>-static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)</div>\r\n" - "<div>+static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size)</div>\r\n" - "<div> {</div>\r\n" - "<div> return vec_reg_offset(s, regno, 0, size);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -871,7 +871,7 @@ static void do_gpr_ld_memidx(DisasContext *s,</div>\r\n" - "<div> bool iss_valid, unsigned int iss_srt,</div>\r\n" - "<div> bool iss_sf, bool iss_ar)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp memop = s->be_data + size;</div>\r\n" - "<div>+ MemOp memop = s->be_data + size;</div>\r\n" - "<div> </div>\r\n" - "<div> g_assert(size <= 3);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -948,7 +948,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div>\r\n" - "<div> TCGv_i64 tmphi;</div>\r\n" - "<div> </div>\r\n" - "<div> if (size < 4) {</div>\r\n" - "<div>- TCGMemOp memop = s->be_data + size;</div>\r\n" - "<div>+ MemOp memop = s->be_data + size;</div>\r\n" - "<div> tmphi = tcg_const_i64(0);</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);</div>\r\n" - "<div> } else {</div>\r\n" - "<div>@@ -989,7 +989,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)</div>\r\n" - "<div> </div>\r\n" - "<div> /* Get value of an element within a vector register */</div>\r\n" - "<div> static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div>- int element, TCGMemOp memop)</div>\r\n" - "<div>+ int element, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>@@ -1021,7 +1021,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div>\r\n" - "<div>- int element, TCGMemOp memop)</div>\r\n" - "<div>+ int element, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>@@ -1048,7 +1048,7 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,</div>\r\n" - "<div> </div>\r\n" - "<div> /* Set value of an element within a vector register */</div>\r\n" - "<div> static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div>- int element, TCGMemOp memop)</div>\r\n" - "<div>+ int element, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>@@ -1070,7 +1070,7 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div>\r\n" - "<div>- int destidx, int element, TCGMemOp memop)</div>\r\n" - "<div>+ int destidx, int element, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);</div>\r\n" - "<div> switch (memop) {</div>\r\n" - "<div>@@ -1090,7 +1090,7 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,</div>\r\n" - "<div> </div>\r\n" - "<div> /* Store from vector register to memory */</div>\r\n" - "<div> static void do_vec_st(DisasContext *s, int srcidx, int element,</div>\r\n" - "<div>- TCGv_i64 tcg_addr, int size, TCGMemOp endian)</div>\r\n" - "<div>+ TCGv_i64 tcg_addr, int size, MemOp endian)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1102,7 +1102,7 @@ static void do_vec_st(DisasContext *s, int srcidx, int element,</div>\r\n" - "<div> </div>\r\n" - "<div> /* Load from memory to vector register */</div>\r\n" - "<div> static void do_vec_ld(DisasContext *s, int destidx, int element,</div>\r\n" - "<div>- TCGv_i64 tcg_addr, int size, TCGMemOp endian)</div>\r\n" - "<div>+ TCGv_i64 tcg_addr, int size, MemOp endian)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 tcg_tmp = tcg_temp_new_i64();</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2200,7 +2200,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div>\r\n" - "<div> TCGv_i64 addr, int size, bool is_pair)</div>\r\n" - "<div> {</div>\r\n" - "<div> int idx = get_mem_index(s);</div>\r\n" - "<div>- TCGMemOp memop = s->be_data;</div>\r\n" - "<div>+ MemOp memop = s->be_data;</div>\r\n" - "<div> </div>\r\n" - "<div> g_assert(size <= 3);</div>\r\n" - "<div> if (is_pair) {</div>\r\n" - "<div>@@ -3286,7 +3286,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> bool is_postidx = extract32(insn, 23, 1);</div>\r\n" - "<div> bool is_q = extract32(insn, 30, 1);</div>\r\n" - "<div> TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;</div>\r\n" - "<div>- TCGMemOp endian = s->be_data;</div>\r\n" - "<div>+ MemOp endian = s->be_data;</div>\r\n" - "<div> </div>\r\n" - "<div> int ebytes; /* bytes per element */</div>\r\n" - "<div> int elements; /* elements per vector */</div>\r\n" - "<div>@@ -5455,7 +5455,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> unsigned int mos, type, rm, cond, rn, rd;</div>\r\n" - "<div> TCGv_i64 t_true, t_false, t_zero;</div>\r\n" - "<div> DisasCompare64 c;</div>\r\n" - "<div>- TCGMemOp sz;</div>\r\n" - "<div>+ MemOp sz;</div>\r\n" - "<div> </div>\r\n" - "<div> mos = extract32(insn, 29, 3);</div>\r\n" - "<div> type = extract32(insn, 22, 2);</div>\r\n" - "<div>@@ -6267,7 +6267,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> int mos = extract32(insn, 29, 3);</div>\r\n" - "<div> uint64_t imm;</div>\r\n" - "<div> TCGv_i64 tcg_res;</div>\r\n" - "<div>- TCGMemOp sz;</div>\r\n" - "<div>+ MemOp sz;</div>\r\n" - "<div> </div>\r\n" - "<div> if (mos || imm5) {</div>\r\n" - "<div> unallocated_encoding(s);</div>\r\n" - "<div>@@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,</div>\r\n" - "<div> {</div>\r\n" - "<div> if (esize == size) {</div>\r\n" - "<div> int element;</div>\r\n" - "<div>- TCGMemOp msize = esize == 16 ? MO_16 : MO_32;</div>\r\n" - "<div>+ MemOp msize = esize == 16 ? MO_16 : MO_32;</div>\r\n" - "<div> TCGv_i32 tcg_elem;</div>\r\n" - "<div> </div>\r\n" - "<div> /* We should have one register left here */</div>\r\n" - "<div>@@ -8022,7 +8022,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,</div>\r\n" - "<div> int shift = (2 * esize) - immhb;</div>\r\n" - "<div> int elements = is_scalar ? 1 : (64 / esize);</div>\r\n" - "<div> bool round = extract32(opcode, 0, 1);</div>\r\n" - "<div>- TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);</div>\r\n" - "<div>+ MemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);</div>\r\n" - "<div> TCGv_i64 tcg_rn, tcg_rd, tcg_round;</div>\r\n" - "<div> TCGv_i32 tcg_rd_narrowed;</div>\r\n" - "<div> TCGv_i64 tcg_final;</div>\r\n" - "<div>@@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,</div>\r\n" - "<div> }</div>\r\n" - "<div> };</div>\r\n" - "<div> NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];</div>\r\n" - "<div>- TCGMemOp memop = scalar ? size : MO_32;</div>\r\n" - "<div>+ MemOp memop = scalar ? size : MO_32;</div>\r\n" - "<div> int maxpass = scalar ? 1 : is_q ? 4 : 2;</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div>@@ -8225,7 +8225,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,</div>\r\n" - "<div> TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);</div>\r\n" - "<div> TCGv_i32 tcg_shift = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div>- TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);</div>\r\n" - "<div>+ MemOp mop = size | (is_signed ? MO_SIGN : 0);</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> </div>\r\n" - "<div> if (fracbits || size == MO_64) {</div>\r\n" - "<div>@@ -10004,7 +10004,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,</div>\r\n" - "<div> int dsize = is_q ? 128 : 64;</div>\r\n" - "<div> int esize = 8 << size;</div>\r\n" - "<div> int elements = dsize/esize;</div>\r\n" - "<div>- TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);</div>\r\n" - "<div>+ MemOp memop = size | (is_u ? 0 : MO_SIGN);</div>\r\n" - "<div> TCGv_i64 tcg_rn = new_tmp_a64(s);</div>\r\n" - "<div> TCGv_i64 tcg_rd = new_tmp_a64(s);</div>\r\n" - "<div> TCGv_i64 tcg_round;</div>\r\n" - "<div>@@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,</div>\r\n" - "<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_op2 = tcg_temp_new_i64();</div>\r\n" - "<div> TCGv_i64 tcg_passres;</div>\r\n" - "<div>- TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div>\r\n" - "<div>+ MemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);</div>\r\n" - "<div> </div>\r\n" - "<div> int elt = pass + is_q * 2;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -11827,7 +11827,7 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,</div>\r\n" - "<div> </div>\r\n" - "<div> if (size == 2) {</div>\r\n" - "<div> /* 32 + 32 -> 64 op */</div>\r\n" - "<div>- TCGMemOp memop = size + (u ? 0 : MO_SIGN);</div>\r\n" - "<div>+ MemOp memop = size + (u ? 0 : MO_SIGN);</div>\r\n" - "<div> </div>\r\n" - "<div> for (pass = 0; pass < maxpass; pass++) {</div>\r\n" - "<div> TCGv_i64 tcg_op1 = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -12849,7 +12849,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> </div>\r\n" - "<div> switch (is_fp) {</div>\r\n" - "<div> case 1: /* normal fp */</div>\r\n" - "<div>- /* convert insn encoded size to TCGMemOp size */</div>\r\n" - "<div>+ /* convert insn encoded size to MemOp size */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case 0: /* half-precision */</div>\r\n" - "<div> size = MO_16;</div>\r\n" - "<div>@@ -12897,7 +12897,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> return;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>- /* Given TCGMemOp size, adjust register and indexing. */</div>\r\n" - "<div>+ /* Given MemOp size, adjust register and indexing. */</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case MO_16:</div>\r\n" - "<div> index = h << 2 | l << 1 | m;</div>\r\n" - "<div>@@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> TCGv_i64 tcg_res[2];</div>\r\n" - "<div> int pass;</div>\r\n" - "<div> bool satop = extract32(opcode, 0, 1);</div>\r\n" - "<div>- TCGMemOp memop = MO_32;</div>\r\n" - "<div>+ MemOp memop = MO_32;</div>\r\n" - "<div> </div>\r\n" - "<div> if (satop || !u) {</div>\r\n" - "<div> memop |= MO_SIGN;</div>\r\n" - "<div>diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h</div>\r\n" - "<div>index 9ab4087..f1246b7 100644</div>\r\n" - "<div>--- a/target/arm/translate-a64.h</div>\r\n" - "<div>+++ b/target/arm/translate-a64.h</div>\r\n" - "<div>@@ -64,7 +64,7 @@ static inline void assert_fp_access_checked(DisasContext *s)</div>\r\n" - "<div> * the FP/vector register Qn.</div>\r\n" - "<div> */</div>\r\n" - "<div> static inline int vec_reg_offset(DisasContext *s, int regno,</div>\r\n" - "<div>- int element, TCGMemOp size)</div>\r\n" - "<div>+ int element, MemOp size)</div>\r\n" - "<div> {</div>\r\n" - "<div> int element_size = 1 << size;</div>\r\n" - "<div> int offs = element * element_size;</div>\r\n" - "<div>diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c</div>\r\n" - "<div>index fa068b0..5d7edd0 100644</div>\r\n" - "<div>--- a/target/arm/translate-sve.c</div>\r\n" - "<div>+++ b/target/arm/translate-sve.c</div>\r\n" - "<div>@@ -4567,7 +4567,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)</div>\r\n" - "<div> */</div>\r\n" - "<div> </div>\r\n" - "<div> /* The memory mode of the dtype. */</div>\r\n" - "<div>-static const TCGMemOp dtype_mop[16] = {</div>\r\n" - "<div>+static const MemOp dtype_mop[16] = {</div>\r\n" - "<div> MO_UB, MO_UB, MO_UB, MO_UB,</div>\r\n" - "<div> MO_SL, MO_UW, MO_UW, MO_UW,</div>\r\n" - "<div> MO_SW, MO_SW, MO_UL, MO_UL,</div>\r\n" - "<div>diff --git a/target/arm/translate.c b/target/arm/translate.c</div>\r\n" - "<div>index 7853462..d116c8c 100644</div>\r\n" - "<div>--- a/target/arm/translate.c</div>\r\n" - "<div>+++ b/target/arm/translate.c</div>\r\n" - "<div>@@ -114,7 +114,7 @@ typedef enum ISSInfo {</div>\r\n" - "<div> } ISSInfo;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Save the syndrome information for a Data Abort */</div>\r\n" - "<div>-static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)</div>\r\n" - "<div>+static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo)</div>\r\n" - "<div> {</div>\r\n" - "<div> uint32_t syn;</div>\r\n" - "<div> int sas = memop & MO_SIZE;</div>\r\n" - "<div>@@ -1079,7 +1079,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)</div>\r\n" - "<div> * that the address argument is TCGv_i32 rather than TCGv.</div>\r\n" - "<div> */</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div>\r\n" - "<div>+static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_extu_i32_tl(addr, a32);</div>\r\n" - "<div>@@ -1092,7 +1092,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div>\r\n" - "<div>- int index, TCGMemOp opc)</div>\r\n" - "<div>+ int index, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1107,7 +1107,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,</div>\r\n" - "<div>- int index, TCGMemOp opc)</div>\r\n" - "<div>+ int index, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1160,7 +1160,7 @@ static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div>\r\n" - "<div>- int index, TCGMemOp opc)</div>\r\n" - "<div>+ int index, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr = gen_aa32_addr(s, a32, opc);</div>\r\n" - "<div> tcg_gen_qemu_ld_i64(val, addr, index, opc);</div>\r\n" - "<div>@@ -1175,7 +1175,7 @@ static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,</div>\r\n" - "<div>- int index, TCGMemOp opc)</div>\r\n" - "<div>+ int index, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr = gen_aa32_addr(s, a32, opc);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1400,7 +1400,7 @@ neon_reg_offset (int reg, int n)</div>\r\n" - "<div> * where 0 is the least significant end of the register.</div>\r\n" - "<div> */</div>\r\n" - "<div> static inline long</div>\r\n" - "<div>-neon_element_offset(int reg, int element, TCGMemOp size)</div>\r\n" - "<div>+neon_element_offset(int reg, int element, MemOp size)</div>\r\n" - "<div> {</div>\r\n" - "<div> int element_size = 1 << size;</div>\r\n" - "<div> int ofs = element * element_size;</div>\r\n" - "<div>@@ -1422,7 +1422,7 @@ static TCGv_i32 neon_load_reg(int reg, int pass)</div>\r\n" - "<div> return tmp;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)</div>\r\n" - "<div>+static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, mop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1441,7 +1441,7 @@ static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)</div>\r\n" - "<div>+static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, mop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1469,7 +1469,7 @@ static void neon_store_reg(int reg, int pass, TCGv_i32 var)</div>\r\n" - "<div> tcg_temp_free_i32(var);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div>\r\n" - "<div>+static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var)</div>\r\n" - "<div> {</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, size);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1488,7 +1488,7 @@ static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)</div>\r\n" - "<div>+static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)</div>\r\n" - "<div> {</div>\r\n" - "<div> long offset = neon_element_offset(reg, ele, size);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3558,7 +3558,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> int n;</div>\r\n" - "<div> int vec_size;</div>\r\n" - "<div> int mmu_idx;</div>\r\n" - "<div>- TCGMemOp endian;</div>\r\n" - "<div>+ MemOp endian;</div>\r\n" - "<div> TCGv_i32 addr;</div>\r\n" - "<div> TCGv_i32 tmp;</div>\r\n" - "<div> TCGv_i32 tmp2;</div>\r\n" - "<div>@@ -6867,7 +6867,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)</div>\r\n" - "<div> } else if ((insn & 0x380) == 0) {</div>\r\n" - "<div> /* VDUP */</div>\r\n" - "<div> int element;</div>\r\n" - "<div>- TCGMemOp size;</div>\r\n" - "<div>+ MemOp size;</div>\r\n" - "<div> </div>\r\n" - "<div> if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {</div>\r\n" - "<div> return 1;</div>\r\n" - "<div>@@ -7435,7 +7435,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,</div>\r\n" - "<div> TCGv_i32 addr, int size)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 tmp = tcg_temp_new_i32();</div>\r\n" - "<div>- TCGMemOp opc = size | MO_ALIGN | s->be_data;</div>\r\n" - "<div>+ MemOp opc = size | MO_ALIGN | s->be_data;</div>\r\n" - "<div> </div>\r\n" - "<div> s->is_ldex = true;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -7489,7 +7489,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,</div>\r\n" - "<div> TCGv taddr;</div>\r\n" - "<div> TCGLabel *done_label;</div>\r\n" - "<div> TCGLabel *fail_label;</div>\r\n" - "<div>- TCGMemOp opc = size | MO_ALIGN | s->be_data;</div>\r\n" - "<div>+ MemOp opc = size | MO_ALIGN | s->be_data;</div>\r\n" - "<div> </div>\r\n" - "<div> /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {</div>\r\n" - "<div> [addr] = {Rt};</div>\r\n" - "<div>@@ -8603,7 +8603,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)</div>\r\n" - "<div> */</div>\r\n" - "<div> </div>\r\n" - "<div> TCGv taddr;</div>\r\n" - "<div>- TCGMemOp opc = s->be_data;</div>\r\n" - "<div>+ MemOp opc = s->be_data;</div>\r\n" - "<div> </div>\r\n" - "<div> rm = (insn) & 0xf;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/arm/translate.h b/target/arm/translate.h</div>\r\n" - "<div>index a20f6e2..284c510 100644</div>\r\n" - "<div>--- a/target/arm/translate.h</div>\r\n" - "<div>+++ b/target/arm/translate.h</div>\r\n" - "<div>@@ -21,7 +21,7 @@ typedef struct DisasContext {</div>\r\n" - "<div> int condexec_cond;</div>\r\n" - "<div> int thumb;</div>\r\n" - "<div> int sctlr_b;</div>\r\n" - "<div>- TCGMemOp be_data;</div>\r\n" - "<div>+ MemOp be_data;</div>\r\n" - "<div> #if !defined(CONFIG_USER_ONLY)</div>\r\n" - "<div> int user;</div>\r\n" - "<div> #endif</div>\r\n" - "<div>diff --git a/target/hppa/translate.c b/target/hppa/translate.c</div>\r\n" - "<div>index 188fe68..ff4802a 100644</div>\r\n" - "<div>--- a/target/hppa/translate.c</div>\r\n" - "<div>+++ b/target/hppa/translate.c</div>\r\n" - "<div>@@ -1500,7 +1500,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,</div>\r\n" - "<div> */</div>\r\n" - "<div> static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,</div>\r\n" - "<div> unsigned rx, int scale, target_sreg disp,</div>\r\n" - "<div>- unsigned sp, int modify, TCGMemOp mop)</div>\r\n" - "<div>+ unsigned sp, int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_reg ofs;</div>\r\n" - "<div> TCGv_tl addr;</div>\r\n" - "<div>@@ -1518,7 +1518,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,</div>\r\n" - "<div> unsigned rx, int scale, target_sreg disp,</div>\r\n" - "<div>- unsigned sp, int modify, TCGMemOp mop)</div>\r\n" - "<div>+ unsigned sp, int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_reg ofs;</div>\r\n" - "<div> TCGv_tl addr;</div>\r\n" - "<div>@@ -1536,7 +1536,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,</div>\r\n" - "<div> unsigned rx, int scale, target_sreg disp,</div>\r\n" - "<div>- unsigned sp, int modify, TCGMemOp mop)</div>\r\n" - "<div>+ unsigned sp, int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_reg ofs;</div>\r\n" - "<div> TCGv_tl addr;</div>\r\n" - "<div>@@ -1554,7 +1554,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,</div>\r\n" - "<div> unsigned rx, int scale, target_sreg disp,</div>\r\n" - "<div>- unsigned sp, int modify, TCGMemOp mop)</div>\r\n" - "<div>+ unsigned sp, int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_reg ofs;</div>\r\n" - "<div> TCGv_tl addr;</div>\r\n" - "<div>@@ -1580,7 +1580,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,</div>\r\n" - "<div> </div>\r\n" - "<div> static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,</div>\r\n" - "<div> unsigned rx, int scale, target_sreg disp,</div>\r\n" - "<div>- unsigned sp, int modify, TCGMemOp mop)</div>\r\n" - "<div>+ unsigned sp, int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_reg dest;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1653,7 +1653,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a)</div>\r\n" - "<div> </div>\r\n" - "<div> static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,</div>\r\n" - "<div> target_sreg disp, unsigned sp,</div>\r\n" - "<div>- int modify, TCGMemOp mop)</div>\r\n" - "<div>+ int modify, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> nullify_over(ctx);</div>\r\n" - "<div> do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);</div>\r\n" - "<div>@@ -2940,7 +2940,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)</div>\r\n" - "<div> </div>\r\n" - "<div> static bool trans_ldc(DisasContext *ctx, arg_ldst *a)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;</div>\r\n" - "<div>+ MemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;</div>\r\n" - "<div> TCGv_reg zero, dest, ofs;</div>\r\n" - "<div> TCGv_tl addr;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/i386/translate.c b/target/i386/translate.c</div>\r\n" - "<div>index 03150a8..def9867 100644</div>\r\n" - "<div>--- a/target/i386/translate.c</div>\r\n" - "<div>+++ b/target/i386/translate.c</div>\r\n" - "<div>@@ -87,8 +87,8 @@ typedef struct DisasContext {</div>\r\n" - "<div> /* current insn context */</div>\r\n" - "<div> int override; /* -1 if no override */</div>\r\n" - "<div> int prefix;</div>\r\n" - "<div>- TCGMemOp aflag;</div>\r\n" - "<div>- TCGMemOp dflag;</div>\r\n" - "<div>+ MemOp aflag;</div>\r\n" - "<div>+ MemOp dflag;</div>\r\n" - "<div> target_ulong pc_start;</div>\r\n" - "<div> target_ulong pc; /* pc = eip + cs_base */</div>\r\n" - "<div> /* current block context */</div>\r\n" - "<div>@@ -149,7 +149,7 @@ static void gen_eob(DisasContext *s);</div>\r\n" - "<div> static void gen_jr(DisasContext *s, TCGv dest);</div>\r\n" - "<div> static void gen_jmp(DisasContext *s, target_ulong eip);</div>\r\n" - "<div> static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);</div>\r\n" - "<div>-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d);</div>\r\n" - "<div>+static void gen_op(DisasContext *s1, int op, MemOp ot, int d);</div>\r\n" - "<div> </div>\r\n" - "<div> /* i386 arith/logic operations */</div>\r\n" - "<div> enum {</div>\r\n" - "<div>@@ -320,7 +320,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int reg)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select the size of a push/pop operation. */</div>\r\n" - "<div>-static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline MemOp mo_pushpop(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (CODE64(s)) {</div>\r\n" - "<div> return ot == MO_16 ? MO_16 : MO_64;</div>\r\n" - "<div>@@ -330,13 +330,13 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select the size of the stack pointer. */</div>\r\n" - "<div>-static inline TCGMemOp mo_stacksize(DisasContext *s)</div>\r\n" - "<div>+static inline MemOp mo_stacksize(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div> return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select only size 64 else 32. Used for SSE operand sizes. */</div>\r\n" - "<div>-static inline TCGMemOp mo_64_32(TCGMemOp ot)</div>\r\n" - "<div>+static inline MemOp mo_64_32(MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> #ifdef TARGET_X86_64</div>\r\n" - "<div> return ot == MO_64 ? MO_64 : MO_32;</div>\r\n" - "<div>@@ -347,19 +347,19 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot)</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select size 8 if lsb of B is clear, else OT. Used for decoding</div>\r\n" - "<div> byte vs word opcodes. */</div>\r\n" - "<div>-static inline TCGMemOp mo_b_d(int b, TCGMemOp ot)</div>\r\n" - "<div>+static inline MemOp mo_b_d(int b, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> return b & 1 ? ot : MO_8;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* Select size 8 if lsb of B is clear, else OT capped at 32.</div>\r\n" - "<div> Used for decoding operand size of port opcodes. */</div>\r\n" - "<div>-static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot)</div>\r\n" - "<div>+static inline MemOp mo_b_d32(int b, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> return b & 1 ? (ot == MO_16 ? MO_16 : MO_32) : MO_8;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div>+static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch(ot) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -388,7 +388,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t0)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline</div>\r\n" - "<div>-void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg)</div>\r\n" - "<div>+void gen_op_mov_v_reg(DisasContext *s, MemOp ot, TCGv t0, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (ot == MO_8 && byte_reg_is_xH(s, reg)) {</div>\r\n" - "<div> tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);</div>\r\n" - "<div>@@ -411,13 +411,13 @@ static inline void gen_op_jmp_v(TCGv dest)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline</div>\r\n" - "<div>-void gen_op_add_reg_im(DisasContext *s, TCGMemOp size, int reg, int32_t val)</div>\r\n" - "<div>+void gen_op_add_reg_im(DisasContext *s, MemOp size, int reg, int32_t val)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_addi_tl(s->tmp0, cpu_regs[reg], val);</div>\r\n" - "<div> gen_op_mov_reg_v(s, size, reg, s->tmp0);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_op_add_reg_T0(DisasContext *s, TCGMemOp size, int reg)</div>\r\n" - "<div>+static inline void gen_op_add_reg_T0(DisasContext *s, MemOp size, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_add_tl(s->tmp0, cpu_regs[reg], s->T0);</div>\r\n" - "<div> gen_op_mov_reg_v(s, size, reg, s->tmp0);</div>\r\n" - "<div>@@ -451,7 +451,7 @@ static inline void gen_jmp_im(DisasContext *s, target_ulong pc)</div>\r\n" - "<div> /* Compute SEG:REG into A0. SEG is selected from the override segment</div>\r\n" - "<div> (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to</div>\r\n" - "<div> indicate no override. */</div>\r\n" - "<div>-static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,</div>\r\n" - "<div>+static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,</div>\r\n" - "<div> int def_seg, int ovr_seg)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (aflag) {</div>\r\n" - "<div>@@ -514,13 +514,13 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s)</div>\r\n" - "<div> gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df));</div>\r\n" - "<div> tcg_gen_shli_tl(s->T0, s->T0, ot);</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div>-static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div>\r\n" - "<div>+static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (size) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -551,18 +551,18 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_extu(TCGMemOp ot, TCGv reg)</div>\r\n" - "<div>+static void gen_extu(MemOp ot, TCGv reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_ext_tl(reg, reg, ot, false);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_exts(TCGMemOp ot, TCGv reg)</div>\r\n" - "<div>+static void gen_exts(MemOp ot, TCGv reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_ext_tl(reg, reg, ot, true);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline</div>\r\n" - "<div>-void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div>\r\n" - "<div>+void gen_op_jnz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);</div>\r\n" - "<div> gen_extu(size, s->tmp0);</div>\r\n" - "<div>@@ -570,14 +570,14 @@ void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline</div>\r\n" - "<div>-void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1)</div>\r\n" - "<div>+void gen_op_jz_ecx(DisasContext *s, MemOp size, TCGLabel *label1)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]);</div>\r\n" - "<div> gen_extu(size, s->tmp0);</div>\r\n" - "<div> tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div>+static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -594,7 +594,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div>+static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (ot) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -611,7 +611,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div>\r\n" - "<div>+static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip,</div>\r\n" - "<div> uint32_t svm_flags)</div>\r\n" - "<div> {</div>\r\n" - "<div> target_ulong next_eip;</div>\r\n" - "<div>@@ -644,7 +644,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_movs(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_movs(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_string_movl_A0_ESI(s);</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T0, s->A0);</div>\r\n" - "<div>@@ -840,7 +840,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)</div>\r\n" - "<div> return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };</div>\r\n" - "<div> default:</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div>\r\n" - "<div>+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div>\r\n" - "<div> TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);</div>\r\n" - "<div> return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -885,7 +885,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)</div>\r\n" - "<div> .mask = -1 };</div>\r\n" - "<div> default:</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div>\r\n" - "<div>+ MemOp size = (s->cc_op - CC_OP_ADDB) & 3;</div>\r\n" - "<div> TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);</div>\r\n" - "<div> return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -897,7 +897,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)</div>\r\n" - "<div> static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> int inv, jcc_op, cond;</div>\r\n" - "<div>- TCGMemOp size;</div>\r\n" - "<div>+ MemOp size;</div>\r\n" - "<div> CCPrepare cc;</div>\r\n" - "<div> TCGv t0;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1075,7 +1075,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)</div>\r\n" - "<div> return l2;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_stos(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX);</div>\r\n" - "<div> gen_string_movl_A0_EDI(s);</div>\r\n" - "<div>@@ -1084,7 +1084,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> gen_op_add_reg_T0(s, s->aflag, R_EDI);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_lods(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_lods(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_string_movl_A0_ESI(s);</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T0, s->A0);</div>\r\n" - "<div>@@ -1093,7 +1093,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> gen_op_add_reg_T0(s, s->aflag, R_ESI);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_scas(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_scas(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_string_movl_A0_EDI(s);</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div>\r\n" - "<div>@@ -1102,7 +1102,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> gen_op_add_reg_T0(s, s->aflag, R_EDI);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_cmps(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_cmps(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_string_movl_A0_EDI(s);</div>\r\n" - "<div> gen_op_ld_v(s, ot, s->T1, s->A0);</div>\r\n" - "<div>@@ -1126,7 +1126,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_ins(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_ins(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {</div>\r\n" - "<div> gen_io_start();</div>\r\n" - "<div>@@ -1148,7 +1148,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_outs(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_outs(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {</div>\r\n" - "<div> gen_io_start();</div>\r\n" - "<div>@@ -1171,7 +1171,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> /* same method as Valgrind : we generate jumps to current or next</div>\r\n" - "<div> instruction */</div>\r\n" - "<div> #define GEN_REPZ(op) \\</div>\r\n" - "<div>-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \\</div>\r\n" - "<div>+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \\</div>\r\n" - "<div> target_ulong cur_eip, target_ulong next_eip) \\</div>\r\n" - "<div> { \\</div>\r\n" - "<div> TCGLabel *l2; \\</div>\r\n" - "<div>@@ -1187,7 +1187,7 @@ static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \\</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> #define GEN_REPZ2(op) \\</div>\r\n" - "<div>-static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, \\</div>\r\n" - "<div>+static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \\</div>\r\n" - "<div> target_ulong cur_eip, \\</div>\r\n" - "<div> target_ulong next_eip, \\</div>\r\n" - "<div> int nz) \\</div>\r\n" - "<div>@@ -1284,7 +1284,7 @@ static void gen_illegal_opcode(DisasContext *s)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* if d == OR_TMP0, it means memory operand (address in A0) */</div>\r\n" - "<div>-static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)</div>\r\n" - "<div>+static void gen_op(DisasContext *s1, int op, MemOp ot, int d)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (d != OR_TMP0) {</div>\r\n" - "<div> if (s1->prefix & PREFIX_LOCK) {</div>\r\n" - "<div>@@ -1395,7 +1395,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* if d == OR_TMP0, it means memory operand (address in A0) */</div>\r\n" - "<div>-static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)</div>\r\n" - "<div>+static void gen_inc(DisasContext *s1, MemOp ot, int d, int c)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (s1->prefix & PREFIX_LOCK) {</div>\r\n" - "<div> if (d != OR_TMP0) {</div>\r\n" - "<div>@@ -1421,7 +1421,7 @@ static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)</div>\r\n" - "<div> set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div>\r\n" - "<div>+static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,</div>\r\n" - "<div> TCGv shm1, TCGv count, bool is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 z32, s32, oldop;</div>\r\n" - "<div>@@ -1466,7 +1466,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result,</div>\r\n" - "<div> set_cc_op(s, CC_OP_DYNAMIC);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div>+static void gen_shift_rm_T1(DisasContext *s, MemOp ot, int op1,</div>\r\n" - "<div> int is_right, int is_arith)</div>\r\n" - "<div> {</div>\r\n" - "<div> target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>@@ -1502,7 +1502,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div>+static void gen_shift_rm_im(DisasContext *s, MemOp ot, int op1, int op2,</div>\r\n" - "<div> int is_right, int is_arith)</div>\r\n" - "<div> {</div>\r\n" - "<div> int mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>@@ -1542,7 +1542,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div>+static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div> target_ulong mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div> TCGv_i32 t0, t1;</div>\r\n" - "<div>@@ -1627,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_right)</div>\r\n" - "<div> set_cc_op(s, CC_OP_DYNAMIC);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div>+static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2,</div>\r\n" - "<div> int is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div> int mask = (ot == MO_64 ? 0x3f : 0x1f);</div>\r\n" - "<div>@@ -1705,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* XXX: add faster immediate = 1 case */</div>\r\n" - "<div>-static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div>+static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,</div>\r\n" - "<div> int is_right)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_compute_eflags(s);</div>\r\n" - "<div>@@ -1761,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* XXX: add faster immediate case */</div>\r\n" - "<div>-static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div>+static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,</div>\r\n" - "<div> bool is_right, TCGv count_in)</div>\r\n" - "<div> {</div>\r\n" - "<div> target_ulong mask = (ot == MO_64 ? 63 : 31);</div>\r\n" - "<div>@@ -1842,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,</div>\r\n" - "<div> tcg_temp_free(count);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)</div>\r\n" - "<div>+static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (s != OR_TMP1)</div>\r\n" - "<div> gen_op_mov_v_reg(s1, ot, s1->T1, s);</div>\r\n" - "<div>@@ -1872,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c)</div>\r\n" - "<div>+static void gen_shifti(DisasContext *s1, int op, MemOp ot, int d, int c)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch(op) {</div>\r\n" - "<div> case OP_ROL:</div>\r\n" - "<div>@@ -2149,7 +2149,7 @@ static void gen_add_A0_ds_seg(DisasContext *s)</div>\r\n" - "<div> /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==</div>\r\n" - "<div> OR_TMP0 */</div>\r\n" - "<div> static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,</div>\r\n" - "<div>- TCGMemOp ot, int reg, int is_store)</div>\r\n" - "<div>+ MemOp ot, int reg, int is_store)</div>\r\n" - "<div> {</div>\r\n" - "<div> int mod, rm;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2179,7 +2179,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> uint32_t ret;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2202,7 +2202,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div> return ret;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline int insn_const_size(TCGMemOp ot)</div>\r\n" - "<div>+static inline int insn_const_size(MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (ot <= MO_32) {</div>\r\n" - "<div> return 1 << ot;</div>\r\n" - "<div>@@ -2266,7 +2266,7 @@ static inline void gen_jcc(DisasContext *s, int b,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, int b,</div>\r\n" - "<div>+static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,</div>\r\n" - "<div> int modrm, int reg)</div>\r\n" - "<div> {</div>\r\n" - "<div> CCPrepare cc;</div>\r\n" - "<div>@@ -2363,8 +2363,8 @@ static inline void gen_stack_update(DisasContext *s, int addend)</div>\r\n" - "<div> /* Generate a push. It depends on ss32, addseg and dflag. */</div>\r\n" - "<div> static void gen_push_v(DisasContext *s, TCGv val)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = mo_stacksize(s);</div>\r\n" - "<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>+ MemOp a_ot = mo_stacksize(s);</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> TCGv new_esp = s->A0;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2383,9 +2383,9 @@ static void gen_push_v(DisasContext *s, TCGv val)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> /* two step pop is necessary for precise exceptions */</div>\r\n" - "<div>-static TCGMemOp gen_pop_T0(DisasContext *s)</div>\r\n" - "<div>+static MemOp gen_pop_T0(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div> </div>\r\n" - "<div> gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1);</div>\r\n" - "<div> gen_op_ld_v(s, d_ot, s->T0, s->A0);</div>\r\n" - "<div>@@ -2393,7 +2393,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s)</div>\r\n" - "<div> return d_ot;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void gen_pop_update(DisasContext *s, TCGMemOp ot)</div>\r\n" - "<div>+static inline void gen_pop_update(DisasContext *s, MemOp ot)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_stack_update(s, 1 << ot);</div>\r\n" - "<div> }</div>\r\n" - "<div>@@ -2405,8 +2405,8 @@ static inline void gen_stack_A0(DisasContext *s)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>- TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div>+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ MemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2421,8 +2421,8 @@ static void gen_pusha(DisasContext *s)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_popa(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>- TCGMemOp d_ot = s->dflag;</div>\r\n" - "<div>+ MemOp s_ot = s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ MemOp d_ot = s->dflag;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2442,8 +2442,8 @@ static void gen_popa(DisasContext *s)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_enter(DisasContext *s, int esp_addend, int level)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>+ MemOp a_ot = CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16;</div>\r\n" - "<div> int size = 1 << d_ot;</div>\r\n" - "<div> </div>\r\n" - "<div> /* Push BP; compute FrameTemp into T1. */</div>\r\n" - "<div>@@ -2482,8 +2482,8 @@ static void gen_enter(DisasContext *s, int esp_addend, int level)</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_leave(DisasContext *s)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>- TCGMemOp a_ot = mo_stacksize(s);</div>\r\n" - "<div>+ MemOp d_ot = mo_pushpop(s, s->dflag);</div>\r\n" - "<div>+ MemOp a_ot = mo_stacksize(s);</div>\r\n" - "<div> </div>\r\n" - "<div> gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1);</div>\r\n" - "<div> gen_op_ld_v(s, d_ot, s->T0, s->A0);</div>\r\n" - "<div>@@ -3045,7 +3045,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,</div>\r\n" - "<div> SSEFunc_0_eppi sse_fn_eppi;</div>\r\n" - "<div> SSEFunc_0_ppi sse_fn_ppi;</div>\r\n" - "<div> SSEFunc_0_eppt sse_fn_eppt;</div>\r\n" - "<div>- TCGMemOp ot;</div>\r\n" - "<div>+ MemOp ot;</div>\r\n" - "<div> </div>\r\n" - "<div> b &= 0xff;</div>\r\n" - "<div> if (s->prefix & PREFIX_DATA)</div>\r\n" - "<div>@@ -4488,7 +4488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> CPUX86State *env = cpu->env_ptr;</div>\r\n" - "<div> int b, prefixes;</div>\r\n" - "<div> int shift;</div>\r\n" - "<div>- TCGMemOp ot, aflag, dflag;</div>\r\n" - "<div>+ MemOp ot, aflag, dflag;</div>\r\n" - "<div> int modrm, reg, rm, mod, op, opreg, val;</div>\r\n" - "<div> target_ulong next_eip, tval;</div>\r\n" - "<div> int rex_w, rex_r;</div>\r\n" - "<div>@@ -5567,8 +5567,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)</div>\r\n" - "<div> case 0x1be: /* movsbS Gv, Eb */</div>\r\n" - "<div> case 0x1bf: /* movswS Gv, Eb */</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp d_ot;</div>\r\n" - "<div>- TCGMemOp s_ot;</div>\r\n" - "<div>+ MemOp d_ot;</div>\r\n" - "<div>+ MemOp s_ot;</div>\r\n" - "<div> </div>\r\n" - "<div> /* d_ot is the size of destination */</div>\r\n" - "<div> d_ot = dflag;</div>\r\n" - "<div>diff --git a/target/m68k/translate.c b/target/m68k/translate.c</div>\r\n" - "<div>index 60bcfb7..24c1dd3 100644</div>\r\n" - "<div>--- a/target/m68k/translate.c</div>\r\n" - "<div>+++ b/target/m68k/translate.c</div>\r\n" - "<div>@@ -2414,7 +2414,7 @@ DISAS_INSN(cas)</div>\r\n" - "<div> uint16_t ext;</div>\r\n" - "<div> TCGv load;</div>\r\n" - "<div> TCGv cmp;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> </div>\r\n" - "<div> switch ((insn >> 9) & 3) {</div>\r\n" - "<div> case 1:</div>\r\n" - "<div>diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c</div>\r\n" - "<div>index 9ce65f3..41d1b8b 100644</div>\r\n" - "<div>--- a/target/microblaze/translate.c</div>\r\n" - "<div>+++ b/target/microblaze/translate.c</div>\r\n" - "<div>@@ -919,7 +919,7 @@ static void dec_load(DisasContext *dc)</div>\r\n" - "<div> unsigned int size;</div>\r\n" - "<div> bool rev = false, ex = false, ea = false;</div>\r\n" - "<div> int mem_index = cpu_mmu_index(&dc->cpu->env, false);</div>\r\n" - "<div>- TCGMemOp mop;</div>\r\n" - "<div>+ MemOp mop;</div>\r\n" - "<div> </div>\r\n" - "<div> mop = dc->opcode & 3;</div>\r\n" - "<div> size = 1 << mop;</div>\r\n" - "<div>@@ -1035,7 +1035,7 @@ static void dec_store(DisasContext *dc)</div>\r\n" - "<div> unsigned int size;</div>\r\n" - "<div> bool rev = false, ex = false, ea = false;</div>\r\n" - "<div> int mem_index = cpu_mmu_index(&dc->cpu->env, false);</div>\r\n" - "<div>- TCGMemOp mop;</div>\r\n" - "<div>+ MemOp mop;</div>\r\n" - "<div> </div>\r\n" - "<div> mop = dc->opcode & 3;</div>\r\n" - "<div> size = 1 << mop;</div>\r\n" - "<div>diff --git a/target/mips/translate.c b/target/mips/translate.c</div>\r\n" - "<div>index ca62800..59b5d85 100644</div>\r\n" - "<div>--- a/target/mips/translate.c</div>\r\n" - "<div>+++ b/target/mips/translate.c</div>\r\n" - "<div>@@ -2526,7 +2526,7 @@ typedef struct DisasContext {</div>\r\n" - "<div> int32_t CP0_Config5;</div>\r\n" - "<div> /* Routine used to access memory */</div>\r\n" - "<div> int mem_idx;</div>\r\n" - "<div>- TCGMemOp default_tcg_memop_mask;</div>\r\n" - "<div>+ MemOp default_tcg_memop_mask;</div>\r\n" - "<div> uint32_t hflags, saved_hflags;</div>\r\n" - "<div> target_ulong btarget;</div>\r\n" - "<div> bool ulri;</div>\r\n" - "<div>@@ -3706,7 +3706,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,</div>\r\n" - "<div> </div>\r\n" - "<div> /* Store conditional */</div>\r\n" - "<div> static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,</div>\r\n" - "<div>- TCGMemOp tcg_mo, bool eva)</div>\r\n" - "<div>+ MemOp tcg_mo, bool eva)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv addr, t0, val;</div>\r\n" - "<div> TCGLabel *l1 = gen_new_label();</div>\r\n" - "<div>@@ -4546,7 +4546,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_r6_ld(target_long addr, int reg, int memidx,</div>\r\n" - "<div>- TCGMemOp memop)</div>\r\n" - "<div>+ MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv t0 = tcg_const_tl(addr);</div>\r\n" - "<div> tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);</div>\r\n" - "<div>@@ -21828,7 +21828,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)</div>\r\n" - "<div> extract32(ctx->opcode, 0, 8);</div>\r\n" - "<div> TCGv va = tcg_temp_new();</div>\r\n" - "<div> TCGv t1 = tcg_temp_new();</div>\r\n" - "<div>- TCGMemOp memop = (extract32(ctx->opcode, 8, 3)) ==</div>\r\n" - "<div>+ MemOp memop = (extract32(ctx->opcode, 8, 3)) ==</div>\r\n" - "<div> NM_P_LS_UAWM ? MO_UNALN : 0;</div>\r\n" - "<div> </div>\r\n" - "<div> count = (count == 0) ? 8 : count;</div>\r\n" - "<div>diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c</div>\r\n" - "<div>index 4360ce4..b189c50 100644</div>\r\n" - "<div>--- a/target/openrisc/translate.c</div>\r\n" - "<div>+++ b/target/openrisc/translate.c</div>\r\n" - "<div>@@ -681,7 +681,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)</div>\r\n" - "<div> return true;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)</div>\r\n" - "<div>+static void do_load(DisasContext *dc, arg_load *a, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv ea;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -763,7 +763,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)</div>\r\n" - "<div> return true;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)</div>\r\n" - "<div>+static void do_store(DisasContext *dc, arg_store *a, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv t0 = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_addi_tl(t0, cpu_R[a->a], a->i);</div>\r\n" - "<div>diff --git a/target/ppc/translate.c b/target/ppc/translate.c</div>\r\n" - "<div>index 4a5de28..31800ed 100644</div>\r\n" - "<div>--- a/target/ppc/translate.c</div>\r\n" - "<div>+++ b/target/ppc/translate.c</div>\r\n" - "<div>@@ -162,7 +162,7 @@ struct DisasContext {</div>\r\n" - "<div> int mem_idx;</div>\r\n" - "<div> int access_type;</div>\r\n" - "<div> /* Translation flags */</div>\r\n" - "<div>- TCGMemOp default_tcg_memop_mask;</div>\r\n" - "<div>+ MemOp default_tcg_memop_mask;</div>\r\n" - "<div> #if defined(TARGET_PPC64)</div>\r\n" - "<div> bool sf_mode;</div>\r\n" - "<div> bool has_cfar;</div>\r\n" - "<div>@@ -3142,7 +3142,7 @@ static void gen_isync(DisasContext *ctx)</div>\r\n" - "<div> </div>\r\n" - "<div> #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)</div>\r\n" - "<div>+static void gen_load_locked(DisasContext *ctx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv gpr = cpu_gpr[rD(ctx->opcode)];</div>\r\n" - "<div> TCGv t0 = tcg_temp_new();</div>\r\n" - "<div>@@ -3167,7 +3167,7 @@ LARX(lbarx, DEF_MEMOP(MO_UB))</div>\r\n" - "<div> LARX(lharx, DEF_MEMOP(MO_UW))</div>\r\n" - "<div> LARX(lwarx, DEF_MEMOP(MO_UL))</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,</div>\r\n" - "<div>+static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,</div>\r\n" - "<div> TCGv EA, TCGCond cond, int addend)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv t = tcg_temp_new();</div>\r\n" - "<div>@@ -3193,7 +3193,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,</div>\r\n" - "<div> tcg_temp_free(u);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)</div>\r\n" - "<div>+static void gen_ld_atomic(DisasContext *ctx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> uint32_t gpr_FC = FC(ctx->opcode);</div>\r\n" - "<div> TCGv EA = tcg_temp_new();</div>\r\n" - "<div>@@ -3306,7 +3306,7 @@ static void gen_ldat(DisasContext *ctx)</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)</div>\r\n" - "<div>+static void gen_st_atomic(DisasContext *ctx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> uint32_t gpr_FC = FC(ctx->opcode);</div>\r\n" - "<div> TCGv EA = tcg_temp_new();</div>\r\n" - "<div>@@ -3389,7 +3389,7 @@ static void gen_stdat(DisasContext *ctx)</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>-static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)</div>\r\n" - "<div>+static void gen_conditional_store(DisasContext *ctx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGLabel *l1 = gen_new_label();</div>\r\n" - "<div> TCGLabel *l2 = gen_new_label();</div>\r\n" - "<div>diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c</div>\r\n" - "<div>index fadd888..be8a9f0 100644</div>\r\n" - "<div>--- a/target/riscv/insn_trans/trans_rva.inc.c</div>\r\n" - "<div>+++ b/target/riscv/insn_trans/trans_rva.inc.c</div>\r\n" - "<div>@@ -18,7 +18,7 @@</div>\r\n" - "<div> * this program. If not, see <http://www.gnu.org/licenses/>.</div>\r\n" - "<div> */</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div>\r\n" - "<div>+static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv src1 = tcg_temp_new();</div>\r\n" - "<div> /* Put addr in load_res, data in load_val. */</div>\r\n" - "<div>@@ -37,7 +37,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div>\r\n" - "<div> return true;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div>\r\n" - "<div>+static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv src1 = tcg_temp_new();</div>\r\n" - "<div> TCGv src2 = tcg_temp_new();</div>\r\n" - "<div>@@ -82,8 +82,8 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static bool gen_amo(DisasContext *ctx, arg_atomic *a,</div>\r\n" - "<div>- void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp),</div>\r\n" - "<div>- TCGMemOp mop)</div>\r\n" - "<div>+ void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),</div>\r\n" - "<div>+ MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv src1 = tcg_temp_new();</div>\r\n" - "<div> TCGv src2 = tcg_temp_new();</div>\r\n" - "<div>diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c</div>\r\n" - "<div>index ea64731..cf440d1 100644</div>\r\n" - "<div>--- a/target/riscv/insn_trans/trans_rvi.inc.c</div>\r\n" - "<div>+++ b/target/riscv/insn_trans/trans_rvi.inc.c</div>\r\n" - "<div>@@ -135,7 +135,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)</div>\r\n" - "<div> return gen_branch(ctx, a, TCG_COND_GEU);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop)</div>\r\n" - "<div>+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv t0 = tcg_temp_new();</div>\r\n" - "<div> TCGv t1 = tcg_temp_new();</div>\r\n" - "<div>@@ -174,7 +174,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)</div>\r\n" - "<div> return gen_load(ctx, a, MO_TEUW);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)</div>\r\n" - "<div>+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv t0 = tcg_temp_new();</div>\r\n" - "<div> TCGv dat = tcg_temp_new();</div>\r\n" - "<div>diff --git a/target/s390x/translate.c b/target/s390x/translate.c</div>\r\n" - "<div>index ac0d8b6..2927247 100644</div>\r\n" - "<div>--- a/target/s390x/translate.c</div>\r\n" - "<div>+++ b/target/s390x/translate.c</div>\r\n" - "<div>@@ -152,7 +152,7 @@ static inline int vec_full_reg_offset(uint8_t reg)</div>\r\n" - "<div> return offsetof(CPUS390XState, vregs[reg][0]);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es)</div>\r\n" - "<div>+static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* Convert element size (es) - e.g. MO_8 - to bytes */</div>\r\n" - "<div> const uint8_t bytes = 1 << es;</div>\r\n" - "<div>@@ -2262,7 +2262,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOps *o)</div>\r\n" - "<div> #ifndef CONFIG_USER_ONLY</div>\r\n" - "<div> static DisasJumpType op_csp(DisasContext *s, DisasOps *o)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp mop = s->insn->data;</div>\r\n" - "<div>+ MemOp mop = s->insn->data;</div>\r\n" - "<div> TCGv_i64 addr, old, cc;</div>\r\n" - "<div> TCGLabel *lab = gen_new_label();</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3228,7 +3228,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)</div>\r\n" - "<div> static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 a1, a2;</div>\r\n" - "<div>- TCGMemOp mop = s->insn->data;</div>\r\n" - "<div>+ MemOp mop = s->insn->data;</div>\r\n" - "<div> </div>\r\n" - "<div> /* In a parallel context, stop the world and single step. */</div>\r\n" - "<div> if (tb_cflags(s->base.tb) & CF_PARALLEL) {</div>\r\n" - "<div>diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>index 41d5cf8..4c56bbb 100644</div>\r\n" - "<div>--- a/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>+++ b/target/s390x/translate_vx.inc.c</div>\r\n" - "<div>@@ -57,13 +57,13 @@</div>\r\n" - "<div> #define FPF_LONG 3</div>\r\n" - "<div> #define FPF_EXT 4</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)</div>\r\n" - "<div>+static inline bool valid_vec_element(uint8_t enr, MemOp es)</div>\r\n" - "<div> {</div>\r\n" - "<div> return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,</div>\r\n" - "<div>- TCGMemOp memop)</div>\r\n" - "<div>+ MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -96,7 +96,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,</div>\r\n" - "<div>- TCGMemOp memop)</div>\r\n" - "<div>+ MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -123,7 +123,7 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,</div>\r\n" - "<div>- TCGMemOp memop)</div>\r\n" - "<div>+ MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -146,7 +146,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,</div>\r\n" - "<div>- TCGMemOp memop)</div>\r\n" - "<div>+ MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/sparc/translate.c b/target/sparc/translate.c</div>\r\n" - "<div>index 091bab5..bef9ce6 100644</div>\r\n" - "<div>--- a/target/sparc/translate.c</div>\r\n" - "<div>+++ b/target/sparc/translate.c</div>\r\n" - "<div>@@ -2019,7 +2019,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,</div>\r\n" - "<div>- TCGv addr, int mmu_idx, TCGMemOp memop)</div>\r\n" - "<div>+ TCGv addr, int mmu_idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_address_mask(dc, addr);</div>\r\n" - "<div> tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);</div>\r\n" - "<div>@@ -2050,10 +2050,10 @@ typedef struct {</div>\r\n" - "<div> ASIType type;</div>\r\n" - "<div> int asi;</div>\r\n" - "<div> int mem_idx;</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> } DisasASI;</div>\r\n" - "<div> </div>\r\n" - "<div>-static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)</div>\r\n" - "<div>+static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> int asi = GET_FIELD(insn, 19, 26);</div>\r\n" - "<div> ASIType type = GET_ASI_HELPER;</div>\r\n" - "<div>@@ -2267,7 +2267,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,</div>\r\n" - "<div>- int insn, TCGMemOp memop)</div>\r\n" - "<div>+ int insn, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> DisasASI da = get_asi(dc, insn, memop);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2305,7 +2305,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,</div>\r\n" - "<div>- int insn, TCGMemOp memop)</div>\r\n" - "<div>+ int insn, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> DisasASI da = get_asi(dc, insn, memop);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2511,7 +2511,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,</div>\r\n" - "<div> case GET_ASI_BLOCK:</div>\r\n" - "<div> /* Valid for lddfa on aligned registers only. */</div>\r\n" - "<div> if (size == 8 && (rd & 7) == 0) {</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> TCGv eight;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2625,7 +2625,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,</div>\r\n" - "<div> case GET_ASI_BLOCK:</div>\r\n" - "<div> /* Valid for stdfa on aligned registers only. */</div>\r\n" - "<div> if (size == 8 && (rd & 7) == 0) {</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> TCGv eight;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div>diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c</div>\r\n" - "<div>index c46a4ab..68dd4aa 100644</div>\r\n" - "<div>--- a/target/tilegx/translate.c</div>\r\n" - "<div>+++ b/target/tilegx/translate.c</div>\r\n" - "<div>@@ -290,7 +290,7 @@ static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,</div>\r\n" - "<div>- unsigned srcb, TCGMemOp memop, const char *name)</div>\r\n" - "<div>+ unsigned srcb, MemOp memop, const char *name)</div>\r\n" - "<div> {</div>\r\n" - "<div> if (dest) {</div>\r\n" - "<div> return TILEGX_EXCP_OPCODE_UNKNOWN;</div>\r\n" - "<div>@@ -305,7 +305,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,</div>\r\n" - "<div>- int imm, TCGMemOp memop, const char *name)</div>\r\n" - "<div>+ int imm, MemOp memop, const char *name)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv tsrca = load_gr(dc, srca);</div>\r\n" - "<div> TCGv tsrcb = load_gr(dc, srcb);</div>\r\n" - "<div>@@ -496,7 +496,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv tdest, tsrca;</div>\r\n" - "<div> const char *mnemonic;</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> TileExcp ret = TILEGX_EXCP_NONE;</div>\r\n" - "<div> bool prefetch_nofault = false;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1478,7 +1478,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,</div>\r\n" - "<div> TCGv tsrca = load_gr(dc, srca);</div>\r\n" - "<div> bool prefetch_nofault = false;</div>\r\n" - "<div> const char *mnemonic;</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> int i2, i3;</div>\r\n" - "<div> TCGv t0;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2106,7 +2106,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)</div>\r\n" - "<div> unsigned srca = get_SrcA_Y2(bundle);</div>\r\n" - "<div> unsigned srcbdest = get_SrcBDest_Y2(bundle);</div>\r\n" - "<div> const char *mnemonic;</div>\r\n" - "<div>- TCGMemOp memop;</div>\r\n" - "<div>+ MemOp memop;</div>\r\n" - "<div> bool prefetch_nofault = false;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (OEY2(opc, mode)) {</div>\r\n" - "<div>diff --git a/target/tricore/translate.c b/target/tricore/translate.c</div>\r\n" - "<div>index dc2a65f..87a5f50 100644</div>\r\n" - "<div>--- a/target/tricore/translate.c</div>\r\n" - "<div>+++ b/target/tricore/translate.c</div>\r\n" - "<div>@@ -227,7 +227,7 @@ static inline void generate_trap(DisasContext *ctx, int class, int tin);</div>\r\n" - "<div> /* Functions for load/save to/from memory */</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,</div>\r\n" - "<div>- int16_t con, TCGMemOp mop)</div>\r\n" - "<div>+ int16_t con, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv temp = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_addi_tl(temp, r2, con);</div>\r\n" - "<div>@@ -236,7 +236,7 @@ static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,</div>\r\n" - "<div>- int16_t con, TCGMemOp mop)</div>\r\n" - "<div>+ int16_t con, MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv temp = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_addi_tl(temp, r2, con);</div>\r\n" - "<div>@@ -284,7 +284,7 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div>\r\n" - "<div>- TCGMemOp mop)</div>\r\n" - "<div>+ MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv temp = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_addi_tl(temp, r2, off);</div>\r\n" - "<div>@@ -294,7 +294,7 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,</div>\r\n" - "<div>- TCGMemOp mop)</div>\r\n" - "<div>+ MemOp mop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv temp = tcg_temp_new();</div>\r\n" - "<div> tcg_gen_addi_tl(temp, r2, off);</div>\r\n" - "<div>diff --git a/tcg/README b/tcg/README</div>\r\n" - "<div>index 21fcdf7..b4382fa 100644</div>\r\n" - "<div>--- a/tcg/README</div>\r\n" - "<div>+++ b/tcg/README</div>\r\n" - "<div>@@ -512,7 +512,7 @@ Both t0 and t1 may be split into little-endian ordered pairs of registers</div>\r\n" - "<div> if dealing with 64-bit quantities on a 32-bit host.</div>\r\n" - "<div> </div>\r\n" - "<div> The memidx selects the qemu tlb index to use (e.g. user or kernel access).</div>\r\n" - "<div>-The flags are the TCGMemOp bits, selecting the sign, width, and endianness</div>\r\n" - "<div>+The flags are the MemOp bits, selecting the sign, width, and endianness</div>\r\n" - "<div> of the memory access.</div>\r\n" - "<div> </div>\r\n" - "<div> For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a</div>\r\n" - "<div>diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>index 0713448..3f92101 100644</div>\r\n" - "<div>--- a/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/aarch64/tcg-target.inc.c</div>\r\n" - "<div>@@ -1423,7 +1423,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)</div>\r\n" - "<div> tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,</div>\r\n" - "<div>+static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,</div>\r\n" - "<div> TCGReg rd, TCGReg rn)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */</div>\r\n" - "<div>@@ -1431,7 +1431,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,</div>\r\n" - "<div> tcg_out_sbfm(s, ext, rd, rn, 0, bits);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_uxt(TCGContext *s, TCGMemOp s_bits,</div>\r\n" - "<div>+static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,</div>\r\n" - "<div> TCGReg rd, TCGReg rn)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */</div>\r\n" - "<div>@@ -1580,8 +1580,8 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)</div>\r\n" - "<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp size = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp size = opc & MO_SIZE;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div>@@ -1605,8 +1605,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp size = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp size = opc & MO_SIZE;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div>@@ -1649,7 +1649,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);</div>\r\n" - "<div> slow path for the failure case, which will be patched later when finalizing</div>\r\n" - "<div> the slow path. Generated code returns the host addend in X1,</div>\r\n" - "<div> clobbers X0,X2,X3,TMP. */</div>\r\n" - "<div>-static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,</div>\r\n" - "<div>+static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,</div>\r\n" - "<div> tcg_insn_unit **label_ptr, int mem_index,</div>\r\n" - "<div> bool is_read)</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -1709,11 +1709,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,</div>\r\n" - "<div> </div>\r\n" - "<div> #endif /* CONFIG_SOFTMMU */</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div>\r\n" - "<div>+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,</div>\r\n" - "<div> TCGReg data_r, TCGReg addr_r,</div>\r\n" - "<div> TCGType otype, TCGReg off_r)</div>\r\n" - "<div> {</div>\r\n" - "<div>- const TCGMemOp bswap = memop & MO_BSWAP;</div>\r\n" - "<div>+ const MemOp bswap = memop & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (memop & MO_SSIZE) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>@@ -1765,11 +1765,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div>+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,</div>\r\n" - "<div> TCGReg data_r, TCGReg addr_r,</div>\r\n" - "<div> TCGType otype, TCGReg off_r)</div>\r\n" - "<div> {</div>\r\n" - "<div>- const TCGMemOp bswap = memop & MO_BSWAP;</div>\r\n" - "<div>+ const MemOp bswap = memop & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (memop & MO_SIZE) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop,</div>\r\n" - "<div> static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> TCGMemOpIdx oi, TCGType ext)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp memop = get_memop(oi);</div>\r\n" - "<div>+ MemOp memop = get_memop(oi);</div>\r\n" - "<div> const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned mem_index = get_mmuidx(oi);</div>\r\n" - "<div>@@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> TCGMemOpIdx oi)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp memop = get_memop(oi);</div>\r\n" - "<div>+ MemOp memop = get_memop(oi);</div>\r\n" - "<div> const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned mem_index = get_mmuidx(oi);</div>\r\n" - "<div>diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>index ece88dc..94d80d7 100644</div>\r\n" - "<div>--- a/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/arm/tcg-target.inc.c</div>\r\n" - "<div>@@ -1233,7 +1233,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);</div>\r\n" - "<div> containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */</div>\r\n" - "<div> </div>\r\n" - "<div> static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,</div>\r\n" - "<div>- TCGMemOp opc, int mem_index, bool is_load)</div>\r\n" - "<div>+ MemOp opc, int mem_index, bool is_load)</div>\r\n" - "<div> {</div>\r\n" - "<div> int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)</div>\r\n" - "<div> : offsetof(CPUTLBEntry, addr_write));</div>\r\n" - "<div>@@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg argreg, datalo, datahi;</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> void *func;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div>@@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg argreg, datalo, datahi;</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div> return false;</div>\r\n" - "<div>@@ -1453,11 +1453,11 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> }</div>\r\n" - "<div> #endif /* SOFTMMU */</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div>+static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,</div>\r\n" - "<div> TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg addrlo, TCGReg addend)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SSIZE) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>@@ -1514,11 +1514,11 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div>+static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,</div>\r\n" - "<div> TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg addrlo)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SSIZE) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>@@ -1577,7 +1577,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> TCGReg addend;</div>\r\n" - "<div>@@ -1614,11 +1614,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div>+static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,</div>\r\n" - "<div> TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg addrlo, TCGReg addend)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SIZE) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -1659,11 +1659,11 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp opc,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div>+static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,</div>\r\n" - "<div> TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg addrlo)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> switch (opc & MO_SIZE) {</div>\r\n" - "<div> case MO_8:</div>\r\n" - "<div>@@ -1708,7 +1708,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> TCGReg addend;</div>\r\n" - "<div>diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>index 6ddeebf..9d8ed97 100644</div>\r\n" - "<div>--- a/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/i386/tcg-target.inc.c</div>\r\n" - "<div>@@ -1697,7 +1697,7 @@ static void * const qemu_st_helpers[16] = {</div>\r\n" - "<div> First argument register is clobbered. */</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,</div>\r\n" - "<div>- int mem_index, TCGMemOp opc,</div>\r\n" - "<div>+ int mem_index, MemOp opc,</div>\r\n" - "<div> tcg_insn_unit **label_ptr, int which)</div>\r\n" - "<div> {</div>\r\n" - "<div> const TCGReg r0 = TCG_REG_L0;</div>\r\n" - "<div>@@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,</div>\r\n" - "<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> TCGReg data_reg;</div>\r\n" - "<div> tcg_insn_unit **label_ptr = &l->label_ptr[0];</div>\r\n" - "<div> int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0);</div>\r\n" - "<div>@@ -1895,8 +1895,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div> tcg_insn_unit **label_ptr = &l->label_ptr[0];</div>\r\n" - "<div> TCGReg retaddr;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1995,10 +1995,10 @@ static inline int setup_guest_base_seg(void)</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg base, int index, intptr_t ofs,</div>\r\n" - "<div>- int seg, bool is64, TCGMemOp memop)</div>\r\n" - "<div>+ int seg, bool is64, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div>- const TCGMemOp real_bswap = memop & MO_BSWAP;</div>\r\n" - "<div>- TCGMemOp bswap = real_bswap;</div>\r\n" - "<div>+ const MemOp real_bswap = memop & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = real_bswap;</div>\r\n" - "<div> int rexw = is64 * P_REXW;</div>\r\n" - "<div> int movop = OPC_MOVL_GvEv;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2103,7 +2103,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> TCGReg datalo, datahi, addrlo;</div>\r\n" - "<div> TCGReg addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> tcg_insn_unit *label_ptr[2];</div>\r\n" - "<div>@@ -2137,15 +2137,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,</div>\r\n" - "<div> TCGReg base, int index, intptr_t ofs,</div>\r\n" - "<div>- int seg, TCGMemOp memop)</div>\r\n" - "<div>+ int seg, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* ??? Ideally we wouldn't need a scratch register. For user-only,</div>\r\n" - "<div> we could perform the bswap twice to restore the original value</div>\r\n" - "<div> instead of moving to the scratch. But as it is, the L constraint</div>\r\n" - "<div> means that TCG_REG_L0 is definitely free here. */</div>\r\n" - "<div> const TCGReg scratch = TCG_REG_L0;</div>\r\n" - "<div>- const TCGMemOp real_bswap = memop & MO_BSWAP;</div>\r\n" - "<div>- TCGMemOp bswap = real_bswap;</div>\r\n" - "<div>+ const MemOp real_bswap = memop & MO_BSWAP;</div>\r\n" - "<div>+ MemOp bswap = real_bswap;</div>\r\n" - "<div> int movop = OPC_MOVL_EvGv;</div>\r\n" - "<div> </div>\r\n" - "<div> if (have_movbe && real_bswap) {</div>\r\n" - "<div>@@ -2221,7 +2221,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)</div>\r\n" - "<div> TCGReg datalo, datahi, addrlo;</div>\r\n" - "<div> TCGReg addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> tcg_insn_unit *label_ptr[2];</div>\r\n" - "<div>diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>index 41bff32..5442167 100644</div>\r\n" - "<div>--- a/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/mips/tcg-target.inc.c</div>\r\n" - "<div>@@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,</div>\r\n" - "<div> TCGReg addrh, TCGMemOpIdx oi,</div>\r\n" - "<div> tcg_insn_unit *label_ptr[2], bool is_load)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> unsigned s_bits = opc & MO_SIZE;</div>\r\n" - "<div> unsigned a_bits = get_alignment_bits(opc);</div>\r\n" - "<div> int mem_index = get_mmuidx(oi);</div>\r\n" - "<div>@@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,</div>\r\n" - "<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> TCGReg v0;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1363,8 +1363,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div> int i;</div>\r\n" - "<div> </div>\r\n" - "<div> /* resolve label address */</div>\r\n" - "<div>@@ -1413,7 +1413,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div>- TCGReg base, TCGMemOp opc, bool is_64)</div>\r\n" - "<div>+ TCGReg base, MemOp opc, bool is_64)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (opc & (MO_SSIZE | MO_BSWAP)) {</div>\r\n" - "<div> case MO_UB:</div>\r\n" - "<div>@@ -1521,7 +1521,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div>\r\n" - "<div> TCGReg data_regl, data_regh;</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> tcg_insn_unit *label_ptr[2];</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -1558,7 +1558,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div>- TCGReg base, TCGMemOp opc)</div>\r\n" - "<div>+ TCGReg base, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* Don't clutter the code below with checks to avoid bswapping ZERO. */</div>\r\n" - "<div> if ((lo | hi) == 0) {</div>\r\n" - "<div>@@ -1624,7 +1624,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div>\r\n" - "<div> TCGReg data_regl, data_regh;</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> tcg_insn_unit *label_ptr[2];</div>\r\n" - "<div> #endif</div>\r\n" - "<div>diff --git a/tcg/optimize.c b/tcg/optimize.c</div>\r\n" - "<div>index d2424de..a89ffda 100644</div>\r\n" - "<div>--- a/tcg/optimize.c</div>\r\n" - "<div>+++ b/tcg/optimize.c</div>\r\n" - "<div>@@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s)</div>\r\n" - "<div> CASE_OP_32_64(qemu_ld):</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];</div>\r\n" - "<div>- TCGMemOp mop = get_memop(oi);</div>\r\n" - "<div>+ MemOp mop = get_memop(oi);</div>\r\n" - "<div> if (!(mop & MO_SIGN)) {</div>\r\n" - "<div> mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>index 852b894..815edac 100644</div>\r\n" - "<div>--- a/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/ppc/tcg-target.inc.c</div>\r\n" - "<div>@@ -1506,7 +1506,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);</div>\r\n" - "<div> in CR7, loads the addend of the TLB into R3, and returns the register</div>\r\n" - "<div> containing the guest address (zero-extended into R4). Clobbers R0 and R2. */</div>\r\n" - "<div> </div>\r\n" - "<div>-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,</div>\r\n" - "<div>+static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,</div>\r\n" - "<div> TCGReg addrlo, TCGReg addrhi,</div>\r\n" - "<div> int mem_index, bool is_read)</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,</div>\r\n" - "<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> TCGReg hi, lo, arg = TCG_REG_R3;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div>@@ -1680,8 +1680,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div> TCGReg hi, lo, arg = TCG_REG_R3;</div>\r\n" - "<div> </div>\r\n" - "<div> if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {</div>\r\n" - "<div>@@ -1744,7 +1744,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg datalo, datahi, addrlo, rbase;</div>\r\n" - "<div> TCGReg addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc, s_bits;</div>\r\n" - "<div>+ MemOp opc, s_bits;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> tcg_insn_unit *label_ptr;</div>\r\n" - "<div>@@ -1819,7 +1819,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg datalo, datahi, addrlo, rbase;</div>\r\n" - "<div> TCGReg addrhi __attribute__((unused));</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc, s_bits;</div>\r\n" - "<div>+ MemOp opc, s_bits;</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> int mem_index;</div>\r\n" - "<div> tcg_insn_unit *label_ptr;</div>\r\n" - "<div>diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>index 3e76bf5..7018509 100644</div>\r\n" - "<div>--- a/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/riscv/tcg-target.inc.c</div>\r\n" - "<div>@@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,</div>\r\n" - "<div> TCGReg addrh, TCGMemOpIdx oi,</div>\r\n" - "<div> tcg_insn_unit **label_ptr, bool is_load)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> unsigned s_bits = opc & MO_SIZE;</div>\r\n" - "<div> unsigned a_bits = get_alignment_bits(opc);</div>\r\n" - "<div> tcg_target_long compare_mask;</div>\r\n" - "<div>@@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,</div>\r\n" - "<div> static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> TCGReg a0 = tcg_target_call_iarg_regs[0];</div>\r\n" - "<div> TCGReg a1 = tcg_target_call_iarg_regs[1];</div>\r\n" - "<div> TCGReg a2 = tcg_target_call_iarg_regs[2];</div>\r\n" - "<div>@@ -1077,8 +1077,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = l->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>- TCGMemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp s_bits = opc & MO_SIZE;</div>\r\n" - "<div> TCGReg a0 = tcg_target_call_iarg_regs[0];</div>\r\n" - "<div> TCGReg a1 = tcg_target_call_iarg_regs[1];</div>\r\n" - "<div> TCGReg a2 = tcg_target_call_iarg_regs[2];</div>\r\n" - "<div>@@ -1121,9 +1121,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)</div>\r\n" - "<div> #endif /* CONFIG_SOFTMMU */</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div>- TCGReg base, TCGMemOp opc, bool is_64)</div>\r\n" - "<div>+ TCGReg base, MemOp opc, bool is_64)</div>\r\n" - "<div> {</div>\r\n" - "<div>- const TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ const MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> /* We don't yet handle byteswapping, assert */</div>\r\n" - "<div> g_assert(!bswap);</div>\r\n" - "<div>@@ -1172,7 +1172,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div>\r\n" - "<div> TCGReg data_regl, data_regh;</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> tcg_insn_unit *label_ptr[1];</div>\r\n" - "<div> #endif</div>\r\n" - "<div>@@ -1208,9 +1208,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,</div>\r\n" - "<div>- TCGReg base, TCGMemOp opc)</div>\r\n" - "<div>+ TCGReg base, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div>- const TCGMemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div>+ const MemOp bswap = opc & MO_BSWAP;</div>\r\n" - "<div> </div>\r\n" - "<div> /* We don't yet handle byteswapping, assert */</div>\r\n" - "<div> g_assert(!bswap);</div>\r\n" - "<div>@@ -1243,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)</div>\r\n" - "<div> TCGReg addr_regl, addr_regh __attribute__((unused));</div>\r\n" - "<div> TCGReg data_regl, data_regh;</div>\r\n" - "<div> TCGMemOpIdx oi;</div>\r\n" - "<div>- TCGMemOp opc;</div>\r\n" - "<div>+ MemOp opc;</div>\r\n" - "<div> #if defined(CONFIG_SOFTMMU)</div>\r\n" - "<div> tcg_insn_unit *label_ptr[1];</div>\r\n" - "<div> #endif</div>\r\n" - "<div>diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>index fe42939..8aaa4ce 100644</div>\r\n" - "<div>--- a/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/s390/tcg-target.inc.c</div>\r\n" - "<div>@@ -1430,7 +1430,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div>\r\n" - "<div>+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,</div>\r\n" - "<div> TCGReg base, TCGReg index, int disp)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (opc & (MO_SSIZE | MO_BSWAP)) {</div>\r\n" - "<div>@@ -1489,7 +1489,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,</div>\r\n" - "<div>+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,</div>\r\n" - "<div> TCGReg base, TCGReg index, int disp)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (opc & (MO_SIZE | MO_BSWAP)) {</div>\r\n" - "<div>@@ -1544,7 +1544,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));</div>\r\n" - "<div> </div>\r\n" - "<div> /* Load and compare a TLB entry, leaving the flags set. Loads the TLB</div>\r\n" - "<div> addend into R2. Returns a register with the santitized guest address. */</div>\r\n" - "<div>-static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,</div>\r\n" - "<div>+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,</div>\r\n" - "<div> int mem_index, bool is_ld)</div>\r\n" - "<div> {</div>\r\n" - "<div> unsigned s_bits = opc & MO_SIZE;</div>\r\n" - "<div>@@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> TCGReg addr_reg = lb->addrlo_reg;</div>\r\n" - "<div> TCGReg data_reg = lb->datalo_reg;</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> </div>\r\n" - "<div> if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,</div>\r\n" - "<div> (intptr_t)s->code_ptr, 2)) {</div>\r\n" - "<div>@@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)</div>\r\n" - "<div> TCGReg addr_reg = lb->addrlo_reg;</div>\r\n" - "<div> TCGReg data_reg = lb->datalo_reg;</div>\r\n" - "<div> TCGMemOpIdx oi = lb->oi;</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> </div>\r\n" - "<div> if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,</div>\r\n" - "<div> (intptr_t)s->code_ptr, 2)) {</div>\r\n" - "<div>@@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,</div>\r\n" - "<div> static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> TCGMemOpIdx oi)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned mem_index = get_mmuidx(oi);</div>\r\n" - "<div> tcg_insn_unit *label_ptr;</div>\r\n" - "<div>@@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,</div>\r\n" - "<div> TCGMemOpIdx oi)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp opc = get_memop(oi);</div>\r\n" - "<div>+ MemOp opc = get_memop(oi);</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned mem_index = get_mmuidx(oi);</div>\r\n" - "<div> tcg_insn_unit *label_ptr;</div>\r\n" - "<div>diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>index 10b1cea..d7986cd 100644</div>\r\n" - "<div>--- a/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>+++ b/tcg/sparc/tcg-target.inc.c</div>\r\n" - "<div>@@ -1081,7 +1081,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));</div>\r\n" - "<div> is in the returned register, maybe %o0. The TLB addend is in %o1. */</div>\r\n" - "<div> </div>\r\n" - "<div> static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,</div>\r\n" - "<div>- TCGMemOp opc, int which)</div>\r\n" - "<div>+ MemOp opc, int which)</div>\r\n" - "<div> {</div>\r\n" - "<div> int fast_off = TLB_MASK_TABLE_OFS(mem_index);</div>\r\n" - "<div> int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);</div>\r\n" - "<div>@@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] = {</div>\r\n" - "<div> static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div>\r\n" - "<div> TCGMemOpIdx oi, bool is_64)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp memop = get_memop(oi);</div>\r\n" - "<div>+ MemOp memop = get_memop(oi);</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned memi = get_mmuidx(oi);</div>\r\n" - "<div> TCGReg addrz, param;</div>\r\n" - "<div>@@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,</div>\r\n" - "<div> static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,</div>\r\n" - "<div> TCGMemOpIdx oi)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp memop = get_memop(oi);</div>\r\n" - "<div>+ MemOp memop = get_memop(oi);</div>\r\n" - "<div> #ifdef CONFIG_SOFTMMU</div>\r\n" - "<div> unsigned memi = get_mmuidx(oi);</div>\r\n" - "<div> TCGReg addrz, param;</div>\r\n" - "<div>diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c</div>\r\n" - "<div>index 587d092..e87c327 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.c</div>\r\n" - "<div>+++ b/tcg/tcg-op.c</div>\r\n" - "<div>@@ -2714,7 +2714,7 @@ void tcg_gen_lookup_and_goto_ptr(void)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div>+static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)</div>\r\n" - "<div> {</div>\r\n" - "<div> /* Trigger the asserts within as early as possible. */</div>\r\n" - "<div> (void)get_alignment_bits(op);</div>\r\n" - "<div>@@ -2743,7 +2743,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,</div>\r\n" - "<div>- TCGMemOp memop, TCGArg idx)</div>\r\n" - "<div>+ MemOp memop, TCGArg idx)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = make_memop_idx(memop, idx);</div>\r\n" - "<div> #if TARGET_LONG_BITS == 32</div>\r\n" - "<div>@@ -2758,7 +2758,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,</div>\r\n" - "<div>- TCGMemOp memop, TCGArg idx)</div>\r\n" - "<div>+ MemOp memop, TCGArg idx)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = make_memop_idx(memop, idx);</div>\r\n" - "<div> #if TARGET_LONG_BITS == 32</div>\r\n" - "<div>@@ -2788,9 +2788,9 @@ static void tcg_gen_req_mo(TCGBar type)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp orig_memop;</div>\r\n" - "<div>+ MemOp orig_memop;</div>\r\n" - "<div> </div>\r\n" - "<div> tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);</div>\r\n" - "<div> memop = tcg_canonicalize_memop(memop, 0, 0);</div>\r\n" - "<div>@@ -2825,7 +2825,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 swap = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2858,9 +2858,9 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div>- TCGMemOp orig_memop;</div>\r\n" - "<div>+ MemOp orig_memop;</div>\r\n" - "<div> </div>\r\n" - "<div> if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {</div>\r\n" - "<div> tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);</div>\r\n" - "<div>@@ -2911,7 +2911,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 swap = NULL;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -2953,7 +2953,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)</div>\r\n" - "<div>+static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (opc & MO_SSIZE) {</div>\r\n" - "<div> case MO_SB:</div>\r\n" - "<div>@@ -2974,7 +2974,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)</div>\r\n" - "<div> }</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc)</div>\r\n" - "<div>+static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc)</div>\r\n" - "<div> {</div>\r\n" - "<div> switch (opc & MO_SSIZE) {</div>\r\n" - "<div> case MO_SB:</div>\r\n" - "<div>@@ -3034,7 +3034,7 @@ static void * const table_cmpxchg[16] = {</div>\r\n" - "<div> };</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div>\r\n" - "<div>- TCGv_i32 newv, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+ TCGv_i32 newv, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> memop = tcg_canonicalize_memop(memop, 0, 0);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3078,7 +3078,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div>\r\n" - "<div>- TCGv_i64 newv, TCGArg idx, TCGMemOp memop)</div>\r\n" - "<div>+ TCGv_i64 newv, TCGArg idx, MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3142,7 +3142,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div>\r\n" - "<div>- TCGArg idx, TCGMemOp memop, bool new_val,</div>\r\n" - "<div>+ TCGArg idx, MemOp memop, bool new_val,</div>\r\n" - "<div> void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i32 t1 = tcg_temp_new_i32();</div>\r\n" - "<div>@@ -3160,7 +3160,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div>\r\n" - "<div>- TCGArg idx, TCGMemOp memop, void * const table[])</div>\r\n" - "<div>+ TCGArg idx, MemOp memop, void * const table[])</div>\r\n" - "<div> {</div>\r\n" - "<div> gen_atomic_op_i32 gen;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3185,7 +3185,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div>- TCGArg idx, TCGMemOp memop, bool new_val,</div>\r\n" - "<div>+ TCGArg idx, MemOp memop, bool new_val,</div>\r\n" - "<div> void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGv_i64 t1 = tcg_temp_new_i64();</div>\r\n" - "<div>@@ -3203,7 +3203,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,</div>\r\n" - "<div>- TCGArg idx, TCGMemOp memop, void * const table[])</div>\r\n" - "<div>+ TCGArg idx, MemOp memop, void * const table[])</div>\r\n" - "<div> {</div>\r\n" - "<div> memop = tcg_canonicalize_memop(memop, 1, 0);</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -3257,7 +3257,7 @@ static void * const table_##NAME[16] = { \\</div>\r\n" - "<div> WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be) \\</div>\r\n" - "<div> }; \\</div>\r\n" - "<div> void tcg_gen_atomic_##NAME##_i32 \\</div>\r\n" - "<div>- (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \\</div>\r\n" - "<div>+ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \\</div>\r\n" - "<div> { \\</div>\r\n" - "<div> if (tcg_ctx->tb_cflags & CF_PARALLEL) { \\</div>\r\n" - "<div> do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \\</div>\r\n" - "<div>@@ -3267,7 +3267,7 @@ void tcg_gen_atomic_##NAME##_i32 \\</div>\r\n" - "<div> } \\</div>\r\n" - "<div> } \\</div>\r\n" - "<div> void tcg_gen_atomic_##NAME##_i64 \\</div>\r\n" - "<div>- (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \\</div>\r\n" - "<div>+ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \\</div>\r\n" - "<div> { \\</div>\r\n" - "<div> if (tcg_ctx->tb_cflags & CF_PARALLEL) { \\</div>\r\n" - "<div> do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \\</div>\r\n" - "<div>diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h</div>\r\n" - "<div>index 2d4dd5c..e9cf172 100644</div>\r\n" - "<div>--- a/tcg/tcg-op.h</div>\r\n" - "<div>+++ b/tcg/tcg-op.h</div>\r\n" - "<div>@@ -851,10 +851,10 @@ void tcg_gen_lookup_and_goto_ptr(void);</div>\r\n" - "<div> #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64</div>\r\n" - "<div> #endif</div>\r\n" - "<div> </div>\r\n" - "<div>-void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);</div>\r\n" - "<div>+void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);</div>\r\n" - "<div> </div>\r\n" - "<div> static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)</div>\r\n" - "<div> {</div>\r\n" - "<div>@@ -912,46 +912,46 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,</div>\r\n" - "<div>- TCGArg, TCGMemOp);</div>\r\n" - "<div>+ TCGArg, MemOp);</div>\r\n" - "<div> void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,</div>\r\n" - "<div>- TCGArg, TCGMemOp);</div>\r\n" - "<div>-</div>\r\n" - "<div>-void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-</div>\r\n" - "<div>-void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);</div>\r\n" - "<div>-void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);</div>\r\n" - "<div>+ TCGArg, MemOp);</div>\r\n" - "<div>+</div>\r\n" - "<div>+void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+</div>\r\n" - "<div>+void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);</div>\r\n" - "<div>+void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);</div>\r\n" - "<div> </div>\r\n" - "<div> void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);</div>\r\n" - "<div> void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);</div>\r\n" - "<div>diff --git a/tcg/tcg.c b/tcg/tcg.c</div>\r\n" - "<div>index 8d23fb0..0dff196 100644</div>\r\n" - "<div>--- a/tcg/tcg.c</div>\r\n" - "<div>+++ b/tcg/tcg.c</div>\r\n" - "<div>@@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)</div>\r\n" - "<div> case INDEX_op_qemu_st_i64:</div>\r\n" - "<div> {</div>\r\n" - "<div> TCGMemOpIdx oi = op->args[k++];</div>\r\n" - "<div>- TCGMemOp op = get_memop(oi);</div>\r\n" - "<div>+ MemOp op = get_memop(oi);</div>\r\n" - "<div> unsigned ix = get_mmuidx(oi);</div>\r\n" - "<div> </div>\r\n" - "<div> if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {</div>\r\n" - "<div>diff --git a/tcg/tcg.h b/tcg/tcg.h</div>\r\n" - "<div>index 529acb2..a37181c 100644</div>\r\n" - "<div>--- a/tcg/tcg.h</div>\r\n" - "<div>+++ b/tcg/tcg.h</div>\r\n" - "<div>@@ -26,6 +26,7 @@</div>\r\n" - "<div> #define TCG_H</div>\r\n" - "<div> </div>\r\n" - "<div> #include "cpu.h"</div>\r\n" - "<div>+#include "exec/memop.h"</div>\r\n" - "<div> #include "exec/tb-context.h"</div>\r\n" - "<div> #include "qemu/bitops.h"</div>\r\n" - "<div> #include "qemu/queue.h"</div>\r\n" - "<div>@@ -309,103 +310,13 @@ typedef enum TCGType {</div>\r\n" - "<div> #endif</div>\r\n" - "<div> } TCGType;</div>\r\n" - "<div> </div>\r\n" - "<div>-/* Constants for qemu_ld and qemu_st for the Memory Operation field. */</div>\r\n" - "<div>-typedef enum TCGMemOp {</div>\r\n" - "<div>- MO_8 = 0,</div>\r\n" - "<div>- MO_16 = 1,</div>\r\n" - "<div>- MO_32 = 2,</div>\r\n" - "<div>- MO_64 = 3,</div>\r\n" - "<div>- MO_SIZE = 3, /* Mask for the above. */</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_BSWAP = 8, /* Host reverse endian. */</div>\r\n" - "<div>-#ifdef HOST_WORDS_BIGENDIAN</div>\r\n" - "<div>- MO_LE = MO_BSWAP,</div>\r\n" - "<div>- MO_BE = 0,</div>\r\n" - "<div>-#else</div>\r\n" - "<div>- MO_LE = 0,</div>\r\n" - "<div>- MO_BE = MO_BSWAP,</div>\r\n" - "<div>-#endif</div>\r\n" - "<div>-#ifdef TARGET_WORDS_BIGENDIAN</div>\r\n" - "<div>- MO_TE = MO_BE,</div>\r\n" - "<div>-#else</div>\r\n" - "<div>- MO_TE = MO_LE,</div>\r\n" - "<div>-#endif</div>\r\n" - "<div>-</div>\r\n" - "<div>- /*</div>\r\n" - "<div>- * MO_UNALN accesses are never checked for alignment.</div>\r\n" - "<div>- * MO_ALIGN accesses will result in a call to the CPU's</div>\r\n" - "<div>- * do_unaligned_access hook if the guest address is not aligned.</div>\r\n" - "<div>- * The default depends on whether the target CPU defines</div>\r\n" - "<div>- * TARGET_ALIGNED_ONLY.</div>\r\n" - "<div>- *</div>\r\n" - "<div>- * Some architectures (e.g. ARMv8) need the address which is aligned</div>\r\n" - "<div>- * to a size more than the size of the memory access.</div>\r\n" - "<div>- * Some architectures (e.g. SPARCv9) need an address which is aligned,</div>\r\n" - "<div>- * but less strictly than the natural alignment.</div>\r\n" - "<div>- *</div>\r\n" - "<div>- * MO_ALIGN supposes the alignment size is the size of a memory access.</div>\r\n" - "<div>- *</div>\r\n" - "<div>- * There are three options:</div>\r\n" - "<div>- * - unaligned access permitted (MO_UNALN).</div>\r\n" - "<div>- * - an alignment to the size of an access (MO_ALIGN);</div>\r\n" - "<div>- * - an alignment to a specified size, which may be more or less than</div>\r\n" - "<div>- * the access size (MO_ALIGN_x where 'x' is a size in bytes);</div>\r\n" - "<div>- */</div>\r\n" - "<div>- MO_ASHIFT = 4,</div>\r\n" - "<div>- MO_AMASK = 7 << MO_ASHIFT,</div>\r\n" - "<div>-#ifdef TARGET_ALIGNED_ONLY</div>\r\n" - "<div>- MO_ALIGN = 0,</div>\r\n" - "<div>- MO_UNALN = MO_AMASK,</div>\r\n" - "<div>-#else</div>\r\n" - "<div>- MO_ALIGN = MO_AMASK,</div>\r\n" - "<div>- MO_UNALN = 0,</div>\r\n" - "<div>-#endif</div>\r\n" - "<div>- MO_ALIGN_2 = 1 << MO_ASHIFT,</div>\r\n" - "<div>- MO_ALIGN_4 = 2 << MO_ASHIFT,</div>\r\n" - "<div>- MO_ALIGN_8 = 3 << MO_ASHIFT,</div>\r\n" - "<div>- MO_ALIGN_16 = 4 << MO_ASHIFT,</div>\r\n" - "<div>- MO_ALIGN_32 = 5 << MO_ASHIFT,</div>\r\n" - "<div>- MO_ALIGN_64 = 6 << MO_ASHIFT,</div>\r\n" - "<div>-</div>\r\n" - "<div>- /* Combinations of the above, for ease of use. */</div>\r\n" - "<div>- MO_UB = MO_8,</div>\r\n" - "<div>- MO_UW = MO_16,</div>\r\n" - "<div>- MO_UL = MO_32,</div>\r\n" - "<div>- MO_SB = MO_SIGN | MO_8,</div>\r\n" - "<div>- MO_SW = MO_SIGN | MO_16,</div>\r\n" - "<div>- MO_SL = MO_SIGN | MO_32,</div>\r\n" - "<div>- MO_Q = MO_64,</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_LEUW = MO_LE | MO_UW,</div>\r\n" - "<div>- MO_LEUL = MO_LE | MO_UL,</div>\r\n" - "<div>- MO_LESW = MO_LE | MO_SW,</div>\r\n" - "<div>- MO_LESL = MO_LE | MO_SL,</div>\r\n" - "<div>- MO_LEQ = MO_LE | MO_Q,</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_BEUW = MO_BE | MO_UW,</div>\r\n" - "<div>- MO_BEUL = MO_BE | MO_UL,</div>\r\n" - "<div>- MO_BESW = MO_BE | MO_SW,</div>\r\n" - "<div>- MO_BESL = MO_BE | MO_SL,</div>\r\n" - "<div>- MO_BEQ = MO_BE | MO_Q,</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_TEUW = MO_TE | MO_UW,</div>\r\n" - "<div>- MO_TEUL = MO_TE | MO_UL,</div>\r\n" - "<div>- MO_TESW = MO_TE | MO_SW,</div>\r\n" - "<div>- MO_TESL = MO_TE | MO_SL,</div>\r\n" - "<div>- MO_TEQ = MO_TE | MO_Q,</div>\r\n" - "<div>-</div>\r\n" - "<div>- MO_SSIZE = MO_SIZE | MO_SIGN,</div>\r\n" - "<div>-} TCGMemOp;</div>\r\n" - "<div>-</div>\r\n" - "<div> /**</div>\r\n" - "<div> * get_alignment_bits</div>\r\n" - "<div>- * @memop: TCGMemOp value</div>\r\n" - "<div>+ * @memop: MemOp value</div>\r\n" - "<div> *</div>\r\n" - "<div> * Extract the alignment size from the memop.</div>\r\n" - "<div> */</div>\r\n" - "<div>-static inline unsigned get_alignment_bits(TCGMemOp memop)</div>\r\n" - "<div>+static inline unsigned get_alignment_bits(MemOp memop)</div>\r\n" - "<div> {</div>\r\n" - "<div> unsigned a = memop & MO_AMASK;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -1186,7 +1097,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)</div>\r\n" - "<div> return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-/* Combine the TCGMemOp and mmu_idx parameters into a single value. */</div>\r\n" - "<div>+/* Combine the MemOp and mmu_idx parameters into a single value. */</div>\r\n" - "<div> typedef uint32_t TCGMemOpIdx;</div>\r\n" - "<div> </div>\r\n" - "<div> /**</div>\r\n" - "<div>@@ -1196,7 +1107,7 @@ typedef uint32_t TCGMemOpIdx;</div>\r\n" - "<div> *</div>\r\n" - "<div> * Encode these values into a single parameter.</div>\r\n" - "<div> */</div>\r\n" - "<div>-static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)</div>\r\n" - "<div>+static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)</div>\r\n" - "<div> {</div>\r\n" - "<div> tcg_debug_assert(idx <= 15);</div>\r\n" - "<div> return (op << 4) | idx;</div>\r\n" - "<div>@@ -1208,7 +1119,7 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)</div>\r\n" - "<div> *</div>\r\n" - "<div> * Extract the memory operation from the combined value.</div>\r\n" - "<div> */</div>\r\n" - "<div>-static inline TCGMemOp get_memop(TCGMemOpIdx oi)</div>\r\n" - "<div>+static inline MemOp get_memop(TCGMemOpIdx oi)</div>\r\n" - "<div> {</div>\r\n" - "<div> return oi >> 4;</div>\r\n" - "<div> }</div>\r\n" - "<div>diff --git a/trace/mem-internal.h b/trace/mem-internal.h</div>\r\n" - "<div>index f6efaf6..3444fbc 100644</div>\r\n" - "<div>--- a/trace/mem-internal.h</div>\r\n" - "<div>+++ b/trace/mem-internal.h</div>\r\n" - "<div>@@ -16,7 +16,7 @@</div>\r\n" - "<div> #define TRACE_MEM_ST (1ULL << 5) /* store (y/n) */</div>\r\n" - "<div> </div>\r\n" - "<div> static inline uint8_t trace_mem_build_info(</div>\r\n" - "<div>- int size_shift, bool sign_extend, TCGMemOp endianness, bool store)</div>\r\n" - "<div>+ int size_shift, bool sign_extend, MemOp endianness, bool store)</div>\r\n" - "<div> {</div>\r\n" - "<div> uint8_t res;</div>\r\n" - "<div> </div>\r\n" - "<div>@@ -33,7 +33,7 @@ static inline uint8_t trace_mem_build_info(</div>\r\n" - "<div> return res;</div>\r\n" - "<div> }</div>\r\n" - "<div> </div>\r\n" - "<div>-static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)</div>\r\n" - "<div>+static inline uint8_t trace_mem_get_info(MemOp op, bool store)</div>\r\n" - "<div> {</div>\r\n" - "<div> return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),</div>\r\n" - "<div> op & MO_BSWAP, store);</div>\r\n" - "<div>diff --git a/trace/mem.h b/trace/mem.h</div>\r\n" - "<div>index 2b58196..8cf213d 100644</div>\r\n" - "<div>--- a/trace/mem.h</div>\r\n" - "<div>+++ b/trace/mem.h</div>\r\n" - "<div>@@ -18,7 +18,7 @@</div>\r\n" - "<div> *</div>\r\n" - "<div> * Return a value for the 'info' argument in guest memory access traces.</div>\r\n" - "<div> */</div>\r\n" - "<div>-static uint8_t trace_mem_get_info(TCGMemOp op, bool store);</div>\r\n" - "<div>+static uint8_t trace_mem_get_info(MemOp op, bool store);</div>\r\n" - "<div> </div>\r\n" - "<div> /**</div>\r\n" - "<div> * trace_mem_build_info:</div>\r\n" - "<div>@@ -26,7 +26,7 @@ static uint8_t trace_mem_get_info(TCGMemOp op, bool store);</div>\r\n" - "<div> * Return a value for the 'info' argument in guest memory access traces.</div>\r\n" - "<div> */</div>\r\n" - "<div> static uint8_t trace_mem_build_info(int size_shift, bool sign_extend,</div>\r\n" - "<div>- TCGMemOp endianness, bool store);</div>\r\n" - "<div>+ MemOp endianness, bool store);</div>\r\n" - "<div> </div>\r\n" - "<div> </div>\r\n" - "<div> #include "trace/mem-internal.h"</div>\r\n" - "<div>-- </div>\r\n" - "<div>1.8.3.1</div>\r\n" - "<div><br>\r\n" - "​<br>\r\n" - "</div>\r\n" - "<p><br>\r\n" - "</p>\r\n" - "</body>\r\n" - "</html>\r\n" -db8536e3ed94cbe04b09d62e3589775b76edac95045071f5f61d3b26de193fa8 +5528ae3c4f86d3bd2ad4529b6486519c2167ad4ea7463502f322f4e78ac177ed
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.