From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iCkbA-00082k-8o for mharc-qemu-riscv@gnu.org; Tue, 24 Sep 2019 09:11:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51829) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCcx6-0002Ef-Vk for qemu-riscv@nongnu.org; Tue, 24 Sep 2019 01:01:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCcx5-0002Vq-Rz for qemu-riscv@nongnu.org; Tue, 24 Sep 2019 01:01:28 -0400 Received: from mail.kernel.org ([198.145.29.99]:42318) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCcx0-0002SV-Gm; Tue, 24 Sep 2019 01:01:22 -0400 Received: from guoren-Inspiron-7460.lan (unknown [223.93.147.148]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E62BF20872; Tue, 24 Sep 2019 05:00:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569301277; bh=n1RdI/OAQ/Vw9nYytQuGvnrhjR9yJhMd+lcOx6KQFv8=; h=From:To:Cc:Subject:Date:From; b=XntcTVCQElHvXgfQECcraAyn8QkgAwmxqKipHF0Q2uGOCXdfk9/CfaF52nEFsDHih D88ImgDkR3tnHgnmVBPFEeD/QekZyi6KFnoYrdnm04UEgBpb5bPKkCTD3c5xUbxIjB Fn+RASkpqoYtdRv6tll1cnrhz742yKIvNx5/VDYw= From: guoren@kernel.org To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@sifive.com, alistair23@gmail.com, Guo Ren Subject: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64 Date: Tue, 24 Sep 2019 13:00:32 +0800 Message-Id: <1569301232-7128-1-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 198.145.29.99 X-Mailman-Approved-At: Tue, 24 Sep 2019 09:11:19 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Sep 2019 05:01:32 -0000 From: Guo Ren Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we need to ignore them. They can not be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System Signed-off-by: Guo Ren Reviewed-by: Liu Zhiwei --- target/riscv/cpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 87dd6a6..3c5e8f6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -260,6 +260,7 @@ restart: target_ulong pte = ldl_phys(cs->as, pte_addr); #elif defined(TARGET_RISCV64) target_ulong pte = ldq_phys(cs->as, pte_addr); + pte = pte << 10 >> 10; #endif hwaddr ppn = pte >> PTE_PPN_SHIFT; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0645AC432C1 for ; Tue, 24 Sep 2019 05:04:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C671420872 for ; Tue, 24 Sep 2019 05:04:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="XntcTVCQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C671420872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:40794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCczo-00047e-Ar for qemu-devel@archiver.kernel.org; Tue, 24 Sep 2019 01:04:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51804) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCcx4-0002A9-LB for qemu-devel@nongnu.org; Tue, 24 Sep 2019 01:01:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCcx2-0002UO-Gp for qemu-devel@nongnu.org; Tue, 24 Sep 2019 01:01:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:42318) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCcx0-0002SV-Gm; Tue, 24 Sep 2019 01:01:22 -0400 Received: from guoren-Inspiron-7460.lan (unknown [223.93.147.148]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E62BF20872; Tue, 24 Sep 2019 05:00:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569301277; bh=n1RdI/OAQ/Vw9nYytQuGvnrhjR9yJhMd+lcOx6KQFv8=; h=From:To:Cc:Subject:Date:From; b=XntcTVCQElHvXgfQECcraAyn8QkgAwmxqKipHF0Q2uGOCXdfk9/CfaF52nEFsDHih D88ImgDkR3tnHgnmVBPFEeD/QekZyi6KFnoYrdnm04UEgBpb5bPKkCTD3c5xUbxIjB Fn+RASkpqoYtdRv6tll1cnrhz742yKIvNx5/VDYw= From: guoren@kernel.org To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64 Date: Tue, 24 Sep 2019 13:00:32 +0800 Message-Id: <1569301232-7128-1-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 198.145.29.99 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, Guo Ren Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Guo Ren Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we need to ignore them. They can not be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System Signed-off-by: Guo Ren Reviewed-by: Liu Zhiwei --- target/riscv/cpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 87dd6a6..3c5e8f6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -260,6 +260,7 @@ restart: target_ulong pte = ldl_phys(cs->as, pte_addr); #elif defined(TARGET_RISCV64) target_ulong pte = ldq_phys(cs->as, pte_addr); + pte = pte << 10 >> 10; #endif hwaddr ppn = pte >> PTE_PPN_SHIFT; -- 2.7.4