From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v5, 10/32] drm/mediatek: add mutex sof register offset into ddp private data Date: Wed, 9 Oct 2019 17:33:36 +0800 Message-ID: <1570613616.7713.13.camel@mtksdaap41> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: yongqiang.niu@mediatek.com Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFlvbmdxaWFuZzoKCk9uIFRodSwgMjAxOS0wOC0yOSBhdCAyMjo1MCArMDgwMCwgeW9uZ3Fp YW5nLm5pdUBtZWRpYXRlay5jb20gd3JvdGU6Cj4gRnJvbTogWW9uZ3FpYW5nIE5pdSA8eW9uZ3Fp YW5nLm5pdUBtZWRpYXRlay5jb20+Cj4gCj4gbXV0ZXggc29mIHJlZ2lzdGVyIG9mZnNldCB3aWxs IGJlIHByaXZhdGUgZGF0YSBvZiBkZHAKPiAKCkFwcGxpZWQgdG8gbWVkaWF0ZWstZHJtLW5leHQt NS41IFsxXSwgdGhhbmtzLgoKWzFdCmh0dHBzOi8vZ2l0aHViLmNvbS9ja2h1LW1lZGlhdGVrL2xp bnV4LmdpdC10YWdzL2NvbW1pdHMvbWVkaWF0ZWstZHJtLW5leHQtNS41CgpSZWdhcmRzLApDSwoK PiBTaWduZWQtb2ZmLWJ5OiBZb25ncWlhbmcgTml1IDx5b25ncWlhbmcubml1QG1lZGlhdGVrLmNv bT4KPiBSZXZpZXdlZC1ieTogQ0sgSHUgPGNrLmh1QG1lZGlhdGVrLmNvbT4KPiAtLS0KPiAgZHJp dmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMgfCAxMyArKysrKysrKysrLS0tCj4g IDEgZmlsZSBjaGFuZ2VkLCAxMCBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQo+IAo+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYyBiL2RyaXZl cnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jCj4gaW5kZXggOWJkYmQ4ZC4uNDg2NmE5 YiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYwo+ ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jCj4gQEAgLTM0LDEy ICszNCwxMyBAQAo+ICAjZGVmaW5lIERJU1BfUkVHX0NPTkZJR19EUElfU0VMCQkJMHgwNjQKPiAg Cj4gICNkZWZpbmUgTVQyNzAxX0RJU1BfTVVURVgwX01PRDAJCQkweDJjCj4gKyNkZWZpbmUgTVQy NzAxX0RJU1BfTVVURVgwX1NPRjAJCQkweDMwCj4gIAo+ICAjZGVmaW5lIERJU1BfUkVHX01VVEVY X0VOKG4pCQkJKDB4MjAgKyAweDIwICogKG4pKQo+ICAjZGVmaW5lIERJU1BfUkVHX01VVEVYKG4p CQkJKDB4MjQgKyAweDIwICogKG4pKQo+ICAjZGVmaW5lIERJU1BfUkVHX01VVEVYX1JTVChuKQkJ CSgweDI4ICsgMHgyMCAqIChuKSkKPiAgI2RlZmluZSBESVNQX1JFR19NVVRFWF9NT0QobXV0ZXhf bW9kX3JlZywgbikJKG11dGV4X21vZF9yZWcgKyAweDIwICogKG4pKQo+IC0jZGVmaW5lIERJU1Bf UkVHX01VVEVYX1NPRihuKQkJCSgweDMwICsgMHgyMCAqIChuKSkKPiArI2RlZmluZSBESVNQX1JF R19NVVRFWF9TT0YobXV0ZXhfc29mX3JlZywgbikJKG11dGV4X3NvZl9yZWcgKyAweDIwICogKG4p KQo+ICAjZGVmaW5lIERJU1BfUkVHX01VVEVYX01PRDIobikJCQkoMHgzNCArIDB4MjAgKiAobikp Cj4gIAo+ICAjZGVmaW5lIElOVF9NVVRFWAkJCQlCSVQoMSkKPiBAQCAtMTU1LDYgKzE1Niw3IEBA IHN0cnVjdCBtdGtfZGRwX2RhdGEgewo+ICAJY29uc3QgdW5zaWduZWQgaW50ICptdXRleF9tb2Q7 Cj4gIAljb25zdCB1bnNpZ25lZCBpbnQgKm11dGV4X3NvZjsKPiAgCWNvbnN0IHVuc2lnbmVkIGlu dCBtdXRleF9tb2RfcmVnOwo+ICsJY29uc3QgdW5zaWduZWQgaW50IG11dGV4X3NvZl9yZWc7Cj4g IH07Cj4gIAo+ICBzdHJ1Y3QgbXRrX2RkcCB7Cj4gQEAgLTIyNiwxOCArMjI4LDIxIEBAIHN0cnVj dCBtdGtfZGRwIHsKPiAgCS5tdXRleF9tb2QgPSBtdDI3MDFfbXV0ZXhfbW9kLAo+ICAJLm11dGV4 X3NvZiA9IG10MjcxMl9tdXRleF9zb2YsCj4gIAkubXV0ZXhfbW9kX3JlZyA9IE1UMjcwMV9ESVNQ X01VVEVYMF9NT0QwLAo+ICsJLm11dGV4X3NvZl9yZWcgPSBNVDI3MDFfRElTUF9NVVRFWDBfU09G MCwKPiAgfTsKPiAgCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX2RkcF9kYXRhIG10MjcxMl9k ZHBfZHJpdmVyX2RhdGEgPSB7Cj4gIAkubXV0ZXhfbW9kID0gbXQyNzEyX211dGV4X21vZCwKPiAg CS5tdXRleF9zb2YgPSBtdDI3MTJfbXV0ZXhfc29mLAo+ICAJLm11dGV4X21vZF9yZWcgPSBNVDI3 MDFfRElTUF9NVVRFWDBfTU9EMCwKPiArCS5tdXRleF9zb2ZfcmVnID0gTVQyNzAxX0RJU1BfTVVU RVgwX1NPRjAsCj4gIH07Cj4gIAo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfZGF0YSBt dDgxNzNfZGRwX2RyaXZlcl9kYXRhID0gewo+ICAJLm11dGV4X21vZCA9IG10ODE3M19tdXRleF9t b2QsCj4gIAkubXV0ZXhfc29mID0gbXQyNzEyX211dGV4X3NvZiwKPiAgCS5tdXRleF9tb2RfcmVn ID0gTVQyNzAxX0RJU1BfTVVURVgwX01PRDAsCj4gKwkubXV0ZXhfc29mX3JlZyA9IE1UMjcwMV9E SVNQX01VVEVYMF9TT0YwLAo+ICB9Owo+ICAKPiAgc3RhdGljIHVuc2lnbmVkIGludCBtdGtfZGRw X21vdXRfZW4oZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLAo+IEBAIC01MTksNyArNTI0LDggQEAg dm9pZCBtdGtfZGlzcF9tdXRleF9hZGRfY29tcChzdHJ1Y3QgbXRrX2Rpc3BfbXV0ZXggKm11dGV4 LAo+ICAJfQo+ICAKPiAgCXdyaXRlbF9yZWxheGVkKGRkcC0+ZGF0YS0+bXV0ZXhfc29mW3NvZl9p ZF0sCj4gLQkJICAgICAgIGRkcC0+cmVncyArIERJU1BfUkVHX01VVEVYX1NPRihtdXRleC0+aWQp KTsKPiArCQkgICAgICAgZGRwLT5yZWdzICsKPiArCQkgICAgICAgRElTUF9SRUdfTVVURVhfU09G KGRkcC0+ZGF0YS0+bXV0ZXhfc29mX3JlZywgbXV0ZXgtPmlkKSk7Cj4gIH0KPiAgCj4gIHZvaWQg bXRrX2Rpc3BfbXV0ZXhfcmVtb3ZlX2NvbXAoc3RydWN0IG10a19kaXNwX211dGV4ICptdXRleCwK PiBAQCAtNTQxLDcgKzU0Nyw4IEBAIHZvaWQgbXRrX2Rpc3BfbXV0ZXhfcmVtb3ZlX2NvbXAoc3Ry dWN0IG10a19kaXNwX211dGV4ICptdXRleCwKPiAgCWNhc2UgRERQX0NPTVBPTkVOVF9EUEkxOgo+ ICAJCXdyaXRlbF9yZWxheGVkKE1VVEVYX1NPRl9TSU5HTEVfTU9ERSwKPiAgCQkJICAgICAgIGRk cC0+cmVncyArCj4gLQkJCSAgICAgICBESVNQX1JFR19NVVRFWF9TT0YobXV0ZXgtPmlkKSk7Cj4g KwkJCSAgICAgICBESVNQX1JFR19NVVRFWF9TT0YoZGRwLT5kYXRhLT5tdXRleF9zb2ZfcmVnLAo+ ICsJCQkJCQkgIG11dGV4LT5pZCkpOwo+ICAJCWJyZWFrOwo+ICAJZGVmYXVsdDoKPiAgCQlpZiAo ZGRwLT5kYXRhLT5tdXRleF9tb2RbaWRdIDwgMzIpIHsKCgpfX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZl bEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFp bG1hbi9saXN0aW5mby9kcmktZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38167C47404 for ; Wed, 9 Oct 2019 10:19:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0781D21848 for ; Wed, 9 Oct 2019 10:19:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="i/Jfpung" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0781D21848 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=748KmNQvI8FneU0FVmYzXnA8dt0SKjHxammJJ7wTIv4=; b=i/Jfpung18Mb+y Hko2cVYKaTjWgQqg1uW7nUxils7Bu2TD+3RgAsw9BGUt4ANBay5pWmoYIGG8jsqUq2tDpjIJejorU TkTvTYutgCinBEpwuOj0mmO5uvnNTsFF+xDsWLXHLK7e5dod0cZoLXUpvWgzwL0VmKPK9tku19URa i0+re3HyGsrzEM/SWTx/oo9iCiLLuXmahNlvIeqDhjQ+SsMoAvx6xryk00V/V3xO5WA71i9tkYIJZ qoFqQeEbG3DSPpArd/Z5SroDYjN2+nelBfePncluu5qSgRw6CnwuQ+33we86OOc4btovCiYhYX0mS TdUYUHUdARFOCC4Ki8FA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iI93x-0000YX-4z; Wed, 09 Oct 2019 10:19:21 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iI93h-0000IJ-KR; Wed, 09 Oct 2019 10:19:07 +0000 X-UUID: 2d6ef7fb739a4a3e8c9d65599f03cc01-20191009 X-UUID: 2d6ef7fb739a4a3e8c9d65599f03cc01-20191009 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 2022212364; Wed, 09 Oct 2019 02:19:08 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 03:18:54 -0700 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 17:33:33 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 17:33:33 +0800 Message-ID: <1570613616.7713.13.camel@mtksdaap41> Subject: Re: [PATCH v5, 10/32] drm/mediatek: add mutex sof register offset into ddp private data From: CK Hu To: Date: Wed, 9 Oct 2019 17:33:36 +0800 In-Reply-To: <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 249AE8EC08E0A52E09ECE236DDF6C34DA7BE6F12C7E6CED2986292B9B84AD3502000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191009_031905_683854_6102B46A X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > mutex sof register offset will be private data of ddp > Applied to mediatek-drm-next-5.5 [1], thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK > Signed-off-by: Yongqiang Niu > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 9bdbd8d..4866a9b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -34,12 +34,13 @@ > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > +#define MT2701_DISP_MUTEX0_SOF0 0x30 > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) > -#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > @@ -155,6 +156,7 @@ struct mtk_ddp_data { > const unsigned int *mutex_mod; > const unsigned int *mutex_sof; > const unsigned int mutex_mod_reg; > + const unsigned int mutex_sof_reg; > }; > > struct mtk_ddp { > @@ -226,18 +228,21 @@ struct mtk_ddp { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt2712_ddp_driver_data = { > .mutex_mod = mt2712_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_mod = mt8173_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > @@ -519,7 +524,8 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > } > > writel_relaxed(ddp->data->mutex_sof[sof_id], > - ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > + ddp->regs + > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); > } > > void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > @@ -541,7 +547,8 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > case DDP_COMPONENT_DPI1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > ddp->regs + > - DISP_REG_MUTEX_SOF(mutex->id)); > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, > + mutex->id)); > break; > default: > if (ddp->data->mutex_mod[id] < 32) { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5916BC47404 for ; Wed, 9 Oct 2019 09:33:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C28720B7C for ; Wed, 9 Oct 2019 09:33:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730621AbfJIJdp (ORCPT ); Wed, 9 Oct 2019 05:33:45 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:22879 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725942AbfJIJdo (ORCPT ); Wed, 9 Oct 2019 05:33:44 -0400 X-UUID: bd1c4bed054b419e875e3979d164f1cd-20191009 X-UUID: bd1c4bed054b419e875e3979d164f1cd-20191009 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1626025133; Wed, 09 Oct 2019 17:33:36 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 17:33:33 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 17:33:33 +0800 Message-ID: <1570613616.7713.13.camel@mtksdaap41> Subject: Re: [PATCH v5, 10/32] drm/mediatek: add mutex sof register offset into ddp private data From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 9 Oct 2019 17:33:36 +0800 In-Reply-To: <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-11-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 249AE8EC08E0A52E09ECE236DDF6C34DA7BE6F12C7E6CED2986292B9B84AD3502000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > mutex sof register offset will be private data of ddp > Applied to mediatek-drm-next-5.5 [1], thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK > Signed-off-by: Yongqiang Niu > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 9bdbd8d..4866a9b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -34,12 +34,13 @@ > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > +#define MT2701_DISP_MUTEX0_SOF0 0x30 > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) > -#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > @@ -155,6 +156,7 @@ struct mtk_ddp_data { > const unsigned int *mutex_mod; > const unsigned int *mutex_sof; > const unsigned int mutex_mod_reg; > + const unsigned int mutex_sof_reg; > }; > > struct mtk_ddp { > @@ -226,18 +228,21 @@ struct mtk_ddp { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt2712_ddp_driver_data = { > .mutex_mod = mt2712_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_mod = mt8173_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > @@ -519,7 +524,8 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > } > > writel_relaxed(ddp->data->mutex_sof[sof_id], > - ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > + ddp->regs + > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); > } > > void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > @@ -541,7 +547,8 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > case DDP_COMPONENT_DPI1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > ddp->regs + > - DISP_REG_MUTEX_SOF(mutex->id)); > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, > + mutex->id)); > break; > default: > if (ddp->data->mutex_mod[id] < 32) {