From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:51242 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbeINCUC (ORCPT ); Thu, 13 Sep 2018 22:20:02 -0400 From: Laurent Pinchart To: jacopo mondi Cc: Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Archit Taneja , Andrzej Hajda Subject: Re: [PATCH 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency Date: Fri, 14 Sep 2018 00:08:50 +0300 Message-ID: <1575091.vT7yhvHn82@avalon> In-Reply-To: <20180911133155.GV28160@w540> References: <20180904121027.24031-1-laurent.pinchart+renesas@ideasonboard.com> <20180904121027.24031-5-laurent.pinchart+renesas@ideasonboard.com> <20180911133155.GV28160@w540> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Jacopo, On Tuesday, 11 September 2018 16:31:55 EEST jacopo mondi wrote: > Hi Laurent, > sorry, I might be confused but, > > On Tue, Sep 04, 2018 at 03:10:15PM +0300, Laurent Pinchart wrote: > > The THC63LVD1024 is restricted to a pixel clock frequency in the range > > of 8 to 135 MHz. Implement the bridge .mode_valid() operation > > accordingly. > > > > Signed-off-by: Laurent Pinchart > > > > --- > > > > drivers/gpu/drm/bridge/thc63lvd1024.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c > > b/drivers/gpu/drm/bridge/thc63lvd1024.c index c8b9edd5a7f4..63609ba16b6d > > 100644 > > --- a/drivers/gpu/drm/bridge/thc63lvd1024.c > > +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c > > @@ -45,6 +45,23 @@ static int thc63_attach(struct drm_bridge *bridge) > > return drm_bridge_attach(bridge->encoder, thc63->next, bridge); > > } > > > > +static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge, > > + const struct drm_display_mode *mode) > > +{ > > + /* > > + * The THC63LVD0124 clock frequency range is 8 to 135 MHz in single-in, > > + * single-out mode. Note that the limits depends on the mode and will > > + * need to be adjusted accordingly. > > + */ > > + if (mode->clock < 8000) > > + return MODE_CLOCK_LOW; > > + > > + if (mode->clock > 135000) > > + return MODE_CLOCK_HIGH; > > + > > + return MODE_OK; > > +} > > + > > Are we talking about the CLKOUT frequency? Because that's the one I > see depending on the dual/single output mode, and I assume we're > checking for the mode->clock of the DRM mode to be applied to the > connector (which receives an RGB stream from this bridge). > > In case we're talking about CLKOUT, I read > > "Dual LVDS port IN/Dual TTL port Out Mode: > 8 - 135MHz(CLKOUT) > Dual LVDS port IN/Single TTL port Out Mode: > 40 - 150MHz(CLKOUT)" > > If we're talking about the PLL input clock (RCLK) then used to > generate CLKOUT it's indeed defined in the 8-135Mhz range, but > I don't see mention on it depending on the mode. This is about the input clock on the LVDS side of the LVDS decoder, named RCLK. It is received from the LVDS interface on the other side and its frequency is equal to the pixel clock. > > static void thc63_enable(struct drm_bridge *bridge) > > { > > struct thc63_dev *thc63 = to_thc63(bridge); > > @@ -77,6 +94,7 @@ static void thc63_disable(struct drm_bridge *bridge) > > > > static const struct drm_bridge_funcs thc63_bridge_func = { > > .attach = thc63_attach, > > + .mode_valid = thc63_mode_valid, > > .enable = thc63_enable, > > .disable = thc63_disable, > > }; -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 04/16] drm: bridge: thc63: Restrict modes based on hardware operating frequency Date: Fri, 14 Sep 2018 00:08:50 +0300 Message-ID: <1575091.vT7yhvHn82@avalon> References: <20180904121027.24031-1-laurent.pinchart+renesas@ideasonboard.com> <20180904121027.24031-5-laurent.pinchart+renesas@ideasonboard.com> <20180911133155.GV28160@w540> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA37A6E1E1 for ; Thu, 13 Sep 2018 21:08:49 +0000 (UTC) In-Reply-To: <20180911133155.GV28160@w540> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: jacopo mondi Cc: linux-renesas-soc@vger.kernel.org, Laurent Pinchart , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgSmFjb3BvLAoKT24gVHVlc2RheSwgMTEgU2VwdGVtYmVyIDIwMTggMTY6MzE6NTUgRUVTVCBq YWNvcG8gbW9uZGkgd3JvdGU6Cj4gSGkgTGF1cmVudCwKPiAgICBzb3JyeSwgSSBtaWdodCBiZSBj b25mdXNlZCBidXQsCj4gCj4gT24gVHVlLCBTZXAgMDQsIDIwMTggYXQgMDM6MTA6MTVQTSArMDMw MCwgTGF1cmVudCBQaW5jaGFydCB3cm90ZToKPiA+IFRoZSBUSEM2M0xWRDEwMjQgaXMgcmVzdHJp Y3RlZCB0byBhIHBpeGVsIGNsb2NrIGZyZXF1ZW5jeSBpbiB0aGUgcmFuZ2UKPiA+IG9mIDggdG8g MTM1IE1Iei4gSW1wbGVtZW50IHRoZSBicmlkZ2UgLm1vZGVfdmFsaWQoKSBvcGVyYXRpb24KPiA+ IGFjY29yZGluZ2x5Lgo+ID4gCj4gPiBTaWduZWQtb2ZmLWJ5OiBMYXVyZW50IFBpbmNoYXJ0Cj4g PiA8bGF1cmVudC5waW5jaGFydCtyZW5lc2FzQGlkZWFzb25ib2FyZC5jb20+Cj4gPiAtLS0KPiA+ IAo+ID4gIGRyaXZlcnMvZ3B1L2RybS9icmlkZ2UvdGhjNjNsdmQxMDI0LmMgfCAxOCArKysrKysr KysrKysrKysrKysKPiA+ICAxIGZpbGUgY2hhbmdlZCwgMTggaW5zZXJ0aW9ucygrKQo+ID4gCj4g PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS90aGM2M2x2ZDEwMjQuYwo+ID4g Yi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL3RoYzYzbHZkMTAyNC5jIGluZGV4IGM4YjllZGQ1YTdm NC4uNjM2MDliYTE2YjZkCj4gPiAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9icmlk Z2UvdGhjNjNsdmQxMDI0LmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvdGhjNjNs dmQxMDI0LmMKPiA+IEBAIC00NSw2ICs0NSwyMyBAQCBzdGF0aWMgaW50IHRoYzYzX2F0dGFjaChz dHJ1Y3QgZHJtX2JyaWRnZSAqYnJpZGdlKQo+ID4gIAlyZXR1cm4gZHJtX2JyaWRnZV9hdHRhY2go YnJpZGdlLT5lbmNvZGVyLCB0aGM2My0+bmV4dCwgYnJpZGdlKTsKPiA+ICB9Cj4gPiAKPiA+ICtz dGF0aWMgZW51bSBkcm1fbW9kZV9zdGF0dXMgdGhjNjNfbW9kZV92YWxpZChzdHJ1Y3QgZHJtX2Jy aWRnZSAqYnJpZGdlLAo+ID4gKwkJCQkJY29uc3Qgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1v ZGUpCj4gPiArewo+ID4gKwkvKgo+ID4gKwkgKiBUaGUgVEhDNjNMVkQwMTI0IGNsb2NrIGZyZXF1 ZW5jeSByYW5nZSBpcyA4IHRvIDEzNSBNSHogaW4gc2luZ2xlLWluLAo+ID4gKwkgKiBzaW5nbGUt b3V0IG1vZGUuIE5vdGUgdGhhdCB0aGUgbGltaXRzIGRlcGVuZHMgb24gdGhlIG1vZGUgYW5kIHdp bGwKPiA+ICsJICogbmVlZCB0byBiZSBhZGp1c3RlZCBhY2NvcmRpbmdseS4KPiA+ICsJICovCj4g PiArCWlmIChtb2RlLT5jbG9jayA8IDgwMDApCj4gPiArCQlyZXR1cm4gTU9ERV9DTE9DS19MT1c7 Cj4gPiArCj4gPiArCWlmIChtb2RlLT5jbG9jayA+IDEzNTAwMCkKPiA+ICsJCXJldHVybiBNT0RF X0NMT0NLX0hJR0g7Cj4gPiArCj4gPiArCXJldHVybiBNT0RFX09LOwo+ID4gK30KPiA+ICsKPiAK PiBBcmUgd2UgdGFsa2luZyBhYm91dCB0aGUgQ0xLT1VUIGZyZXF1ZW5jeT8gQmVjYXVzZSB0aGF0 J3MgdGhlIG9uZSBJCj4gc2VlIGRlcGVuZGluZyBvbiB0aGUgZHVhbC9zaW5nbGUgb3V0cHV0IG1v ZGUsIGFuZCBJIGFzc3VtZSB3ZSdyZQo+IGNoZWNraW5nIGZvciB0aGUgbW9kZS0+Y2xvY2sgb2Yg dGhlIERSTSBtb2RlIHRvIGJlIGFwcGxpZWQgdG8gdGhlCj4gY29ubmVjdG9yICh3aGljaCByZWNl aXZlcyBhbiBSR0Igc3RyZWFtIGZyb20gdGhpcyBicmlkZ2UpLgo+IAo+IEluIGNhc2Ugd2UncmUg dGFsa2luZyBhYm91dCBDTEtPVVQsIEkgcmVhZAo+IAo+ICJEdWFsIExWRFMgcG9ydCBJTi9EdWFs IFRUTCBwb3J0IE91dCBNb2RlOgo+ICA4IC0gMTM1TUh6KENMS09VVCkKPiAgRHVhbCBMVkRTIHBv cnQgSU4vU2luZ2xlIFRUTCBwb3J0IE91dCBNb2RlOgo+ICA0MCAtIDE1ME1IeihDTEtPVVQpIgo+ IAo+IElmIHdlJ3JlIHRhbGtpbmcgYWJvdXQgdGhlIFBMTCBpbnB1dCBjbG9jayAoUkNMSykgdGhl biB1c2VkIHRvCj4gZ2VuZXJhdGUgQ0xLT1VUIGl0J3MgaW5kZWVkIGRlZmluZWQgaW4gdGhlIDgt MTM1TWh6IHJhbmdlLCBidXQKPiBJIGRvbid0IHNlZSBtZW50aW9uIG9uIGl0IGRlcGVuZGluZyBv biB0aGUgbW9kZS4KClRoaXMgaXMgYWJvdXQgdGhlIGlucHV0IGNsb2NrIG9uIHRoZSBMVkRTIHNp ZGUgb2YgdGhlIExWRFMgZGVjb2RlciwgbmFtZWQgClJDTEsuIEl0IGlzIHJlY2VpdmVkIGZyb20g dGhlIExWRFMgaW50ZXJmYWNlIG9uIHRoZSBvdGhlciBzaWRlIGFuZCBpdHMgCmZyZXF1ZW5jeSBp cyBlcXVhbCB0byB0aGUgcGl4ZWwgY2xvY2suCgo+ID4gIHN0YXRpYyB2b2lkIHRoYzYzX2VuYWJs ZShzdHJ1Y3QgZHJtX2JyaWRnZSAqYnJpZGdlKQo+ID4gIHsKPiA+ICAJc3RydWN0IHRoYzYzX2Rl diAqdGhjNjMgPSB0b190aGM2MyhicmlkZ2UpOwo+ID4gQEAgLTc3LDYgKzk0LDcgQEAgc3RhdGlj IHZvaWQgdGhjNjNfZGlzYWJsZShzdHJ1Y3QgZHJtX2JyaWRnZSAqYnJpZGdlKQo+ID4gCj4gPiAg c3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fYnJpZGdlX2Z1bmNzIHRoYzYzX2JyaWRnZV9mdW5jID0g ewo+ID4gIAkuYXR0YWNoCT0gdGhjNjNfYXR0YWNoLAo+ID4gKwkubW9kZV92YWxpZCA9IHRoYzYz X21vZGVfdmFsaWQsCj4gPiAgCS5lbmFibGUgPSB0aGM2M19lbmFibGUsCj4gPiAgCS5kaXNhYmxl ID0gdGhjNjNfZGlzYWJsZSwKPiA+ICB9OwoKLS0gClJlZ2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0 CgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1k ZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczov L2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo=