From: Simon Veith <sveith@amazon.de>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: Simon Veith <sveith@amazon.de>, Eric Auger <eric.auger@redhat.com>
Subject: [PATCH v2 2/6] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value
Date: Wed, 11 Dec 2019 16:05:39 +0100 [thread overview]
Message-ID: <1576076739-23708-1-git-send-email-sveith@amazon.de> (raw)
In-Reply-To: <1576076260-18659-1-git-send-email-sveith@amazon.de>
There are two issues with the current value of SMMU_BASE_ADDR_MASK:
- At the lower end, we are clearing bits [4:0]. Per the SMMUv3 spec,
we should also be treating bit 5 as zero in the base address.
- At the upper end, we are clearing bits [63:48]. Per the SMMUv3 spec,
only bits [63:52] must be explicitly treated as zero.
Update the SMMU_BASE_ADDR_MASK value to mask out bits [63:52] and [5:0].
ref. ARM IHI 0070C, section 6.3.23.
Signed-off-by: Simon Veith <sveith@amazon.de>
Cc: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
hw/arm/smmuv3-internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index d190181..042b435 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -99,7 +99,7 @@ REG32(GERROR_IRQ_CFG2, 0x74)
#define A_STRTAB_BASE 0x80 /* 64b */
-#define SMMU_BASE_ADDR_MASK 0xffffffffffe0
+#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
REG32(STRTAB_BASE_CFG, 0x88)
FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
--
2.7.4
next prev parent reply other threads:[~2019-12-11 15:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-11 14:57 [PATCH v2 0/6] hw/arm/smmuv3: Correct stream ID and event address handling Simon Veith
2019-12-11 14:57 ` [PATCH v2 1/6] hw/arm/smmuv3: Apply address mask to linear strtab base address Simon Veith
2019-12-11 15:05 ` Simon Veith [this message]
2019-12-11 15:07 ` [PATCH v2 3/6] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE Simon Veith
2019-12-11 15:07 ` [PATCH v2 4/6] hw/arm/smmuv3: Align stream table base address to table size Simon Veith
2019-12-11 15:07 ` [PATCH v2 5/6] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Simon Veith
2019-12-11 15:07 ` [PATCH v2 6/6] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position Simon Veith
2019-12-16 14:45 ` [PATCH v2 0/6] hw/arm/smmuv3: Correct stream ID and event address handling Peter Maydell
2019-12-16 14:56 ` Veith, Simon
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