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[RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: Yong Wu To: Chao Hao Date: Mon, 16 Dec 2019 20:05:01 +0800 In-Reply-To: <20191104115238.2394-2-chao.hao@mediatek.com> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: A9E5E71080A842134B9DA6CCB99242C492F30F72968470E68E8786C7F60B10FC2000:8 X-MTK: N Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > This patch adds description for MT6779 IOMMU. > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > use ARM Short-Descriptor translation format. > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > diagram about iommu, it don't focus on the part of smi_larb, so > I don't describe the smi_larb detailedly. > > EMI > | > -------------------------------------- > | | > MM_IOMMU APU_IOMMU > | | > SMI_COMMOM----------- APU_BUS > | | | > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > | | | > | | -------------- > | | | | | > Multimedia engine CCU VPU MDLA EMDA > > All the connections are hardware fixed, software can not adjust it. > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > but CCU is connected with smi_common directly, we can take them as larb12. > APU_IOMMU provides mapping for APU engine, we can take them larb13. > Larb12 and Larb13 are fake larbs. > > Signed-off-by: Chao Hao > --- > .../bindings/iommu/mediatek,iommu.txt | 2 + > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > 2 files changed, 219 insertions(+) > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > index ce59a505f5a4..c1ccd8582eb2 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > @@ -58,6 +58,7 @@ Required properties: > - compatible : must be one of the following string: > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > generation one m4u HW. > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > @@ -78,6 +79,7 @@ Required properties: > Specifies the mtk_m4u_id as defined in > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > dt-binding/memory/mt8173-larb-port.h for mt8173, and > dt-binding/memory/mt8183-larb-port.h for mt8183. > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > new file mode 100644 > index 000000000000..8b7f2d2446ea > --- /dev/null > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > @@ -0,0 +1,217 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Chao Hao > + */ > + > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > +#define _DTS_IOMMU_PORT_MT6779_H_ > + > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 > +#define M4U_LARB6_ID 6 > +#define M4U_LARB7_ID 7 > +#define M4U_LARB8_ID 8 > +#define M4U_LARB9_ID 9 > +#define M4U_LARB10_ID 10 > +#define M4U_LARB11_ID 11 > +#define M4U_LARB12_ID 12 > +#define M4U_LARB13_ID 13 > + > +/* larb0 */ > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > + > +/* larb1 */ > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > + > +/* larb2-VDEC */ > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > + > +/*larb3-VENC*/ Normally add space before and after the word. Like: /* larb3-VENC */ below are the same. > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > + > +/*larb4-dummy*/ > + > +/*larb5-IMG*/ [snip] > + > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > + > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) When do you need this UNKNOWN one? The other SoC doesn't have it. Please remove if it is unnecessary. > + > +#endif _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42FF4C43603 for ; Mon, 16 Dec 2019 12:05:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate 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+0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 16 Dec 2019 20:04:44 +0800 Message-ID: <1576497901.28043.71.camel@mhfsdcap03> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: Yong Wu To: Chao Hao Date: Mon, 16 Dec 2019 20:05:01 +0800 In-Reply-To: <20191104115238.2394-2-chao.hao@mediatek.com> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: A9E5E71080A842134B9DA6CCB99242C492F30F72968470E68E8786C7F60B10FC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191216_040514_817489_A4C66FD1 X-CRM114-Status: GOOD ( 18.27 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > This patch adds description for MT6779 IOMMU. > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > use ARM Short-Descriptor translation format. > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > diagram about iommu, it don't focus on the part of smi_larb, so > I don't describe the smi_larb detailedly. > > EMI > | > -------------------------------------- > | | > MM_IOMMU APU_IOMMU > | | > SMI_COMMOM----------- APU_BUS > | | | > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > | | | > | | -------------- > | | | | | > Multimedia engine CCU VPU MDLA EMDA > > All the connections are hardware fixed, software can not adjust it. > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > but CCU is connected with smi_common directly, we can take them as larb12. > APU_IOMMU provides mapping for APU engine, we can take them larb13. > Larb12 and Larb13 are fake larbs. > > Signed-off-by: Chao Hao > --- > .../bindings/iommu/mediatek,iommu.txt | 2 + > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > 2 files changed, 219 insertions(+) > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > index ce59a505f5a4..c1ccd8582eb2 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > @@ -58,6 +58,7 @@ Required properties: > - compatible : must be one of the following string: > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > generation one m4u HW. > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > @@ -78,6 +79,7 @@ Required properties: > Specifies the mtk_m4u_id as defined in > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > dt-binding/memory/mt8173-larb-port.h for mt8173, and > dt-binding/memory/mt8183-larb-port.h for mt8183. > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > new file mode 100644 > index 000000000000..8b7f2d2446ea > --- /dev/null > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > @@ -0,0 +1,217 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Chao Hao > + */ > + > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > +#define _DTS_IOMMU_PORT_MT6779_H_ > + > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 > +#define M4U_LARB6_ID 6 > +#define M4U_LARB7_ID 7 > +#define M4U_LARB8_ID 8 > +#define M4U_LARB9_ID 9 > +#define M4U_LARB10_ID 10 > +#define M4U_LARB11_ID 11 > +#define M4U_LARB12_ID 12 > +#define M4U_LARB13_ID 13 > + > +/* larb0 */ > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > + > +/* larb1 */ > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > + > +/* larb2-VDEC */ > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > + > +/*larb3-VENC*/ Normally add space before and after the word. Like: /* larb3-VENC */ below are the same. > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > + > +/*larb4-dummy*/ > + > +/*larb5-IMG*/ [snip] > + > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > + > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) When do you need this UNKNOWN one? The other SoC doesn't have it. Please remove if it is unnecessary. > + > +#endif _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20BDAC43603 for ; Mon, 16 Dec 2019 12:05:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client 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v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=Clqeu4fvpnmS/ZiCD2V6ResMoNTOcGR52Rz6w11NnqM=; b=PMX8MTJgfJ5616HcoHjc1OONlBGM2MG0L83STOdHt6G/tN+7ZWgsZHO/CswbV8D+0YbpnL9Wmoz7Tx/vT0Y1G1ZPv+FYQoVrRFpNuEOJwM0GOzaEpUanbc9Q3dWUuikpYzqH3YjwKXYVFN6PRYqTFsGkARnt7tmkmox7L21PIJA=; X-UUID: d7c5a365f594495e9a09df0ca9ba57d9-20191216 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 448083721; Mon, 16 Dec 2019 04:05:06 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 16 Dec 2019 04:05:23 -0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 16 Dec 2019 20:04:02 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 16 Dec 2019 20:04:44 +0800 Message-ID: <1576497901.28043.71.camel@mhfsdcap03> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: Yong Wu To: Chao Hao Date: Mon, 16 Dec 2019 20:05:01 +0800 In-Reply-To: <20191104115238.2394-2-chao.hao@mediatek.com> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: A9E5E71080A842134B9DA6CCB99242C492F30F72968470E68E8786C7F60B10FC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191216_040514_817489_A4C66FD1 X-CRM114-Status: GOOD ( 18.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > This patch adds description for MT6779 IOMMU. > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > use ARM Short-Descriptor translation format. > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > diagram about iommu, it don't focus on the part of smi_larb, so > I don't describe the smi_larb detailedly. > > EMI > | > -------------------------------------- > | | > MM_IOMMU APU_IOMMU > | | > SMI_COMMOM----------- APU_BUS > | | | > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > | | | > | | -------------- > | | | | | > Multimedia engine CCU VPU MDLA EMDA > > All the connections are hardware fixed, software can not adjust it. > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > but CCU is connected with smi_common directly, we can take them as larb12. > APU_IOMMU provides mapping for APU engine, we can take them larb13. > Larb12 and Larb13 are fake larbs. > > Signed-off-by: Chao Hao > --- > .../bindings/iommu/mediatek,iommu.txt | 2 + > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > 2 files changed, 219 insertions(+) > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > index ce59a505f5a4..c1ccd8582eb2 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > @@ -58,6 +58,7 @@ Required properties: > - compatible : must be one of the following string: > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > generation one m4u HW. > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > @@ -78,6 +79,7 @@ Required properties: > Specifies the mtk_m4u_id as defined in > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > dt-binding/memory/mt8173-larb-port.h for mt8173, and > dt-binding/memory/mt8183-larb-port.h for mt8183. > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > new file mode 100644 > index 000000000000..8b7f2d2446ea > --- /dev/null > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > @@ -0,0 +1,217 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Chao Hao > + */ > + > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > +#define _DTS_IOMMU_PORT_MT6779_H_ > + > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 > +#define M4U_LARB6_ID 6 > +#define M4U_LARB7_ID 7 > +#define M4U_LARB8_ID 8 > +#define M4U_LARB9_ID 9 > +#define M4U_LARB10_ID 10 > +#define M4U_LARB11_ID 11 > +#define M4U_LARB12_ID 12 > +#define M4U_LARB13_ID 13 > + > +/* larb0 */ > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > + > +/* larb1 */ > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > + > +/* larb2-VDEC */ > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > + > +/*larb3-VENC*/ Normally add space before and after the word. Like: /* larb3-VENC */ below are the same. > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > + > +/*larb4-dummy*/ > + > +/*larb5-IMG*/ [snip] > + > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > + > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) When do you need this UNKNOWN one? The other SoC doesn't have it. Please remove if it is unnecessary. > + > +#endif _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C2EC43603 for ; Mon, 16 Dec 2019 12:05:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A461B20CC7 for ; Mon, 16 Dec 2019 12:05:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="nDJx9W5K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727385AbfLPMFJ (ORCPT ); Mon, 16 Dec 2019 07:05:09 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:44550 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727241AbfLPMFI (ORCPT ); Mon, 16 Dec 2019 07:05:08 -0500 X-UUID: 99596b7cd1b34e16ad389c4c76883501-20191216 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=Clqeu4fvpnmS/ZiCD2V6ResMoNTOcGR52Rz6w11NnqM=; b=nDJx9W5KJFahX1t1CcbTr7Djqfdsn5p3qRV2ehZQXEYnybufZMQXcAT/Oj81dnmmwA2ooS79lPFVO8zU0vyQpWzRzcmssPJtIXM8iCqxY1dK+KxMLFHsSRTfr4PFH4sx1CanzsQOM6iSgwbLOIR2V0mO7l3V3QqUfJ8CLX23g8k=; X-UUID: 99596b7cd1b34e16ad389c4c76883501-20191216 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 60780563; Mon, 16 Dec 2019 20:05:03 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 16 Dec 2019 20:04:02 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 16 Dec 2019 20:04:44 +0800 Message-ID: <1576497901.28043.71.camel@mhfsdcap03> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: Yong Wu To: Chao Hao CC: Joerg Roedel , Rob Herring , Matthias Brugger , , , , , , , Jun Yan , Cui Zhang , Guangming Cao , Anan Sun , Miles Chen Date: Mon, 16 Dec 2019 20:05:01 +0800 In-Reply-To: <20191104115238.2394-2-chao.hao@mediatek.com> References: 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