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<1576839713.20031.2.camel@mbjsdccf07> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: chao hao To: Yong Wu Date: Fri, 20 Dec 2019 19:01:53 +0800 In-Reply-To: <1576497901.28043.71.camel@mhfsdcap03> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> <1576497901.28043.71.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: CED2145DA5A5DB969C5A979274DE6004671E4E920E54B13366D6759B41D5A90B2000:8 X-MTK: N Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, 2019-12-16 at 20:05 +0800, Yong Wu wrote: > On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > > This patch adds description for MT6779 IOMMU. > > > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > > use ARM Short-Descriptor translation format. > > > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > > diagram about iommu, it don't focus on the part of smi_larb, so > > I don't describe the smi_larb detailedly. > > > > EMI > > | > > -------------------------------------- > > | | > > MM_IOMMU APU_IOMMU > > | | > > SMI_COMMOM----------- APU_BUS > > | | | > > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > > | | | > > | | -------------- > > | | | | | > > Multimedia engine CCU VPU MDLA EMDA > > > > All the connections are hardware fixed, software can not adjust it. > > > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > > but CCU is connected with smi_common directly, we can take them as larb12. > > APU_IOMMU provides mapping for APU engine, we can take them larb13. > > Larb12 and Larb13 are fake larbs. > > > > Signed-off-by: Chao Hao > > --- > > .../bindings/iommu/mediatek,iommu.txt | 2 + > > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > > 2 files changed, 219 insertions(+) > > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..c1ccd8582eb2 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -58,6 +58,7 @@ Required properties: > > - compatible : must be one of the following string: > > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > > generation one m4u HW. > > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > > @@ -78,6 +79,7 @@ Required properties: > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > dt-binding/memory/mt2712-larb-port.h for mt2712, > > + dt-binding/memory/mt6779-larb-port.h for mt6779, > > dt-binding/memory/mt8173-larb-port.h for mt8173, and > > dt-binding/memory/mt8183-larb-port.h for mt8183. > > > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > > new file mode 100644 > > index 000000000000..8b7f2d2446ea > > --- /dev/null > > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > > @@ -0,0 +1,217 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2019 MediaTek Inc. > > + * Author: Chao Hao > > + */ > > + > > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > > +#define _DTS_IOMMU_PORT_MT6779_H_ > > + > > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > > + > > +#define M4U_LARB0_ID 0 > > +#define M4U_LARB1_ID 1 > > +#define M4U_LARB2_ID 2 > > +#define M4U_LARB3_ID 3 > > +#define M4U_LARB4_ID 4 > > +#define M4U_LARB5_ID 5 > > +#define M4U_LARB6_ID 6 > > +#define M4U_LARB7_ID 7 > > +#define M4U_LARB8_ID 8 > > +#define M4U_LARB9_ID 9 > > +#define M4U_LARB10_ID 10 > > +#define M4U_LARB11_ID 11 > > +#define M4U_LARB12_ID 12 > > +#define M4U_LARB13_ID 13 > > + > > +/* larb0 */ > > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > > + > > +/* larb1 */ > > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > > + > > +/* larb2-VDEC */ > > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > > + > > +/*larb3-VENC*/ > > Normally add space before and after the word. Like: /* larb3-VENC */ > > below are the same. > > > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > > + > > +/*larb4-dummy*/ > > + > > +/*larb5-IMG*/ > > [snip] > > > + > > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > > + > > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) > > When do you need this UNKNOWN one? The other SoC doesn't have it. Please > remove if it is unnecessary. > ok, I will fix it in next version, thanks > > + > > +#endif > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D686C43603 for ; Fri, 20 Dec 2019 11:13:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher 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(172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Dec 2019 19:02:38 +0800 Received: from [10.15.20.246] (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Dec 2019 19:01:43 +0800 Message-ID: <1576839713.20031.2.camel@mbjsdccf07> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: chao hao To: Yong Wu Date: Fri, 20 Dec 2019 19:01:53 +0800 In-Reply-To: <1576497901.28043.71.camel@mhfsdcap03> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> <1576497901.28043.71.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: CED2145DA5A5DB969C5A979274DE6004671E4E920E54B13366D6759B41D5A90B2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191220_031250_298232_3B5C9C96 X-CRM114-Status: GOOD ( 20.46 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2019-12-16 at 20:05 +0800, Yong Wu wrote: > On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > > This patch adds description for MT6779 IOMMU. > > > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > > use ARM Short-Descriptor translation format. > > > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > > diagram about iommu, it don't focus on the part of smi_larb, so > > I don't describe the smi_larb detailedly. > > > > EMI > > | > > -------------------------------------- > > | | > > MM_IOMMU APU_IOMMU > > | | > > SMI_COMMOM----------- APU_BUS > > | | | > > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > > | | | > > | | -------------- > > | | | | | > > Multimedia engine CCU VPU MDLA EMDA > > > > All the connections are hardware fixed, software can not adjust it. > > > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > > but CCU is connected with smi_common directly, we can take them as larb12. > > APU_IOMMU provides mapping for APU engine, we can take them larb13. > > Larb12 and Larb13 are fake larbs. > > > > Signed-off-by: Chao Hao > > --- > > .../bindings/iommu/mediatek,iommu.txt | 2 + > > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > > 2 files changed, 219 insertions(+) > > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..c1ccd8582eb2 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -58,6 +58,7 @@ Required properties: > > - compatible : must be one of the following string: > > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > > generation one m4u HW. > > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > > @@ -78,6 +79,7 @@ Required properties: > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > dt-binding/memory/mt2712-larb-port.h for mt2712, > > + dt-binding/memory/mt6779-larb-port.h for mt6779, > > dt-binding/memory/mt8173-larb-port.h for mt8173, and > > dt-binding/memory/mt8183-larb-port.h for mt8183. > > > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > > new file mode 100644 > > index 000000000000..8b7f2d2446ea > > --- /dev/null > > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > > @@ -0,0 +1,217 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2019 MediaTek Inc. > > + * Author: Chao Hao > > + */ > > + > > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > > +#define _DTS_IOMMU_PORT_MT6779_H_ > > + > > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > > + > > +#define M4U_LARB0_ID 0 > > +#define M4U_LARB1_ID 1 > > +#define M4U_LARB2_ID 2 > > +#define M4U_LARB3_ID 3 > > +#define M4U_LARB4_ID 4 > > +#define M4U_LARB5_ID 5 > > +#define M4U_LARB6_ID 6 > > +#define M4U_LARB7_ID 7 > > +#define M4U_LARB8_ID 8 > > +#define M4U_LARB9_ID 9 > > +#define M4U_LARB10_ID 10 > > +#define M4U_LARB11_ID 11 > > +#define M4U_LARB12_ID 12 > > +#define M4U_LARB13_ID 13 > > + > > +/* larb0 */ > > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > > + > > +/* larb1 */ > > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > > + > > +/* larb2-VDEC */ > > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > > + > > +/*larb3-VENC*/ > > Normally add space before and after the word. Like: /* larb3-VENC */ > > below are the same. > > > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > > + > > +/*larb4-dummy*/ > > + > > +/*larb5-IMG*/ > > [snip] > > > + > > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > > + > > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) > > When do you need this UNKNOWN one? The other SoC doesn't have it. Please > remove if it is unnecessary. > ok, I will fix it in next version, thanks > > + > > +#endif > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1C98C2D0C0 for ; Fri, 20 Dec 2019 11:13:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher 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(172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Dec 2019 19:02:38 +0800 Received: from [10.15.20.246] (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Dec 2019 19:01:43 +0800 Message-ID: <1576839713.20031.2.camel@mbjsdccf07> Subject: Re: [RESEND,PATCH 01/13] dt-bindings: mediatek: Add bindings for MT6779 From: chao hao To: Yong Wu Date: Fri, 20 Dec 2019 19:01:53 +0800 In-Reply-To: <1576497901.28043.71.camel@mhfsdcap03> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> <1576497901.28043.71.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: CED2145DA5A5DB969C5A979274DE6004671E4E920E54B13366D6759B41D5A90B2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191220_031250_298232_3B5C9C96 X-CRM114-Status: GOOD ( 20.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anan Sun , devicetree@vger.kernel.org, Cui Zhang , Jun Yan , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Miles Chen , Matthias Brugger , linux-arm-kernel@lists.infradead.org, Guangming Cao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2019-12-16 at 20:05 +0800, Yong Wu wrote: > On Mon, 2019-11-04 at 19:52 +0800, Chao Hao wrote: > > This patch adds description for MT6779 IOMMU. > > > > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which > > use ARM Short-Descriptor translation format. > > > > The MT6779 IOMMU hardware diagram is as below, it is only a brief > > diagram about iommu, it don't focus on the part of smi_larb, so > > I don't describe the smi_larb detailedly. > > > > EMI > > | > > -------------------------------------- > > | | > > MM_IOMMU APU_IOMMU > > | | > > SMI_COMMOM----------- APU_BUS > > | | | > > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE) > > | | | > > | | -------------- > > | | | | | > > Multimedia engine CCU VPU MDLA EMDA > > > > All the connections are hardware fixed, software can not adjust it. > > > > From the diagram above, MM_IOMMU provides mapping for multimedia engine, > > but CCU is connected with smi_common directly, we can take them as larb12. > > APU_IOMMU provides mapping for APU engine, we can take them larb13. > > Larb12 and Larb13 are fake larbs. > > > > Signed-off-by: Chao Hao > > --- > > .../bindings/iommu/mediatek,iommu.txt | 2 + > > include/dt-bindings/memory/mt6779-larb-port.h | 217 ++++++++++++++++++ > > 2 files changed, 219 insertions(+) > > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..c1ccd8582eb2 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -58,6 +58,7 @@ Required properties: > > - compatible : must be one of the following string: > > "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > > "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > > + "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > > generation one m4u HW. > > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > > @@ -78,6 +79,7 @@ Required properties: > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > dt-binding/memory/mt2712-larb-port.h for mt2712, > > + dt-binding/memory/mt6779-larb-port.h for mt6779, > > dt-binding/memory/mt8173-larb-port.h for mt8173, and > > dt-binding/memory/mt8183-larb-port.h for mt8183. > > > > diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h > > new file mode 100644 > > index 000000000000..8b7f2d2446ea > > --- /dev/null > > +++ b/include/dt-bindings/memory/mt6779-larb-port.h > > @@ -0,0 +1,217 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2019 MediaTek Inc. > > + * Author: Chao Hao > > + */ > > + > > +#ifndef _DTS_IOMMU_PORT_MT6779_H_ > > +#define _DTS_IOMMU_PORT_MT6779_H_ > > + > > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > > + > > +#define M4U_LARB0_ID 0 > > +#define M4U_LARB1_ID 1 > > +#define M4U_LARB2_ID 2 > > +#define M4U_LARB3_ID 3 > > +#define M4U_LARB4_ID 4 > > +#define M4U_LARB5_ID 5 > > +#define M4U_LARB6_ID 6 > > +#define M4U_LARB7_ID 7 > > +#define M4U_LARB8_ID 8 > > +#define M4U_LARB9_ID 9 > > +#define M4U_LARB10_ID 10 > > +#define M4U_LARB11_ID 11 > > +#define M4U_LARB12_ID 12 > > +#define M4U_LARB13_ID 13 > > + > > +/* larb0 */ > > +#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) > > +#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) > > +#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) > > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) > > +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) > > +#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) > > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) > > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) > > +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) > > + > > +/* larb1 */ > > +#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) > > +#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) > > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) > > +#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) > > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) > > +#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) > > +#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) > > +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) > > +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) > > +#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) > > +#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) > > +#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) > > +#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) > > +#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) > > + > > +/* larb2-VDEC */ > > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > > +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > > +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) > > +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) > > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) > > +#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) > > +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) > > + > > +/*larb3-VENC*/ > > Normally add space before and after the word. Like: /* larb3-VENC */ > > below are the same. > > > +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) > > +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) > > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) > > +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) > > +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) > > +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) > > +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) > > +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) > > +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) > > +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) > > +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) > > +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) > > +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) > > +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) > > +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) > > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) > > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) > > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) > > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) > > + > > +/*larb4-dummy*/ > > + > > +/*larb5-IMG*/ > > [snip] > > > + > > +#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0) > > +#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1) > > +#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2) > > + > > +#define M4U_PORT_UNKNOWN (M4U_PORT_EDMA + 1) > > When do you need this UNKNOWN one? The other SoC doesn't have it. Please > remove if it is unnecessary. > ok, I will fix it in next version, thanks > > + > > +#endif > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73E3AC43603 for ; Fri, 20 Dec 2019 11:02:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 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Brugger , , , , , , , Jun Yan , Cui Zhang , Guangming Cao , Anan Sun , Miles Chen Date: Fri, 20 Dec 2019 19:01:53 +0800 In-Reply-To: <1576497901.28043.71.camel@mhfsdcap03> References: <20191104115238.2394-1-chao.hao@mediatek.com> <20191104115238.2394-2-chao.hao@mediatek.com> <1576497901.28043.71.camel@mhfsdcap03> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: CED2145DA5A5DB969C5A979274DE6004671E4E920E54B13366D6759B41D5A90B2000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gTW9uLCAyMDE5LTEyLTE2IGF0IDIwOjA1ICswODAwLCBZb25nIFd1IHdyb3RlOg0KPiBPbiBN b24sIDIwMTktMTEtMDQgYXQgMTk6NTIgKzA4MDAsIENoYW8gSGFvIHdyb3RlOg0KPiA+IFRoaXMg cGF0Y2ggYWRkcyBkZXNjcmlwdGlvbiBmb3IgTVQ2Nzc5IElPTU1VLg0KPiA+IA0KPiA+IE1UNjc3 OSBoYXMgdHdvIGlvbW11cywgdGhleSBhcmUgTU1fSU9NTVUgYW5kIEFQVV9JT01NVSB3aGljaA0K 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