From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EC83C352A3 for ; Tue, 11 Feb 2020 07:44:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 610B0206D7 for ; Tue, 11 Feb 2020 07:44:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uRYMkfjU"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FTelS1W2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 610B0206D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+ypq3ZqvQs17tJEolQGqy5joic5ZZWx+393b4OG631E=; b=uRYMkfjUcnLFIE 1gztrzHLD9neO/nslir8N/IlQnkTCdLtYMsvoT82znRlqHTJIFQgLGElW6DQxVogNdZH2W2GmtXkT oy8UW5Cv5pNizpiGnyXQ6hUdaKDhmlOJ9HU+/deyNOlCTgYN4KhWdHGMc6HKgxRV8K7JobESLNkXA vorc5HXKCslYzYNQfI+gRdoYle07/6s6tkJcSRB6F9SGOUU9TCdsldRbKD4xIb/eU1n2d+LESKUwG 6gDMvOwrXvRoWFxg9Jpg3hOSE/zY1m5aknC6QPaSYjzF3yuoQnBjrUMya9/iYvNxGBevW/ixsqS73 rJniHiXlQZhyDs1aUmHA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j1QDM-0007lv-QE; Tue, 11 Feb 2020 07:44:12 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j1QDK-0007lT-Kh; Tue, 11 Feb 2020 07:44:12 +0000 X-UUID: 9cb0417af0364f938a6ae87a9aab0423-20200210 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=WF9g4PEqWlupM4phER8lYwnueeO3pdMwX2AAwBSYAFg=; b=FTelS1W2ak4xC5AmE2V0wcsa9Rda4LaM3ywcKXJdrshuDKsgoWpUffDK8ongubWop0DZZD89r41mPLBabbicUdGz1XTyBesSGr6AGVuvLGJDQFCuq/5Hr0x6pi+xAtPDBPARppiz6WNEQmlpjI2n/Fc7u+HsodFyZXy+e03yK3o=; X-UUID: 9cb0417af0364f938a6ae87a9aab0423-20200210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 730199669; Mon, 10 Feb 2020 23:44:02 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Feb 2020 23:36:15 -0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 11 Feb 2020 15:35:03 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 11 Feb 2020 15:36:19 +0800 Message-ID: <1581406566.14120.46.camel@mtksdaap41> Subject: Re: [PATCH v6 1/3] dt-bindings: soc: add mtk svs dt-bindings From: Roger Lu To: Rob Herring , Nicolas Boichat Date: Tue, 11 Feb 2020 15:36:06 +0800 In-Reply-To: References: <20200107070154.1574-1-roger.lu@mediatek.com> <20200107070154.1574-2-roger.lu@mediatek.com> <20200108203829.GA18987@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200210_234410_691340_30C59F27 X-CRM114-Status: GOOD ( 31.90 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nicolas Boichat , Angus Lin =?UTF-8?Q?=28=E6=9E=97=E7=91=9B=E8=B1=AA=29?= , Kevin Hilman , Stephen Boyd , jamesjj.liao@mediatek.com, "open list:THERMAL" , lkml , HenryC Chen =?UTF-8?Q?=28=E9=99=B3=E5=BB=BA=E8=B1=AA=29?= , YT Lee =?UTF-8?Q?=28=E6=9D=8E=E4=BB=B0=E5=93=B2=29?= , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , Devicetree List , "moderated list:ARM/Mediatek SoC support" , Xiaoqing Liu =?UTF-8?Q?=28=E5=88=98=E6=99=93=E5=BA=86=29?= , Charles Yang =?UTF-8?Q?=28=E6=A5=8A=E4=BA=8E=E9=80=B2=29?= , Matthias Brugger , Nishanth Menon , linux-arm Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Rob & Nicolas, Sorry for the late reply. On Mon, 2020-01-13 at 23:50 +0800, Rob Herring wrote: > On Mon, Jan 13, 2020 at 12:44 AM Nicolas Boichat wrote: > > > > On Thu, Jan 9, 2020 at 4:38 AM Rob Herring wrote: > > > > > > On Tue, Jan 07, 2020 at 03:01:52PM +0800, Roger Lu wrote: > > > > Document the binding for enabling mtk svs on MediaTek SoC. > > > > > > > > Signed-off-by: Roger Lu > > > > --- > > > > .../devicetree/bindings/power/mtk-svs.txt | 76 +++++++++++++++++++ > > > > 1 file changed, 76 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt > > > > > > > > diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt > > > > new file mode 100644 > > > > index 000000000000..9a3e81b9e1d2 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt > > > > @@ -0,0 +1,76 @@ > > > > +* Mediatek Smart Voltage Scaling (MTK SVS) > > > > + > > > > +This describes the device tree binding for the MTK SVS controller (bank) > > > > +which helps provide the optimized CPU/GPU/CCI voltages. This device also > > > > +needs thermal data to calculate thermal slope for accurately compensate > > > > +the voltages when temperature change. > > > > + > > > > +Required properties: > > > > +- compatible: > > > > + - "mediatek,mt8183-svs" : For MT8183 family of SoCs > > > > +- reg: Address range of the MTK SVS controller. > > > > +- interrupts: IRQ for the MTK SVS controller. > > > > +- clocks, clock-names: Clocks needed for the svs hardware. required > > > > + clocks are: > > > > + "main": Main clock for svs controller to work. > > > > +- nvmem-cells: Phandle to the calibration data provided by a nvmem device. > > > > +- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data" > > > > + > > > > +Subnodes: > > > > +- svs-cpu-little: SVS bank device node of little CPU > > > > + compatible: "mediatek,mt8183-svs-cpu-little" > > > > + operating-points-v2: OPP table hooked by SVS little CPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcpu-little-supply: PMIC buck of little CPU > > > > +- svs-cpu-big: SVS bank device node of big CPU > > > > + compatible: "mediatek,mt8183-svs-cpu-big" > > > > + operating-points-v2: OPP table hooked by SVS big CPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcpu-big-supply: PMIC buck of big CPU > > > > +- svs-cci: SVS bank device node of CCI > > > > + compatible: "mediatek,mt8183-svs-cci" > > > > + operating-points-v2: OPP table hooked by SVS CCI bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcci-supply: PMIC buck of CCI > > > > +- svs-gpu: SVS bank device node of GPU > > > > + compatible: "mediatek,mt8183-svs-gpu" > > > > + operating-points-v2: OPP table hooked by SVS GPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vgpu-supply: PMIC buck of GPU > > > > + > > > > +Example: > > > > + > > > > + svs: svs@1100b000 { > > > > + compatible = "mediatek,mt8183-svs"; > > > > + reg = <0 0x1100b000 0 0x1000>; > > > > + interrupts = ; > > > > + clocks = <&infracfg CLK_INFRA_THERM>; > > > > + clock-names = "main_clk"; > > > > + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; > > > > + nvmem-cell-names = "svs-calibration-data", "calibration-data"; > > > > + > > > > + svs_cpu_little: svs-cpu-little { > > > > + compatible = "mediatek,mt8183-svs-cpu-little"; > > > > + operating-points-v2 = <&cluster0_opp>; > > > > + vcpu-little-supply = <&mt6358_vproc12_reg>; > > > > + }; > > > > > > I don't think this is a good binding. This information already exists > > > elsewhere in the DT, so your driver should just look in those nodes. > > > For example the regulator can be in the cpu nodes or the OPP table > > > itself. > > > > Roger, if that helps, without changing any other binding, on 8183, > > basically you could have: > > - svs-cpu-little: Add a handle to &cpu0 and get the regulator/opp > > table from it. > > - svs-cpu-big: Handle to &cpu4 > > Why do you need those? Use the compatible of the cpus to determine big > and little cores. Or there's the cpu capacity property that could be > used instead. > > > - svs-cci: Handle to &cci > > Is there more than 1 CCI? Just retrieve the node by the compatible. > There's no need to have nodes that simply serve as a collection of > data for some driver. > > > - svs-gpu: Handle to &gpu (BTW, it is expected that SVS would only > > apply to vgpu/mali regulator, and not vsram regulator?) svs-gpu depends on vgpu power on for init (don't care vgpu_sram). After svs-gpu init is done, it doesn't need vgpu power on anymore. (vgpu can be turned off) Please allows me to introduce more about what svs-gpu device needs. 1. It needs gpu opp table from "gpu node" and gpu_core2 power-domains from "gpu_core2 node". When svs-gpu has those resources, it turns on gpu_core2 power-domain for svs-gpu-hw to have power (for calculating) and svs-gpu-sw will update gpu opp table voltages' part. 2. Therefore, if I retrieve gpu-related node from phandle or compatible, it means svs-gpu device in driver needs to attach two different gpu nodes for attaining gpu opp table and gpu_core2 power-domains. I think this architecture of svs-gpu confuses maintainer why it attaches two different nodes instead of having a device to describe what it needs. 3. Is it acceptable to have a Linux device attaching two different nodes? If yes, could you guide us some APIs for one device to attach two nodes? I don't know how to implement it. Thanks. > > > > I'm not too sure how we'd fetch the right regulator name, however (for > > the first 3 the name is "proc", for the last one it's "mali"), maybe > > add a regulator-name list in the DT? > > To put this another way, write an SoC specific driver that understands > to some extent what exists in the SoC (and DT). I doubt something like > this is going to be generic across more than a few SoCs at most. > > Rob _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8754AC352A3 for ; Tue, 11 Feb 2020 07:36:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 503C3206ED for ; Tue, 11 Feb 2020 07:36:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="S7DEsO+f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727579AbgBKHgN (ORCPT ); Tue, 11 Feb 2020 02:36:13 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:12453 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727467AbgBKHgN (ORCPT ); Tue, 11 Feb 2020 02:36:13 -0500 X-UUID: b6208217a42c4e998da28eb768635179-20200211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=WF9g4PEqWlupM4phER8lYwnueeO3pdMwX2AAwBSYAFg=; b=S7DEsO+fud6t7SGmRLazQtLkbpjWISULAdOGs8anuFOJ6bsB2qhicZ9+CHFX0BPk0P0sbB11BueuJFQ+Rel9UeFbyINcxYRxMKZ4m9gACpJqBj0CZmeoi7YF/vnZRVWQHZw/fKnPOpy6kIiblVk3Od23s0Ptu/jyusn51tog1BE=; X-UUID: b6208217a42c4e998da28eb768635179-20200211 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1952218471; Tue, 11 Feb 2020 15:36:08 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 11 Feb 2020 15:35:03 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 11 Feb 2020 15:36:19 +0800 Message-ID: <1581406566.14120.46.camel@mtksdaap41> Subject: Re: [PATCH v6 1/3] dt-bindings: soc: add mtk svs dt-bindings From: Roger Lu To: Rob Herring , Nicolas Boichat CC: Kevin Hilman , Nicolas Boichat , Stephen Boyd , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , HenryC Chen =?UTF-8?Q?=28=E9=99=B3=E5=BB=BA=E8=B1=AA=29?= , YT Lee =?UTF-8?Q?=28=E6=9D=8E=E4=BB=B0=E5=93=B2=29?= , Xiaoqing Liu =?UTF-8?Q?=28=E5=88=98=E6=99=93=E5=BA=86=29?= , Charles Yang =?UTF-8?Q?=28=E6=A5=8A=E4=BA=8E=E9=80=B2=29?= , Angus Lin =?UTF-8?Q?=28=E6=9E=97=E7=91=9B=E8=B1=AA=29?= , Mark Rutland , "Matthias Brugger" , Nishanth Menon , "Devicetree List" , linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , lkml , "open list:THERMAL" , Date: Tue, 11 Feb 2020 15:36:06 +0800 In-Reply-To: References: <20200107070154.1574-1-roger.lu@mediatek.com> <20200107070154.1574-2-roger.lu@mediatek.com> <20200108203829.GA18987@bogus> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org SGkgUm9iICYgTmljb2xhcywNCg0KU29ycnkgZm9yIHRoZSBsYXRlIHJlcGx5Lg0KDQpPbiBNb24s IDIwMjAtMDEtMTMgYXQgMjM6NTAgKzA4MDAsIFJvYiBIZXJyaW5nIHdyb3RlOg0KPiBPbiBNb24s IEphbiAxMywgMjAyMCBhdCAxMjo0NCBBTSBOaWNvbGFzIEJvaWNoYXQgPGRyaW5rY2F0QGNocm9t aXVtLm9yZz4gd3JvdGU6DQo+ID4NCj4gPiBPbiBUaHUsIEphbiA5LCAyMDIwIGF0IDQ6MzggQU0g Um9iIEhlcnJpbmcgPHJvYmhAa2VybmVsLm9yZz4gd3JvdGU6DQo+ID4gPg0KPiA+ID4gT24gVHVl LCBKYW4gMDcsIDIwMjAgYXQgMDM6MDE6NTJQTSArMDgwMCwgUm9nZXIgTHUgd3JvdGU6DQo+ID4g PiA+IERvY3VtZW50IHRoZSBiaW5kaW5nIGZvciBlbmFibGluZyBtdGsgc3ZzIG9uIE1lZGlhVGVr IFNvQy4NCj4gPiA+ID4NCj4gPiA+ID4gU2lnbmVkLW9mZi1ieTogUm9nZXIgTHUgPHJvZ2VyLmx1 QG1lZGlhdGVrLmNvbT4NCj4gPiA+ID4gLS0tDQo+ID4gPiA+ICAuLi4vZGV2aWNldHJlZS9iaW5k aW5ncy9wb3dlci9tdGstc3ZzLnR4dCAgICAgfCA3NiArKysrKysrKysrKysrKysrKysrDQo+ID4g PiA+ICAxIGZpbGUgY2hhbmdlZCwgNzYgaW5zZXJ0aW9ucygrKQ0KPiA+ID4gPiAgY3JlYXRlIG1v ZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9wb3dlci9tdGstc3Zz LnR4dA0KPiA+ID4gPg0KPiA+ID4gPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0 cmVlL2JpbmRpbmdzL3Bvd2VyL210ay1zdnMudHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVl L2JpbmRpbmdzL3Bvd2VyL210ay1zdnMudHh0DQo+ID4gPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0 DQo+ID4gPiA+IGluZGV4IDAwMDAwMDAwMDAwMC4uOWEzZTgxYjllMWQyDQo+ID4gPiA+IC0tLSAv ZGV2L251bGwNCj4gPiA+ID4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdz L3Bvd2VyL210ay1zdnMudHh0DQo+ID4gPiA+IEBAIC0wLDAgKzEsNzYgQEANCj4gPiA+ID4gKyog TWVkaWF0ZWsgU21hcnQgVm9sdGFnZSBTY2FsaW5nIChNVEsgU1ZTKQ0KPiA+ID4gPiArDQo+ID4g PiA+ICtUaGlzIGRlc2NyaWJlcyB0aGUgZGV2aWNlIHRyZWUgYmluZGluZyBmb3IgdGhlIE1USyBT VlMgY29udHJvbGxlciAoYmFuaykNCj4gPiA+ID4gK3doaWNoIGhlbHBzIHByb3ZpZGUgdGhlIG9w dGltaXplZCBDUFUvR1BVL0NDSSB2b2x0YWdlcy4gVGhpcyBkZXZpY2UgYWxzbw0KPiA+ID4gPiAr bmVlZHMgdGhlcm1hbCBkYXRhIHRvIGNhbGN1bGF0ZSB0aGVybWFsIHNsb3BlIGZvciBhY2N1cmF0 ZWx5IGNvbXBlbnNhdGUNCj4gPiA+ID4gK3RoZSB2b2x0YWdlcyB3aGVuIHRlbXBlcmF0dXJlIGNo YW5nZS4NCj4gPiA+ID4gKw0KPiA+ID4gPiArUmVxdWlyZWQgcHJvcGVydGllczoNCj4gPiA+ID4g Ky0gY29tcGF0aWJsZToNCj4gPiA+ID4gKyAgLSAibWVkaWF0ZWssbXQ4MTgzLXN2cyIgOiBGb3Ig TVQ4MTgzIGZhbWlseSBvZiBTb0NzDQo+ID4gPiA+ICstIHJlZzogQWRkcmVzcyByYW5nZSBvZiB0 aGUgTVRLIFNWUyBjb250cm9sbGVyLg0KPiA+ID4gPiArLSBpbnRlcnJ1cHRzOiBJUlEgZm9yIHRo ZSBNVEsgU1ZTIGNvbnRyb2xsZXIuDQo+ID4gPiA+ICstIGNsb2NrcywgY2xvY2stbmFtZXM6IENs b2NrcyBuZWVkZWQgZm9yIHRoZSBzdnMgaGFyZHdhcmUuIHJlcXVpcmVkDQo+ID4gPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgIGNsb2NrcyBhcmU6DQo+ID4gPiA+ICsgICAgICAgICAgICAgICAg ICAgICJtYWluIjogTWFpbiBjbG9jayBmb3Igc3ZzIGNvbnRyb2xsZXIgdG8gd29yay4NCj4gPiA+ ID4gKy0gbnZtZW0tY2VsbHM6IFBoYW5kbGUgdG8gdGhlIGNhbGlicmF0aW9uIGRhdGEgcHJvdmlk ZWQgYnkgYSBudm1lbSBkZXZpY2UuDQo+ID4gPiA+ICstIG52bWVtLWNlbGwtbmFtZXM6IFNob3Vs ZCBiZSAic3ZzLWNhbGlicmF0aW9uLWRhdGEiIGFuZCAiY2FsaWJyYXRpb24tZGF0YSINCj4gPiA+ ID4gKw0KPiA+ID4gPiArU3Vibm9kZXM6DQo+ID4gPiA+ICstIHN2cy1jcHUtbGl0dGxlOiBTVlMg YmFuayBkZXZpY2Ugbm9kZSBvZiBsaXR0bGUgQ1BVDQo+ID4gPiA+ICsgIGNvbXBhdGlibGU6ICJt ZWRpYXRlayxtdDgxODMtc3ZzLWNwdS1saXR0bGUiDQo+ID4gPiA+ICsgIG9wZXJhdGluZy1wb2lu dHMtdjI6IE9QUCB0YWJsZSBob29rZWQgYnkgU1ZTIGxpdHRsZSBDUFUgYmFuay4NCj4gPiA+ID4g KyAgICAgICAgICAgICAgICAgICAgU1ZTIHdpbGwgb3B0aW16ZSB0aGlzIE9QUCB0YWJsZSB2b2x0 YWdlIHBhcnQuDQo+ID4gPiA+ICsgIHZjcHUtbGl0dGxlLXN1cHBseTogUE1JQyBidWNrIG9mIGxp dHRsZSBDUFUNCj4gPiA+ID4gKy0gc3ZzLWNwdS1iaWc6IFNWUyBiYW5rIGRldmljZSBub2RlIG9m IGJpZyBDUFUNCj4gPiA+ID4gKyAgY29tcGF0aWJsZTogIm1lZGlhdGVrLG10ODE4My1zdnMtY3B1 LWJpZyINCj4gPiA+ID4gKyAgb3BlcmF0aW5nLXBvaW50cy12MjogT1BQIHRhYmxlIGhvb2tlZCBi eSBTVlMgYmlnIENQVSBiYW5rLg0KPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICBTVlMgd2ls bCBvcHRpbXplIHRoaXMgT1BQIHRhYmxlIHZvbHRhZ2UgcGFydC4NCj4gPiA+ID4gKyAgdmNwdS1i aWctc3VwcGx5OiBQTUlDIGJ1Y2sgb2YgYmlnIENQVQ0KPiA+ID4gPiArLSBzdnMtY2NpOiBTVlMg YmFuayBkZXZpY2Ugbm9kZSBvZiBDQ0kNCj4gPiA+ID4gKyAgY29tcGF0aWJsZTogIm1lZGlhdGVr LG10ODE4My1zdnMtY2NpIg0KPiA+ID4gPiArICBvcGVyYXRpbmctcG9pbnRzLXYyOiBPUFAgdGFi bGUgaG9va2VkIGJ5IFNWUyBDQ0kgYmFuay4NCj4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAg U1ZTIHdpbGwgb3B0aW16ZSB0aGlzIE9QUCB0YWJsZSB2b2x0YWdlIHBhcnQuDQo+ID4gPiA+ICsg IHZjY2ktc3VwcGx5OiBQTUlDIGJ1Y2sgb2YgQ0NJDQo+ID4gPiA+ICstIHN2cy1ncHU6IFNWUyBi YW5rIGRldmljZSBub2RlIG9mIEdQVQ0KPiA+ID4gPiArICBjb21wYXRpYmxlOiAibWVkaWF0ZWss bXQ4MTgzLXN2cy1ncHUiDQo+ID4gPiA+ICsgIG9wZXJhdGluZy1wb2ludHMtdjI6IE9QUCB0YWJs ZSBob29rZWQgYnkgU1ZTIEdQVSBiYW5rLg0KPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICBT VlMgd2lsbCBvcHRpbXplIHRoaXMgT1BQIHRhYmxlIHZvbHRhZ2UgcGFydC4NCj4gPiA+ID4gKyAg dmdwdS1zdXBwbHk6IFBNSUMgYnVjayBvZiBHUFUNCj4gPiA+ID4gKw0KPiA+ID4gPiArRXhhbXBs ZToNCj4gPiA+ID4gKw0KPiA+ID4gPiArICAgICBzdnM6IHN2c0AxMTAwYjAwMCB7DQo+ID4gPiA+ ICsgICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxODMtc3ZzIjsNCj4gPiA+ ID4gKyAgICAgICAgICAgICByZWcgPSA8MCAweDExMDBiMDAwIDAgMHgxMDAwPjsNCj4gPiA+ID4g KyAgICAgICAgICAgICBpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMTI3IElSUV9UWVBFX0xFVkVMX0xP Vz47DQo+ID4gPiA+ICsgICAgICAgICAgICAgY2xvY2tzID0gPCZpbmZyYWNmZyBDTEtfSU5GUkFf VEhFUk0+Ow0KPiA+ID4gPiArICAgICAgICAgICAgIGNsb2NrLW5hbWVzID0gIm1haW5fY2xrIjsN Cj4gPiA+ID4gKyAgICAgICAgICAgICBudm1lbS1jZWxscyA9IDwmc3ZzX2NhbGlicmF0aW9uPiwg PCZ0aGVybWFsX2NhbGlicmF0aW9uPjsNCj4gPiA+ID4gKyAgICAgICAgICAgICBudm1lbS1jZWxs LW5hbWVzID0gInN2cy1jYWxpYnJhdGlvbi1kYXRhIiwgImNhbGlicmF0aW9uLWRhdGEiOw0KPiA+ ID4gPiArDQo+ID4gPiA+ICsgICAgICAgICAgICAgc3ZzX2NwdV9saXR0bGU6IHN2cy1jcHUtbGl0 dGxlIHsNCj4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAibWVkaWF0 ZWssbXQ4MTgzLXN2cy1jcHUtbGl0dGxlIjsNCj4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAg IG9wZXJhdGluZy1wb2ludHMtdjIgPSA8JmNsdXN0ZXIwX29wcD47DQo+ID4gPiA+ICsgICAgICAg ICAgICAgICAgICAgICB2Y3B1LWxpdHRsZS1zdXBwbHkgPSA8Jm10NjM1OF92cHJvYzEyX3JlZz47 DQo+ID4gPiA+ICsgICAgICAgICAgICAgfTsNCj4gPiA+DQo+ID4gPiBJIGRvbid0IHRoaW5rIHRo aXMgaXMgYSBnb29kIGJpbmRpbmcuIFRoaXMgaW5mb3JtYXRpb24gYWxyZWFkeSBleGlzdHMNCj4g PiA+IGVsc2V3aGVyZSBpbiB0aGUgRFQsIHNvIHlvdXIgZHJpdmVyIHNob3VsZCBqdXN0IGxvb2sg aW4gdGhvc2Ugbm9kZXMuDQo+ID4gPiBGb3IgZXhhbXBsZSB0aGUgcmVndWxhdG9yIGNhbiBiZSBp biB0aGUgY3B1IG5vZGVzIG9yIHRoZSBPUFAgdGFibGUNCj4gPiA+IGl0c2VsZi4NCj4gPg0KPiA+ IFJvZ2VyLCBpZiB0aGF0IGhlbHBzLCB3aXRob3V0IGNoYW5naW5nIGFueSBvdGhlciBiaW5kaW5n LCBvbiA4MTgzLA0KPiA+IGJhc2ljYWxseSB5b3UgY291bGQgaGF2ZToNCj4gPiAgLSBzdnMtY3B1 LWxpdHRsZTogQWRkIGEgaGFuZGxlIHRvICZjcHUwIGFuZCBnZXQgdGhlIHJlZ3VsYXRvci9vcHAN Cj4gPiB0YWJsZSBmcm9tIGl0Lg0KPiA+ICAtIHN2cy1jcHUtYmlnOiBIYW5kbGUgdG8gJmNwdTQN Cj4gDQo+IFdoeSBkbyB5b3UgbmVlZCB0aG9zZT8gVXNlIHRoZSBjb21wYXRpYmxlIG9mIHRoZSBj cHVzIHRvIGRldGVybWluZSBiaWcNCj4gYW5kIGxpdHRsZSBjb3Jlcy4gT3IgdGhlcmUncyB0aGUg Y3B1IGNhcGFjaXR5IHByb3BlcnR5IHRoYXQgY291bGQgYmUNCj4gdXNlZCBpbnN0ZWFkLg0KPiAN Cj4gPiAgLSBzdnMtY2NpOiBIYW5kbGUgdG8gJmNjaQ0KPiANCj4gSXMgdGhlcmUgbW9yZSB0aGFu IDEgQ0NJPyBKdXN0IHJldHJpZXZlIHRoZSBub2RlIGJ5IHRoZSBjb21wYXRpYmxlLg0KPiBUaGVy ZSdzIG5vIG5lZWQgdG8gaGF2ZSBub2RlcyB0aGF0IHNpbXBseSBzZXJ2ZSBhcyBhIGNvbGxlY3Rp b24gb2YNCj4gZGF0YSBmb3Igc29tZSBkcml2ZXIuDQo+IA0KPiA+ICAtIHN2cy1ncHU6IEhhbmRs ZSB0byAmZ3B1IChCVFcsIGl0IGlzIGV4cGVjdGVkIHRoYXQgU1ZTIHdvdWxkIG9ubHkNCj4gPiBh cHBseSB0byB2Z3B1L21hbGkgcmVndWxhdG9yLCBhbmQgbm90IHZzcmFtIHJlZ3VsYXRvcj8pDQoN CnN2cy1ncHUgZGVwZW5kcyBvbiB2Z3B1IHBvd2VyIG9uIGZvciBpbml0IChkb24ndCBjYXJlIHZn cHVfc3JhbSkuIEFmdGVyDQpzdnMtZ3B1IGluaXQgaXMgZG9uZSwgaXQgZG9lc24ndCBuZWVkIHZn cHUgcG93ZXIgb24gYW55bW9yZS4gKHZncHUgY2FuDQpiZSB0dXJuZWQgb2ZmKQ0KDQpQbGVhc2Ug YWxsb3dzIG1lIHRvIGludHJvZHVjZSBtb3JlIGFib3V0IHdoYXQgc3ZzLWdwdSBkZXZpY2UgbmVl ZHMuDQoxLiBJdCBuZWVkcyBncHUgb3BwIHRhYmxlIGZyb20gImdwdSBub2RlIiBhbmQgZ3B1X2Nv cmUyIHBvd2VyLWRvbWFpbnMNCmZyb20gImdwdV9jb3JlMiBub2RlIi4gV2hlbiBzdnMtZ3B1IGhh cyB0aG9zZSByZXNvdXJjZXMsIGl0IHR1cm5zIG9uDQpncHVfY29yZTIgcG93ZXItZG9tYWluIGZv ciBzdnMtZ3B1LWh3IHRvIGhhdmUgcG93ZXIgKGZvciBjYWxjdWxhdGluZykNCmFuZCBzdnMtZ3B1 LXN3IHdpbGwgdXBkYXRlIGdwdSBvcHAgdGFibGUgdm9sdGFnZXMnIHBhcnQuDQoyLiBUaGVyZWZv cmUsIGlmIEkgcmV0cmlldmUgZ3B1LXJlbGF0ZWQgbm9kZSBmcm9tIHBoYW5kbGUgb3IgY29tcGF0 aWJsZSwNCml0IG1lYW5zIHN2cy1ncHUgZGV2aWNlIGluIGRyaXZlciBuZWVkcyB0byBhdHRhY2gg dHdvIGRpZmZlcmVudCBncHUNCm5vZGVzIGZvciBhdHRhaW5pbmcgZ3B1IG9wcCB0YWJsZSBhbmQg Z3B1X2NvcmUyIHBvd2VyLWRvbWFpbnMuIEkgdGhpbmsNCnRoaXMgYXJjaGl0ZWN0dXJlIG9mIHN2 cy1ncHUgY29uZnVzZXMgbWFpbnRhaW5lciB3aHkgaXQgYXR0YWNoZXMgdHdvDQpkaWZmZXJlbnQg bm9kZXMgaW5zdGVhZCBvZiBoYXZpbmcgYSBkZXZpY2UgdG8gZGVzY3JpYmUgd2hhdCBpdCBuZWVk cy4NCjMuIElzIGl0IGFjY2VwdGFibGUgdG8gaGF2ZSBhIExpbnV4IGRldmljZSBhdHRhY2hpbmcg dHdvIGRpZmZlcmVudA0Kbm9kZXM/IElmIHllcywgY291bGQgeW91IGd1aWRlIHVzIHNvbWUgQVBJ cyBmb3Igb25lIGRldmljZSB0byBhdHRhY2ggdHdvDQpub2Rlcz8gSSBkb24ndCBrbm93IGhvdyB0 byBpbXBsZW1lbnQgaXQuIFRoYW5rcy4NCg0KPiA+DQo+ID4gSSdtIG5vdCB0b28gc3VyZSBob3cg d2UnZCBmZXRjaCB0aGUgcmlnaHQgcmVndWxhdG9yIG5hbWUsIGhvd2V2ZXIgKGZvcg0KPiA+IHRo ZSBmaXJzdCAzIHRoZSBuYW1lIGlzICJwcm9jIiwgZm9yIHRoZSBsYXN0IG9uZSBpdCdzICJtYWxp IiksIG1heWJlDQo+ID4gYWRkIGEgcmVndWxhdG9yLW5hbWUgbGlzdCBpbiB0aGUgRFQ/DQo+IA0K PiBUbyBwdXQgdGhpcyBhbm90aGVyIHdheSwgd3JpdGUgYW4gU29DIHNwZWNpZmljIGRyaXZlciB0 aGF0IHVuZGVyc3RhbmRzDQo+IHRvIHNvbWUgZXh0ZW50IHdoYXQgZXhpc3RzIGluIHRoZSBTb0Mg KGFuZCBEVCkuIEkgZG91YnQgc29tZXRoaW5nIGxpa2UNCj4gdGhpcyBpcyBnb2luZyB0byBiZSBn ZW5lcmljIGFjcm9zcyBtb3JlIHRoYW4gYSBmZXcgU29DcyBhdCBtb3N0Lg0KDQo+IA0KPiBSb2IN Cg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD0DC352A3 for ; Tue, 11 Feb 2020 07:44:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93E06206D7 for ; Tue, 11 Feb 2020 07:44:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uply0uSh"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FTelS1W2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 93E06206D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3c/0hfgA9wiyaC6L463KTmDKQOjD936sp1CL48wbuIA=; b=uply0uShynQMUe f5TqTMlz5rEkk3f+dGFvk0w+0A4QUtyts59SrdMf6pm6ckW1QUIvJyVEq7F47vetLjsLsYGvRtVeZ chBg4X8mG3906+p5nBN6Vcy+LZfHZ01PxoFXVXQPsWnoDb+cHW88QwxX2VO3ZXIrHS/dIiVPMQORk +/OiYBV++DWczhmz7qt+o5zzgH5X3JBh3fXfbQy5cQMXm48FyVwFvkEgfPI4mbJ+43F0prx8XXVRe 9iqEAWHHI5pYRXgBaliPeWq6Z4UIucKSV3jRkgE6n1kI14YjTyBiqiPgJSNx9oIk489cB0j7uUHW+ 3ubxJCtEpnTlbQTZfaYA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j1QDO-0007mt-Lf; Tue, 11 Feb 2020 07:44:14 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j1QDK-0007lT-Kh; Tue, 11 Feb 2020 07:44:12 +0000 X-UUID: 9cb0417af0364f938a6ae87a9aab0423-20200210 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=WF9g4PEqWlupM4phER8lYwnueeO3pdMwX2AAwBSYAFg=; b=FTelS1W2ak4xC5AmE2V0wcsa9Rda4LaM3ywcKXJdrshuDKsgoWpUffDK8ongubWop0DZZD89r41mPLBabbicUdGz1XTyBesSGr6AGVuvLGJDQFCuq/5Hr0x6pi+xAtPDBPARppiz6WNEQmlpjI2n/Fc7u+HsodFyZXy+e03yK3o=; X-UUID: 9cb0417af0364f938a6ae87a9aab0423-20200210 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 730199669; Mon, 10 Feb 2020 23:44:02 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Feb 2020 23:36:15 -0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 11 Feb 2020 15:35:03 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 11 Feb 2020 15:36:19 +0800 Message-ID: <1581406566.14120.46.camel@mtksdaap41> Subject: Re: [PATCH v6 1/3] dt-bindings: soc: add mtk svs dt-bindings From: Roger Lu To: Rob Herring , Nicolas Boichat Date: Tue, 11 Feb 2020 15:36:06 +0800 In-Reply-To: References: <20200107070154.1574-1-roger.lu@mediatek.com> <20200107070154.1574-2-roger.lu@mediatek.com> <20200108203829.GA18987@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200210_234410_691340_30C59F27 X-CRM114-Status: GOOD ( 31.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nicolas Boichat , Angus Lin =?UTF-8?Q?=28=E6=9E=97=E7=91=9B=E8=B1=AA=29?= , Kevin Hilman , Stephen Boyd , jamesjj.liao@mediatek.com, "open list:THERMAL" , lkml , HenryC Chen =?UTF-8?Q?=28=E9=99=B3=E5=BB=BA=E8=B1=AA=29?= , YT Lee =?UTF-8?Q?=28=E6=9D=8E=E4=BB=B0=E5=93=B2=29?= , Fan Chen =?UTF-8?Q?=28=E9=99=B3=E5=87=A1=29?= , Devicetree List , "moderated list:ARM/Mediatek SoC support" , Xiaoqing Liu =?UTF-8?Q?=28=E5=88=98=E6=99=93=E5=BA=86=29?= , Charles Yang =?UTF-8?Q?=28=E6=A5=8A=E4=BA=8E=E9=80=B2=29?= , Matthias Brugger , Nishanth Menon , linux-arm Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob & Nicolas, Sorry for the late reply. On Mon, 2020-01-13 at 23:50 +0800, Rob Herring wrote: > On Mon, Jan 13, 2020 at 12:44 AM Nicolas Boichat wrote: > > > > On Thu, Jan 9, 2020 at 4:38 AM Rob Herring wrote: > > > > > > On Tue, Jan 07, 2020 at 03:01:52PM +0800, Roger Lu wrote: > > > > Document the binding for enabling mtk svs on MediaTek SoC. > > > > > > > > Signed-off-by: Roger Lu > > > > --- > > > > .../devicetree/bindings/power/mtk-svs.txt | 76 +++++++++++++++++++ > > > > 1 file changed, 76 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt > > > > > > > > diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt > > > > new file mode 100644 > > > > index 000000000000..9a3e81b9e1d2 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt > > > > @@ -0,0 +1,76 @@ > > > > +* Mediatek Smart Voltage Scaling (MTK SVS) > > > > + > > > > +This describes the device tree binding for the MTK SVS controller (bank) > > > > +which helps provide the optimized CPU/GPU/CCI voltages. This device also > > > > +needs thermal data to calculate thermal slope for accurately compensate > > > > +the voltages when temperature change. > > > > + > > > > +Required properties: > > > > +- compatible: > > > > + - "mediatek,mt8183-svs" : For MT8183 family of SoCs > > > > +- reg: Address range of the MTK SVS controller. > > > > +- interrupts: IRQ for the MTK SVS controller. > > > > +- clocks, clock-names: Clocks needed for the svs hardware. required > > > > + clocks are: > > > > + "main": Main clock for svs controller to work. > > > > +- nvmem-cells: Phandle to the calibration data provided by a nvmem device. > > > > +- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data" > > > > + > > > > +Subnodes: > > > > +- svs-cpu-little: SVS bank device node of little CPU > > > > + compatible: "mediatek,mt8183-svs-cpu-little" > > > > + operating-points-v2: OPP table hooked by SVS little CPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcpu-little-supply: PMIC buck of little CPU > > > > +- svs-cpu-big: SVS bank device node of big CPU > > > > + compatible: "mediatek,mt8183-svs-cpu-big" > > > > + operating-points-v2: OPP table hooked by SVS big CPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcpu-big-supply: PMIC buck of big CPU > > > > +- svs-cci: SVS bank device node of CCI > > > > + compatible: "mediatek,mt8183-svs-cci" > > > > + operating-points-v2: OPP table hooked by SVS CCI bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vcci-supply: PMIC buck of CCI > > > > +- svs-gpu: SVS bank device node of GPU > > > > + compatible: "mediatek,mt8183-svs-gpu" > > > > + operating-points-v2: OPP table hooked by SVS GPU bank. > > > > + SVS will optimze this OPP table voltage part. > > > > + vgpu-supply: PMIC buck of GPU > > > > + > > > > +Example: > > > > + > > > > + svs: svs@1100b000 { > > > > + compatible = "mediatek,mt8183-svs"; > > > > + reg = <0 0x1100b000 0 0x1000>; > > > > + interrupts = ; > > > > + clocks = <&infracfg CLK_INFRA_THERM>; > > > > + clock-names = "main_clk"; > > > > + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; > > > > + nvmem-cell-names = "svs-calibration-data", "calibration-data"; > > > > + > > > > + svs_cpu_little: svs-cpu-little { > > > > + compatible = "mediatek,mt8183-svs-cpu-little"; > > > > + operating-points-v2 = <&cluster0_opp>; > > > > + vcpu-little-supply = <&mt6358_vproc12_reg>; > > > > + }; > > > > > > I don't think this is a good binding. This information already exists > > > elsewhere in the DT, so your driver should just look in those nodes. > > > For example the regulator can be in the cpu nodes or the OPP table > > > itself. > > > > Roger, if that helps, without changing any other binding, on 8183, > > basically you could have: > > - svs-cpu-little: Add a handle to &cpu0 and get the regulator/opp > > table from it. > > - svs-cpu-big: Handle to &cpu4 > > Why do you need those? Use the compatible of the cpus to determine big > and little cores. Or there's the cpu capacity property that could be > used instead. > > > - svs-cci: Handle to &cci > > Is there more than 1 CCI? Just retrieve the node by the compatible. > There's no need to have nodes that simply serve as a collection of > data for some driver. > > > - svs-gpu: Handle to &gpu (BTW, it is expected that SVS would only > > apply to vgpu/mali regulator, and not vsram regulator?) svs-gpu depends on vgpu power on for init (don't care vgpu_sram). After svs-gpu init is done, it doesn't need vgpu power on anymore. (vgpu can be turned off) Please allows me to introduce more about what svs-gpu device needs. 1. It needs gpu opp table from "gpu node" and gpu_core2 power-domains from "gpu_core2 node". When svs-gpu has those resources, it turns on gpu_core2 power-domain for svs-gpu-hw to have power (for calculating) and svs-gpu-sw will update gpu opp table voltages' part. 2. Therefore, if I retrieve gpu-related node from phandle or compatible, it means svs-gpu device in driver needs to attach two different gpu nodes for attaining gpu opp table and gpu_core2 power-domains. I think this architecture of svs-gpu confuses maintainer why it attaches two different nodes instead of having a device to describe what it needs. 3. Is it acceptable to have a Linux device attaching two different nodes? If yes, could you guide us some APIs for one device to attach two nodes? I don't know how to implement it. Thanks. > > > > I'm not too sure how we'd fetch the right regulator name, however (for > > the first 3 the name is "proc", for the last one it's "mali"), maybe > > add a regulator-name list in the DT? > > To put this another way, write an SoC specific driver that understands > to some extent what exists in the SoC (and DT). I doubt something like > this is going to be generic across more than a few SoCs at most. > > Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel