From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62D7FC3F2CD for ; Tue, 3 Mar 2020 02:53:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 07EE5246E9 for ; Tue, 3 Mar 2020 02:53:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IeIo2aX6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727573AbgCCCxW (ORCPT ); Mon, 2 Mar 2020 21:53:22 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:33621 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726859AbgCCCxV (ORCPT ); Mon, 2 Mar 2020 21:53:21 -0500 X-UUID: 171917e35e774b8f97a5fdb24639db00-20200303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=8MBDjgDUG1Gbtx2Z1NxKuR7GRGFbh/9SkGfjXkEMHUw=; b=IeIo2aX6B6hzdgZR7OSwsGO8J2OV4ELKx5UoRec4UE8hmpilVkjxoealeRwzSh93H3QpYs2o69mSujGJZpO+Zeg6EqwWfsSTpCqaQnk+LnqkJWX2oT99B9NEQ78j8HRgZFpa1ei0nadx7ZgV0jJNFnyXSDfNz5QTnV6zM9+KCcs=; X-UUID: 171917e35e774b8f97a5fdb24639db00-20200303 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2143834874; Tue, 03 Mar 2020 10:53:05 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Mar 2020 10:51:52 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Mar 2020 10:50:23 +0800 Message-ID: <1583203972.12858.4.camel@mtksdaap41> Subject: Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device From: CK Hu To: Enric Balletbo i Serra CC: , , , , , , , , "Mauro Carvalho Chehab" , , , Weiyi Lu , "Seiya Wang" , , "Collabora Kernel ML" , mtk01761 , Allison Randal , Thomas Gleixner , , Kate Stewart , "Greg Kroah-Hartman" , Houlong Wei , Matthias Brugger , , , , , Minghsiu Tsai , Andrew-CT Chen , , , Matthias Brugger , , Richard Fontana , , , Daniel Vetter Date: Tue, 3 Mar 2020 10:52:52 +0800 In-Reply-To: <20200302110128.2664251-5-enric.balletbo@collabora.com> References: <20200302110128.2664251-1-enric.balletbo@collabora.com> <20200302110128.2664251-5-enric.balletbo@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 00B7F2C20D55390349F22FE86D820093B19171414C8131AE81267416E6CBFF342000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org SGksIEVucmljOg0KDQpPbiBNb24sIDIwMjAtMDMtMDIgYXQgMTI6MDEgKzAxMDAsIEVucmljIEJh bGxldGJvIGkgU2VycmEgd3JvdGU6DQo+IFByb3ZpZGUgYSBtdGtfbW1zeXNfZGRwX2Nvbm5lY3Qo KSBhbmQgbXRrX21tc3lzX2Rpc2Nvbm5lY3QoKSBmdW5jdGlvbnMgdG8NCj4gcmVwbGFjZSBtdGtf ZGRwX2FkZF9jb21wX3RvX3BhdGgoKSBhbmQgbXRrX2RkcF9yZW1vdmVfY29tcF9mcm9tX3BhdGgo KS4NCj4gVGhvc2UgZnVuY3Rpb25zIHdpbGwgYWxsb3cgRFJNIGRyaXZlciBhbmQgb3RoZXJzIHRv IGNvbnRyb2wgdGhlIGRhdGENCj4gcGF0aCByb3V0aW5nLg0KPiANCg0KUmV2aWV3ZWQtYnk6IENL IEh1IDxjay5odUBtZWRpYXRlay5jb20+DQoNCkJ1dCB3aGF0IGlzIHRoZSBiYXNlIG9mIHRoaXMg c2VyaWVzPyBXaGVuIEkgYXBwbHkgdGhpcyBwYXRjaCB0byA1LjYtcmMxLA0Kc29tZSBlcnJvciBo YXBwZW4sIHRoZSBhcHBseSAtLXJlamVjdCByZXN1bHQgaXMNCg0KSW4gZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kcm1fY3J0Yy5jLnJlag0KDQpkaWZmIGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fY3J0Yy5jDQpiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJt X2NydGMuYyAgICAgICAgKHJlamVjdGVkIGh1bmtzKQ0KQEAgLTI5Niw5ICsyOTcsOSBAQCBzdGF0 aWMgaW50IG10a19jcnRjX2RkcF9od19pbml0KHN0cnVjdCBtdGtfZHJtX2NydGMNCiptdGtfY3J0 YykNCiAgICAgICAgfQ0KDQogICAgICAgIGZvciAoaSA9IDA7IGkgPCBtdGtfY3J0Yy0+ZGRwX2Nv bXBfbnIgLSAxOyBpKyspIHsNCi0gICAgICAgICAgICAgICBtdGtfZGRwX2FkZF9jb21wX3RvX3Bh dGgobXRrX2NydGMtPmNvbmZpZ19yZWdzLA0KLSAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBtdGtfY3J0Yy0+ZGRwX2NvbXBbaV0tPmlkLA0KLSAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICBtdGtfY3J0Yy0+ZGRwX2NvbXBbaSArIDFdLT5pZCk7DQor ICAgICAgICAgICAgICAgbXRrX21tc3lzX2RkcF9jb25uZWN0KG10a19jcnRjLT5tbXN5c19kZXYs DQorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIG10a19jcnRjLT5kZHBfY29t cFtpXS0+aWQsDQorICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIG10a19jcnRj LT5kZHBfY29tcFtpICsgMV0tPmlkKTsNCiAgICAgICAgICAgICAgICBtdGtfZGlzcF9tdXRleF9h ZGRfY29tcChtdGtfY3J0Yy0+bXV0ZXgsDQogICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgbXRrX2NydGMtPmRkcF9jb21wW2ldLT5pZCk7DQogICAgICAgIH0NCg0KSSdzIHRy aXZpYWwgZm9yIG1lIHRvIGZpeCB0aGlzIGNvbmZsaWN0cywgc28geW91IGhhdmUgYmV0dGVyIHRv IG5vdGljZQ0Kd2hhdCBpcyB0aGUgYmFzZSBvZiB0aGlzIHNlcmllcyBpbiBjb3ZlciBsYXR0ZXIu DQoNClJlZ2FyZHMsDQpDSw0KDQoNCj4gU2lnbmVkLW9mZi1ieTogRW5yaWMgQmFsbGV0Ym8gaSBT ZXJyYSA8ZW5yaWMuYmFsbGV0Ym9AY29sbGFib3JhLmNvbT4NCj4gUmV2aWV3ZWQtYnk6IE1hdHRo aWFzIEJydWdnZXIgPG1hdHRoaWFzLmJnZ0BnbWFpbC5jb20+DQo+IC0tLQ0KPiANCj4gQ2hhbmdl cyBpbiB2MTE6DQo+IC0gU2VsZWN0IENPTkZJR19NVEtfTU1TWVMgKENLKQ0KPiAtIFBhc3MgZGV2 aWNlIHBvaW50ZXIgb2YgbW1zeXMgZGV2aWNlIGluc3RlYWQgb2YgY29uZmlnIHJlZ3MgKENLKQ0K PiANCj4gQ2hhbmdlcyBpbiB2MTA6DQo+IC0gSW50cm9kdWNlZCBhIG5ldyBwYXRjaCB0byBtb3Zl IHJvdXRpbmcgY29udHJvbCBpbnRvIG1tc3lzIGRyaXZlci4NCj4gLSBSZW1vdmVkIHRoZSBwYXRj aCB0byB1c2UgcmVnbWFwIGFzIGlzIG5vdCBuZWVkZWQgYW55bW9yZS4NCj4gDQo+IENoYW5nZXMg aW4gdjk6IE5vbmUNCj4gQ2hhbmdlcyBpbiB2ODogTm9uZQ0KPiBDaGFuZ2VzIGluIHY3OiBOb25l DQo+IA0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL0tjb25maWcgICAgICAgIHwgICAxICsN Cj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2NydGMuYyB8ICAxOSArLQ0KPiAg ZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMgIHwgMjU2IC0tLS0tLS0tLS0t LS0tLS0tLS0tLS0NCj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5oICB8 ICAgNyAtDQo+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kcnYuYyAgfCAgMTQg Ky0NCj4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5oICB8ICAgMiArLQ0K PiAgZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmMgICAgICAgIHwgMjc3ICsrKysrKysr KysrKysrKysrKysrKysrKw0KPiAgaW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lz LmggIHwgIDIwICsrDQo+ICA4IGZpbGVzIGNoYW5nZWQsIDMxNCBpbnNlcnRpb25zKCspLCAyODIg ZGVsZXRpb25zKC0pDQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgaW5jbHVkZS9saW51eC9zb2MvbWVk aWF0ZWsvbXRrLW1tc3lzLmgNCj4gDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvS2NvbmZpZyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9LY29uZmlnDQo+IGluZGV4 IGZhNWZmYzRmZTgyMy4uYzQyMGY1YTNkMzNiIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvS2NvbmZpZw0KPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvS2Nv bmZpZw0KPiBAQCAtMTEsNiArMTEsNyBAQCBjb25maWcgRFJNX01FRElBVEVLDQo+ICAJc2VsZWN0 IERSTV9NSVBJX0RTSQ0KPiAgCXNlbGVjdCBEUk1fUEFORUwNCj4gIAlzZWxlY3QgTUVNT1JZDQo+ ICsJc2VsZWN0IE1US19NTVNZUw0KPiAgCXNlbGVjdCBNVEtfU01JDQo+ICAJc2VsZWN0IFZJREVP TU9ERV9IRUxQRVJTDQo+ICAJaGVscA0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fY3J0Yy5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1f Y3J0Yy5jDQo+IGluZGV4IGZkNDA0MmRlMTJmMi4uZjYzYTg4NWUwNjNjIDEwMDY0NA0KPiAtLS0g YS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9jcnRjLmMNCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5jDQo+IEBAIC02LDYgKzYsNyBAQA0KPiAg I2luY2x1ZGUgPGxpbnV4L2Nsay5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4N Cj4gICNpbmNsdWRlIDxsaW51eC9zb2MvbWVkaWF0ZWsvbXRrLWNtZHEuaD4NCj4gKyNpbmNsdWRl IDxsaW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmg+DQo+ICANCj4gICNpbmNsdWRlIDxhc20v YmFycmllci5oPg0KPiAgI2luY2x1ZGUgPHNvYy9tZWRpYXRlay9zbWkuaD4NCj4gQEAgLTI4LDcg KzI5LDcgQEANCj4gICAqIEBlbmFibGVkOiByZWNvcmRzIHdoZXRoZXIgY3J0Y19lbmFibGUgc3Vj Y2VlZGVkDQo+ICAgKiBAcGxhbmVzOiBhcnJheSBvZiA0IGRybV9wbGFuZSBzdHJ1Y3R1cmVzLCBv bmUgZm9yIGVhY2ggb3ZlcmxheSBwbGFuZQ0KPiAgICogQHBlbmRpbmdfcGxhbmVzOiB3aGV0aGVy IGFueSBwbGFuZSBoYXMgcGVuZGluZyBjaGFuZ2VzIHRvIGJlIGFwcGxpZWQNCj4gLSAqIEBjb25m aWdfcmVnczogbWVtb3J5IG1hcHBlZCBtbXN5cyBjb25maWd1cmF0aW9uIHJlZ2lzdGVyIHNwYWNl DQo+ICsgKiBAbW1zeXNfZGV2OiBwb2ludGVyIHRvIHRoZSBtbXN5cyBkZXZpY2UgZm9yIGNvbmZp Z3VyYXRpb24gcmVnaXN0ZXJzDQo+ICAgKiBAbXV0ZXg6IGhhbmRsZSB0byBvbmUgb2YgdGhlIHRl biBkaXNwX211dGV4IHN0cmVhbXMNCj4gICAqIEBkZHBfY29tcF9ucjogbnVtYmVyIG9mIGNvbXBv bmVudHMgaW4gZGRwX2NvbXANCj4gICAqIEBkZHBfY29tcDogYXJyYXkgb2YgcG9pbnRlcnMgdGhl IG10a19kZHBfY29tcCBzdHJ1Y3R1cmVzIHVzZWQgYnkgdGhpcyBjcnRjDQo+IEBAIC01MCw3ICs1 MSw3IEBAIHN0cnVjdCBtdGtfZHJtX2NydGMgew0KPiAgCXUzMgkJCQljbWRxX2V2ZW50Ow0KPiAg I2VuZGlmDQo+ICANCj4gLQl2b2lkIF9faW9tZW0JCQkqY29uZmlnX3JlZ3M7DQo+ICsJc3RydWN0 IGRldmljZQkJCSptbXN5c19kZXY7DQo+ICAJc3RydWN0IG10a19kaXNwX211dGV4CQkqbXV0ZXg7 DQo+ICAJdW5zaWduZWQgaW50CQkJZGRwX2NvbXBfbnI7DQo+ICAJc3RydWN0IG10a19kZHBfY29t cAkJKipkZHBfY29tcDsNCj4gQEAgLTI5Niw5ICsyOTcsOSBAQCBzdGF0aWMgaW50IG10a19jcnRj X2RkcF9od19pbml0KHN0cnVjdCBtdGtfZHJtX2NydGMgKm10a19jcnRjKQ0KPiAgCX0NCj4gIA0K PiAgCWZvciAoaSA9IDA7IGkgPCBtdGtfY3J0Yy0+ZGRwX2NvbXBfbnIgLSAxOyBpKyspIHsNCj4g LQkJbXRrX2RkcF9hZGRfY29tcF90b19wYXRoKG10a19jcnRjLT5jb25maWdfcmVncywNCj4gLQkJ CQkJIG10a19jcnRjLT5kZHBfY29tcFtpXS0+aWQsDQo+IC0JCQkJCSBtdGtfY3J0Yy0+ZGRwX2Nv bXBbaSArIDFdLT5pZCk7DQo+ICsJCW10a19tbXN5c19kZHBfY29ubmVjdChtdGtfY3J0Yy0+bW1z eXNfZGV2LA0KPiArCQkJCSAgICAgIG10a19jcnRjLT5kZHBfY29tcFtpXS0+aWQsDQo+ICsJCQkJ ICAgICAgbXRrX2NydGMtPmRkcF9jb21wW2kgKyAxXS0+aWQpOw0KPiAgCQltdGtfZGlzcF9tdXRl eF9hZGRfY29tcChtdGtfY3J0Yy0+bXV0ZXgsDQo+ICAJCQkJCW10a19jcnRjLT5kZHBfY29tcFtp XS0+aWQpOw0KPiAgCX0NCj4gQEAgLTM1NSw5ICszNTYsOSBAQCBzdGF0aWMgdm9pZCBtdGtfY3J0 Y19kZHBfaHdfZmluaShzdHJ1Y3QgbXRrX2RybV9jcnRjICptdGtfY3J0YykNCj4gIAkJCQkJICAg bXRrX2NydGMtPmRkcF9jb21wW2ldLT5pZCk7DQo+ICAJbXRrX2Rpc3BfbXV0ZXhfZGlzYWJsZSht dGtfY3J0Yy0+bXV0ZXgpOw0KPiAgCWZvciAoaSA9IDA7IGkgPCBtdGtfY3J0Yy0+ZGRwX2NvbXBf bnIgLSAxOyBpKyspIHsNCj4gLQkJbXRrX2RkcF9yZW1vdmVfY29tcF9mcm9tX3BhdGgobXRrX2Ny dGMtPmNvbmZpZ19yZWdzLA0KPiAtCQkJCQkgICAgICBtdGtfY3J0Yy0+ZGRwX2NvbXBbaV0tPmlk LA0KPiAtCQkJCQkgICAgICBtdGtfY3J0Yy0+ZGRwX2NvbXBbaSArIDFdLT5pZCk7DQo+ICsJCW10 a19tbXN5c19kZHBfZGlzY29ubmVjdChtdGtfY3J0Yy0+bW1zeXNfZGV2LA0KPiArCQkJCQkgbXRr X2NydGMtPmRkcF9jb21wW2ldLT5pZCwNCj4gKwkJCQkJIG10a19jcnRjLT5kZHBfY29tcFtpICsg MV0tPmlkKTsNCj4gIAkJbXRrX2Rpc3BfbXV0ZXhfcmVtb3ZlX2NvbXAobXRrX2NydGMtPm11dGV4 LA0KPiAgCQkJCQkgICBtdGtfY3J0Yy0+ZGRwX2NvbXBbaV0tPmlkKTsNCj4gIAl9DQo+IEBAIC03 NTgsNyArNzU5LDcgQEAgaW50IG10a19kcm1fY3J0Y19jcmVhdGUoc3RydWN0IGRybV9kZXZpY2Ug KmRybV9kZXYsDQo+ICAJaWYgKCFtdGtfY3J0YykNCj4gIAkJcmV0dXJuIC1FTk9NRU07DQo+ICAN Cj4gLQltdGtfY3J0Yy0+Y29uZmlnX3JlZ3MgPSBwcml2LT5jb25maWdfcmVnczsNCj4gKwltdGtf Y3J0Yy0+bW1zeXNfZGV2ID0gcHJpdi0+bW1zeXNfZGV2Ow0KPiAgCW10a19jcnRjLT5kZHBfY29t cF9uciA9IHBhdGhfbGVuOw0KPiAgCW10a19jcnRjLT5kZHBfY29tcCA9IGRldm1fa21hbGxvY19h cnJheShkZXYsIG10a19jcnRjLT5kZHBfY29tcF9uciwNCj4gIAkJCQkJCXNpemVvZigqbXRrX2Ny dGMtPmRkcF9jb21wKSwNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2RkcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMNCj4g aW5kZXggYjg4NWY2MGY0NzRjLi4wMTRjMWJiZTFkZjIgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5jDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9t ZWRpYXRlay9tdGtfZHJtX2RkcC5jDQo+IEBAIC0xMywyNiArMTMsNiBAQA0KPiAgI2luY2x1ZGUg Im10a19kcm1fZGRwLmgiDQo+ICAjaW5jbHVkZSAibXRrX2RybV9kZHBfY29tcC5oIg0KPiAgDQo+ IC0jZGVmaW5lIERJU1BfUkVHX0NPTkZJR19ESVNQX09WTDBfTU9VVF9FTgkweDA0MA0KPiAtI2Rl ZmluZSBESVNQX1JFR19DT05GSUdfRElTUF9PVkwxX01PVVRfRU4JMHgwNDQNCj4gLSNkZWZpbmUg RElTUF9SRUdfQ09ORklHX0RJU1BfT0RfTU9VVF9FTgkJMHgwNDgNCj4gLSNkZWZpbmUgRElTUF9S RUdfQ09ORklHX0RJU1BfR0FNTUFfTU9VVF9FTgkweDA0Yw0KPiAtI2RlZmluZSBESVNQX1JFR19D T05GSUdfRElTUF9VRk9FX01PVVRfRU4JMHgwNTANCj4gLSNkZWZpbmUgRElTUF9SRUdfQ09ORklH X0RJU1BfQ09MT1IwX1NFTF9JTgkweDA4NA0KPiAtI2RlZmluZSBESVNQX1JFR19DT05GSUdfRElT UF9DT0xPUjFfU0VMX0lOCTB4MDg4DQo+IC0jZGVmaW5lIERJU1BfUkVHX0NPTkZJR19EU0lFX1NF TF9JTgkJMHgwYTQNCj4gLSNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RTSU9fU0VMX0lOCQkweDBh OA0KPiAtI2RlZmluZSBESVNQX1JFR19DT05GSUdfRFBJX1NFTF9JTgkJMHgwYWMNCj4gLSNkZWZp bmUgRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTJfU09VVAkJMHgwYjgNCj4gLSNkZWZpbmUgRElT UF9SRUdfQ09ORklHX0RJU1BfUkRNQTBfU09VVF9FTgkweDBjNA0KPiAtI2RlZmluZSBESVNQX1JF R19DT05GSUdfRElTUF9SRE1BMV9TT1VUX0VOCTB4MGM4DQo+IC0jZGVmaW5lIERJU1BfUkVHX0NP TkZJR19NTVNZU19DR19DT04wCQkweDEwMA0KPiAtDQo+IC0jZGVmaW5lIERJU1BfUkVHX0NPTkZJ R19ESVNQX09WTF9NT1VUX0VOCTB4MDMwDQo+IC0jZGVmaW5lIERJU1BfUkVHX0NPTkZJR19PVVRf U0VMCQkJMHgwNGMNCj4gLSNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RTSV9TRUwJCQkweDA1MA0K PiAtI2RlZmluZSBESVNQX1JFR19DT05GSUdfRFBJX1NFTAkJCTB4MDY0DQo+IC0NCj4gICNkZWZp bmUgTVQyNzAxX0RJU1BfTVVURVgwX01PRDAJCQkweDJjDQo+ICAjZGVmaW5lIE1UMjcwMV9ESVNQ X01VVEVYMF9TT0YwCQkJMHgzMA0KPiAgDQo+IEBAIC05NCw0OCArNzQsNiBAQA0KPiAgI2RlZmlu ZSBNVVRFWF9TT0ZfRFNJMgkJCTUNCj4gICNkZWZpbmUgTVVURVhfU09GX0RTSTMJCQk2DQo+ICAN Cj4gLSNkZWZpbmUgT1ZMMF9NT1VUX0VOX0NPTE9SMAkJMHgxDQo+IC0jZGVmaW5lIE9EX01PVVRf RU5fUkRNQTAJCTB4MQ0KPiAtI2RlZmluZSBPRDFfTU9VVF9FTl9SRE1BMQkJQklUKDE2KQ0KPiAt I2RlZmluZSBVRk9FX01PVVRfRU5fRFNJMAkJMHgxDQo+IC0jZGVmaW5lIENPTE9SMF9TRUxfSU5f T1ZMMAkJMHgxDQo+IC0jZGVmaW5lIE9WTDFfTU9VVF9FTl9DT0xPUjEJCTB4MQ0KPiAtI2RlZmlu ZSBHQU1NQV9NT1VUX0VOX1JETUExCQkweDENCj4gLSNkZWZpbmUgUkRNQTBfU09VVF9EUEkwCQkJ MHgyDQo+IC0jZGVmaW5lIFJETUEwX1NPVVRfRFBJMQkJCTB4Mw0KPiAtI2RlZmluZSBSRE1BMF9T T1VUX0RTSTEJCQkweDENCj4gLSNkZWZpbmUgUkRNQTBfU09VVF9EU0kyCQkJMHg0DQo+IC0jZGVm aW5lIFJETUEwX1NPVVRfRFNJMwkJCTB4NQ0KPiAtI2RlZmluZSBSRE1BMV9TT1VUX0RQSTAJCQkw eDINCj4gLSNkZWZpbmUgUkRNQTFfU09VVF9EUEkxCQkJMHgzDQo+IC0jZGVmaW5lIFJETUExX1NP VVRfRFNJMQkJCTB4MQ0KPiAtI2RlZmluZSBSRE1BMV9TT1VUX0RTSTIJCQkweDQNCj4gLSNkZWZp bmUgUkRNQTFfU09VVF9EU0kzCQkJMHg1DQo+IC0jZGVmaW5lIFJETUEyX1NPVVRfRFBJMAkJCTB4 Mg0KPiAtI2RlZmluZSBSRE1BMl9TT1VUX0RQSTEJCQkweDMNCj4gLSNkZWZpbmUgUkRNQTJfU09V VF9EU0kxCQkJMHgxDQo+IC0jZGVmaW5lIFJETUEyX1NPVVRfRFNJMgkJCTB4NA0KPiAtI2RlZmlu ZSBSRE1BMl9TT1VUX0RTSTMJCQkweDUNCj4gLSNkZWZpbmUgRFBJMF9TRUxfSU5fUkRNQTEJCTB4 MQ0KPiAtI2RlZmluZSBEUEkwX1NFTF9JTl9SRE1BMgkJMHgzDQo+IC0jZGVmaW5lIERQSTFfU0VM X0lOX1JETUExCQkoMHgxIDw8IDgpDQo+IC0jZGVmaW5lIERQSTFfU0VMX0lOX1JETUEyCQkoMHgz IDw8IDgpDQo+IC0jZGVmaW5lIERTSTBfU0VMX0lOX1JETUExCQkweDENCj4gLSNkZWZpbmUgRFNJ MF9TRUxfSU5fUkRNQTIJCTB4NA0KPiAtI2RlZmluZSBEU0kxX1NFTF9JTl9SRE1BMQkJMHgxDQo+ IC0jZGVmaW5lIERTSTFfU0VMX0lOX1JETUEyCQkweDQNCj4gLSNkZWZpbmUgRFNJMl9TRUxfSU5f UkRNQTEJCSgweDEgPDwgMTYpDQo+IC0jZGVmaW5lIERTSTJfU0VMX0lOX1JETUEyCQkoMHg0IDw8 IDE2KQ0KPiAtI2RlZmluZSBEU0kzX1NFTF9JTl9SRE1BMQkJKDB4MSA8PCAxNikNCj4gLSNkZWZp bmUgRFNJM19TRUxfSU5fUkRNQTIJCSgweDQgPDwgMTYpDQo+IC0jZGVmaW5lIENPTE9SMV9TRUxf SU5fT1ZMMQkJMHgxDQo+IC0NCj4gLSNkZWZpbmUgT1ZMX01PVVRfRU5fUkRNQQkJMHgxDQo+IC0j ZGVmaW5lIEJMU19UT19EU0lfUkRNQTFfVE9fRFBJMQkweDgNCj4gLSNkZWZpbmUgQkxTX1RPX0RQ SV9SRE1BMV9UT19EU0kJCTB4Mg0KPiAtI2RlZmluZSBEU0lfU0VMX0lOX0JMUwkJCTB4MA0KPiAt I2RlZmluZSBEUElfU0VMX0lOX0JMUwkJCTB4MA0KPiAtI2RlZmluZSBEU0lfU0VMX0lOX1JETUEJ CQkweDENCj4gIA0KPiAgc3RydWN0IG10a19kaXNwX211dGV4IHsNCj4gIAlpbnQgaWQ7DQo+IEBA IC0yNDYsMjAwICsxODQsNiBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfZGF0YSBtdDgx NzNfZGRwX2RyaXZlcl9kYXRhID0gew0KPiAgCS5tdXRleF9zb2ZfcmVnID0gTVQyNzAxX0RJU1Bf TVVURVgwX1NPRjAsDQo+ICB9Ow0KPiAgDQo+IC1zdGF0aWMgdW5zaWduZWQgaW50IG10a19kZHBf bW91dF9lbihlbnVtIG10a19kZHBfY29tcF9pZCBjdXIsDQo+IC0JCQkJICAgIGVudW0gbXRrX2Rk cF9jb21wX2lkIG5leHQsDQo+IC0JCQkJICAgIHVuc2lnbmVkIGludCAqYWRkcikNCj4gLXsNCj4g LQl1bnNpZ25lZCBpbnQgdmFsdWU7DQo+IC0NCj4gLQlpZiAoY3VyID09IEREUF9DT01QT05FTlRf T1ZMMCAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfQ09MT1IwKSB7DQo+IC0JCSphZGRyID0gRElT UF9SRUdfQ09ORklHX0RJU1BfT1ZMMF9NT1VUX0VOOw0KPiAtCQl2YWx1ZSA9IE9WTDBfTU9VVF9F Tl9DT0xPUjA7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9PVkwwICYmIG5l eHQgPT0gRERQX0NPTVBPTkVOVF9SRE1BMCkgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJ R19ESVNQX09WTF9NT1VUX0VOOw0KPiAtCQl2YWx1ZSA9IE9WTF9NT1VUX0VOX1JETUE7DQo+IC0J fSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9PRDAgJiYgbmV4dCA9PSBERFBfQ09NUE9O RU5UX1JETUEwKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfT0RfTU9VVF9F TjsNCj4gLQkJdmFsdWUgPSBPRF9NT1VUX0VOX1JETUEwOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09 IEREUF9DT01QT05FTlRfVUZPRSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMCkgew0KPiAt CQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1VGT0VfTU9VVF9FTjsNCj4gLQkJdmFsdWUg PSBVRk9FX01PVVRfRU5fRFNJMDsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5U X09WTDEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0NPTE9SMSkgew0KPiAtCQkqYWRkciA9IERJ U1BfUkVHX0NPTkZJR19ESVNQX09WTDFfTU9VVF9FTjsNCj4gLQkJdmFsdWUgPSBPVkwxX01PVVRf RU5fQ09MT1IxOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfR0FNTUEgJiYg bmV4dCA9PSBERFBfQ09NUE9ORU5UX1JETUExKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09O RklHX0RJU1BfR0FNTUFfTU9VVF9FTjsNCj4gLQkJdmFsdWUgPSBHQU1NQV9NT1VUX0VOX1JETUEx Ow0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfT0QxICYmIG5leHQgPT0gRERQ X0NPTVBPTkVOVF9SRE1BMSkgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX09E X01PVVRfRU47DQo+IC0JCXZhbHVlID0gT0QxX01PVVRfRU5fUkRNQTE7DQo+IC0JfSBlbHNlIGlm IChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMCAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJ MCkgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUEwX1NPVVRfRU47DQo+ IC0JCXZhbHVlID0gUkRNQTBfU09VVF9EUEkwOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9D T01QT05FTlRfUkRNQTAgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTEpIHsNCj4gLQkJKmFk ZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9SRE1BMF9TT1VUX0VOOw0KPiAtCQl2YWx1ZSA9IFJE TUEwX1NPVVRfRFBJMTsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEw ICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kxKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdf Q09ORklHX0RJU1BfUkRNQTBfU09VVF9FTjsNCj4gLQkJdmFsdWUgPSBSRE1BMF9TT1VUX0RTSTE7 DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMCAmJiBuZXh0ID09IERE UF9DT01QT05FTlRfRFNJMikgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JE TUEwX1NPVVRfRU47DQo+IC0JCXZhbHVlID0gUkRNQTBfU09VVF9EU0kyOw0KPiAtCX0gZWxzZSBp ZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTAgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RT STMpIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9SRE1BMF9TT1VUX0VOOw0K PiAtCQl2YWx1ZSA9IFJETUEwX1NPVVRfRFNJMzsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBf Q09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kxKSB7DQo+IC0JCSph ZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFfU09VVF9FTjsNCj4gLQkJdmFsdWUgPSBS RE1BMV9TT1VUX0RTSTE7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1B MSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMikgew0KPiAtCQkqYWRkciA9IERJU1BfUkVH X0NPTkZJR19ESVNQX1JETUExX1NPVVRfRU47DQo+IC0JCXZhbHVlID0gUkRNQTFfU09VVF9EU0ky Ow0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBE RFBfQ09NUE9ORU5UX0RTSTMpIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9S RE1BMV9TT1VUX0VOOw0KPiAtCQl2YWx1ZSA9IFJETUExX1NPVVRfRFNJMzsNCj4gLQl9IGVsc2Ug aWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9E UEkwKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFfU09VVF9FTjsN Cj4gLQkJdmFsdWUgPSBSRE1BMV9TT1VUX0RQSTA7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQ X0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgew0KPiAtCQkq YWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUExX1NPVVRfRU47DQo+IC0JCXZhbHVlID0g UkRNQTFfU09VVF9EUEkxOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRN QTIgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTApIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JF R19DT05GSUdfRElTUF9SRE1BMl9TT1VUOw0KPiAtCQl2YWx1ZSA9IFJETUEyX1NPVVRfRFBJMDsN Cj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQ X0NPTVBPTkVOVF9EUEkxKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRN QTJfU09VVDsNCj4gLQkJdmFsdWUgPSBSRE1BMl9TT1VUX0RQSTE7DQo+IC0JfSBlbHNlIGlmIChj dXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMiAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMSkg ew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUEyX1NPVVQ7DQo+IC0JCXZh bHVlID0gUkRNQTJfU09VVF9EU0kxOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05F TlRfUkRNQTIgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTIpIHsNCj4gLQkJKmFkZHIgPSBE SVNQX1JFR19DT05GSUdfRElTUF9SRE1BMl9TT1VUOw0KPiAtCQl2YWx1ZSA9IFJETUEyX1NPVVRf RFNJMjsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQg PT0gRERQX0NPTVBPTkVOVF9EU0kzKSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJ U1BfUkRNQTJfU09VVDsNCj4gLQkJdmFsdWUgPSBSRE1BMl9TT1VUX0RTSTM7DQo+IC0JfSBlbHNl IHsNCj4gLQkJdmFsdWUgPSAwOw0KPiAtCX0NCj4gLQ0KPiAtCXJldHVybiB2YWx1ZTsNCj4gLX0N Cj4gLQ0KPiAtc3RhdGljIHVuc2lnbmVkIGludCBtdGtfZGRwX3NlbF9pbihlbnVtIG10a19kZHBf Y29tcF9pZCBjdXIsDQo+IC0JCQkJICAgZW51bSBtdGtfZGRwX2NvbXBfaWQgbmV4dCwNCj4gLQkJ CQkgICB1bnNpZ25lZCBpbnQgKmFkZHIpDQo+IC17DQo+IC0JdW5zaWduZWQgaW50IHZhbHVlOw0K PiAtDQo+IC0JaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09WTDAgJiYgbmV4dCA9PSBERFBfQ09N UE9ORU5UX0NPTE9SMCkgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX0NPTE9S MF9TRUxfSU47DQo+IC0JCXZhbHVlID0gQ09MT1IwX1NFTF9JTl9PVkwwOw0KPiAtCX0gZWxzZSBp ZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQ STApIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFBJX1NFTF9JTjsNCj4gLQkJdmFs dWUgPSBEUEkwX1NFTF9JTl9SRE1BMTsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9O RU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkxKSB7DQo+IC0JCSphZGRyID0g RElTUF9SRUdfQ09ORklHX0RQSV9TRUxfSU47DQo+IC0JCXZhbHVlID0gRFBJMV9TRUxfSU5fUkRN QTE7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09 IEREUF9DT01QT05FTlRfRFNJMCkgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lF X1NFTF9JTjsNCj4gLQkJdmFsdWUgPSBEU0kwX1NFTF9JTl9SRE1BMTsNCj4gLQl9IGVsc2UgaWYg KGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kx KSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RTSU9fU0VMX0lOOw0KPiAtCQl2YWx1 ZSA9IERTSTFfU0VMX0lOX1JETUExOw0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05F TlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTIpIHsNCj4gLQkJKmFkZHIgPSBE SVNQX1JFR19DT05GSUdfRFNJRV9TRUxfSU47DQo+IC0JCXZhbHVlID0gRFNJMl9TRUxfSU5fUkRN QTE7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09 IEREUF9DT01QT05FTlRfRFNJMykgew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lP X1NFTF9JTjsNCj4gLQkJdmFsdWUgPSBEU0kzX1NFTF9JTl9SRE1BMTsNCj4gLQl9IGVsc2UgaWYg KGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkw KSB7DQo+IC0JCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RQSV9TRUxfSU47DQo+IC0JCXZhbHVl ID0gRFBJMF9TRUxfSU5fUkRNQTI7DQo+IC0JfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVO VF9SRE1BMiAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgew0KPiAtCQkqYWRkciA9IERJ U1BfUkVHX0NPTkZJR19EUElfU0VMX0lOOw0KPiAtCQl2YWx1ZSA9IERQSTFfU0VMX0lOX1JETUEy Ow0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYgbmV4dCA9PSBE RFBfQ09NUE9ORU5UX0RTSTApIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFNJRV9T RUxfSU47DQo+IC0JCXZhbHVlID0gRFNJMF9TRUxfSU5fUkRNQTI7DQo+IC0JfSBlbHNlIGlmIChj dXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMiAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMSkg ew0KPiAtCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lPX1NFTF9JTjsNCj4gLQkJdmFsdWUg PSBEU0kxX1NFTF9JTl9SRE1BMjsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5U X1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kyKSB7DQo+IC0JCSphZGRyID0gRElT UF9SRUdfQ09ORklHX0RTSUVfU0VMX0lOOw0KPiAtCQl2YWx1ZSA9IERTSTJfU0VMX0lOX1JETUEy Ow0KPiAtCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYgbmV4dCA9PSBE RFBfQ09NUE9ORU5UX0RTSTMpIHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFNJRV9T RUxfSU47DQo+IC0JCXZhbHVlID0gRFNJM19TRUxfSU5fUkRNQTI7DQo+IC0JfSBlbHNlIGlmIChj dXIgPT0gRERQX0NPTVBPTkVOVF9PVkwxICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9DT0xPUjEp IHsNCj4gLQkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9DT0xPUjFfU0VMX0lOOw0KPiAt CQl2YWx1ZSA9IENPTE9SMV9TRUxfSU5fT1ZMMTsNCj4gLQl9IGVsc2UgaWYgKGN1ciA9PSBERFBf Q09NUE9ORU5UX0JMUyAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMCkgew0KPiAtCQkqYWRk ciA9IERJU1BfUkVHX0NPTkZJR19EU0lfU0VMOw0KPiAtCQl2YWx1ZSA9IERTSV9TRUxfSU5fQkxT Ow0KPiAtCX0gZWxzZSB7DQo+IC0JCXZhbHVlID0gMDsNCj4gLQl9DQo+IC0NCj4gLQlyZXR1cm4g dmFsdWU7DQo+IC19DQo+IC0NCj4gLXN0YXRpYyB2b2lkIG10a19kZHBfc291dF9zZWwodm9pZCBf X2lvbWVtICpjb25maWdfcmVncywNCj4gLQkJCSAgICAgZW51bSBtdGtfZGRwX2NvbXBfaWQgY3Vy LA0KPiAtCQkJICAgICBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0KQ0KPiAtew0KPiAtCWlmIChj dXIgPT0gRERQX0NPTVBPTkVOVF9CTFMgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTApIHsN Cj4gLQkJd3JpdGVsX3JlbGF4ZWQoQkxTX1RPX0RTSV9SRE1BMV9UT19EUEkxLA0KPiAtCQkJICAg ICAgIGNvbmZpZ19yZWdzICsgRElTUF9SRUdfQ09ORklHX09VVF9TRUwpOw0KPiAtCX0gZWxzZSBp ZiAoY3VyID09IEREUF9DT01QT05FTlRfQkxTICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkw KSB7DQo+IC0JCXdyaXRlbF9yZWxheGVkKEJMU19UT19EUElfUkRNQTFfVE9fRFNJLA0KPiAtCQkJ ICAgICAgIGNvbmZpZ19yZWdzICsgRElTUF9SRUdfQ09ORklHX09VVF9TRUwpOw0KPiAtCQl3cml0 ZWxfcmVsYXhlZChEU0lfU0VMX0lOX1JETUEsDQo+IC0JCQkgICAgICAgY29uZmlnX3JlZ3MgKyBE SVNQX1JFR19DT05GSUdfRFNJX1NFTCk7DQo+IC0JCXdyaXRlbF9yZWxheGVkKERQSV9TRUxfSU5f QkxTLA0KPiAtCQkJICAgICAgIGNvbmZpZ19yZWdzICsgRElTUF9SRUdfQ09ORklHX0RQSV9TRUwp Ow0KPiAtCX0NCj4gLX0NCj4gLQ0KPiAtdm9pZCBtdGtfZGRwX2FkZF9jb21wX3RvX3BhdGgodm9p ZCBfX2lvbWVtICpjb25maWdfcmVncywNCj4gLQkJCSAgICAgIGVudW0gbXRrX2RkcF9jb21wX2lk IGN1ciwNCj4gLQkJCSAgICAgIGVudW0gbXRrX2RkcF9jb21wX2lkIG5leHQpDQo+IC17DQo+IC0J dW5zaWduZWQgaW50IGFkZHIsIHZhbHVlLCByZWc7DQo+IC0NCj4gLQl2YWx1ZSA9IG10a19kZHBf bW91dF9lbihjdXIsIG5leHQsICZhZGRyKTsNCj4gLQlpZiAodmFsdWUpIHsNCj4gLQkJcmVnID0g cmVhZGxfcmVsYXhlZChjb25maWdfcmVncyArIGFkZHIpIHwgdmFsdWU7DQo+IC0JCXdyaXRlbF9y ZWxheGVkKHJlZywgY29uZmlnX3JlZ3MgKyBhZGRyKTsNCj4gLQl9DQo+IC0NCj4gLQltdGtfZGRw X3NvdXRfc2VsKGNvbmZpZ19yZWdzLCBjdXIsIG5leHQpOw0KPiAtDQo+IC0JdmFsdWUgPSBtdGtf ZGRwX3NlbF9pbihjdXIsIG5leHQsICZhZGRyKTsNCj4gLQlpZiAodmFsdWUpIHsNCj4gLQkJcmVn ID0gcmVhZGxfcmVsYXhlZChjb25maWdfcmVncyArIGFkZHIpIHwgdmFsdWU7DQo+IC0JCXdyaXRl bF9yZWxheGVkKHJlZywgY29uZmlnX3JlZ3MgKyBhZGRyKTsNCj4gLQl9DQo+IC19DQo+IC0NCj4g LXZvaWQgbXRrX2RkcF9yZW1vdmVfY29tcF9mcm9tX3BhdGgodm9pZCBfX2lvbWVtICpjb25maWdf cmVncywNCj4gLQkJCQkgICBlbnVtIG10a19kZHBfY29tcF9pZCBjdXIsDQo+IC0JCQkJICAgZW51 bSBtdGtfZGRwX2NvbXBfaWQgbmV4dCkNCj4gLXsNCj4gLQl1bnNpZ25lZCBpbnQgYWRkciwgdmFs dWUsIHJlZzsNCj4gLQ0KPiAtCXZhbHVlID0gbXRrX2RkcF9tb3V0X2VuKGN1ciwgbmV4dCwgJmFk ZHIpOw0KPiAtCWlmICh2YWx1ZSkgew0KPiAtCQlyZWcgPSByZWFkbF9yZWxheGVkKGNvbmZpZ19y ZWdzICsgYWRkcikgJiB+dmFsdWU7DQo+IC0JCXdyaXRlbF9yZWxheGVkKHJlZywgY29uZmlnX3Jl Z3MgKyBhZGRyKTsNCj4gLQl9DQo+IC0NCj4gLQl2YWx1ZSA9IG10a19kZHBfc2VsX2luKGN1ciwg bmV4dCwgJmFkZHIpOw0KPiAtCWlmICh2YWx1ZSkgew0KPiAtCQlyZWcgPSByZWFkbF9yZWxheGVk KGNvbmZpZ19yZWdzICsgYWRkcikgJiB+dmFsdWU7DQo+IC0JCXdyaXRlbF9yZWxheGVkKHJlZywg Y29uZmlnX3JlZ3MgKyBhZGRyKTsNCj4gLQl9DQo+IC19DQo+IC0NCj4gIHN0cnVjdCBtdGtfZGlz cF9tdXRleCAqbXRrX2Rpc3BfbXV0ZXhfZ2V0KHN0cnVjdCBkZXZpY2UgKmRldiwgdW5zaWduZWQg aW50IGlkKQ0KPiAgew0KPiAgCXN0cnVjdCBtdGtfZGRwICpkZHAgPSBkZXZfZ2V0X2RydmRhdGEo ZGV2KTsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rk cC5oIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmgNCj4gaW5kZXggODI3 YmU0MjRhMTQ4Li42YjY5MWE1N2JlNGEgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9t ZWRpYXRlay9tdGtfZHJtX2RkcC5oDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2RkcC5oDQo+IEBAIC0xMiwxMyArMTIsNiBAQCBzdHJ1Y3QgcmVnbWFwOw0KPiAgc3Ry dWN0IGRldmljZTsNCj4gIHN0cnVjdCBtdGtfZGlzcF9tdXRleDsNCj4gIA0KPiAtdm9pZCBtdGtf ZGRwX2FkZF9jb21wX3RvX3BhdGgodm9pZCBfX2lvbWVtICpjb25maWdfcmVncywNCj4gLQkJCSAg ICAgIGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwNCj4gLQkJCSAgICAgIGVudW0gbXRrX2RkcF9j b21wX2lkIG5leHQpOw0KPiAtdm9pZCBtdGtfZGRwX3JlbW92ZV9jb21wX2Zyb21fcGF0aCh2b2lk IF9faW9tZW0gKmNvbmZpZ19yZWdzLA0KPiAtCQkJCSAgIGVudW0gbXRrX2RkcF9jb21wX2lkIGN1 ciwNCj4gLQkJCQkgICBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0KTsNCj4gLQ0KPiAgc3RydWN0 IG10a19kaXNwX211dGV4ICptdGtfZGlzcF9tdXRleF9nZXQoc3RydWN0IGRldmljZSAqZGV2LCB1 bnNpZ25lZCBpbnQgaWQpOw0KPiAgaW50IG10a19kaXNwX211dGV4X3ByZXBhcmUoc3RydWN0IG10 a19kaXNwX211dGV4ICptdXRleCk7DQo+ICB2b2lkIG10a19kaXNwX211dGV4X2FkZF9jb21wKHN0 cnVjdCBtdGtfZGlzcF9tdXRleCAqbXV0ZXgsDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvbXRrX2RybV9kcnYuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtf ZHJtX2Rydi5jDQo+IGluZGV4IDhlMmQzY2I2MmFkNS4uMjA4ZjljNTI1NmVmIDEwMDY0NA0KPiAt LS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kcnYuYw0KPiArKysgYi9kcml2 ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kcnYuYw0KPiBAQCAtMTAsNiArMTAsNyBAQA0K PiAgI2luY2x1ZGUgPGxpbnV4L29mX2FkZHJlc3MuaD4NCj4gICNpbmNsdWRlIDxsaW51eC9vZl9w bGF0Zm9ybS5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4NCj4gKyNpbmNsdWRl IDxsaW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmg+DQo+ICAjaW5jbHVkZSA8bGludXgvZG1h LW1hcHBpbmcuaD4NCj4gIA0KPiAgI2luY2x1ZGUgPGRybS9kcm1fYXRvbWljLmg+DQo+IEBAIC00 MjUsNyArNDI2LDYgQEAgc3RhdGljIGludCBtdGtfZHJtX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9k ZXZpY2UgKnBkZXYpDQo+ICB7DQo+ICAJc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsN Cj4gIAlzdHJ1Y3QgbXRrX2RybV9wcml2YXRlICpwcml2YXRlOw0KPiAtCXN0cnVjdCByZXNvdXJj ZSAqbWVtOw0KPiAgCXN0cnVjdCBkZXZpY2Vfbm9kZSAqbm9kZTsNCj4gIAlzdHJ1Y3QgY29tcG9u ZW50X21hdGNoICptYXRjaCA9IE5VTEw7DQo+ICAJaW50IHJldDsNCj4gQEAgLTQzNiwxNCArNDM2 LDEwIEBAIHN0YXRpYyBpbnQgbXRrX2RybV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpw ZGV2KQ0KPiAgCQlyZXR1cm4gLUVOT01FTTsNCj4gIA0KPiAgCXByaXZhdGUtPmRhdGEgPSBvZl9k ZXZpY2VfZ2V0X21hdGNoX2RhdGEoZGV2KTsNCj4gLQ0KPiAtCW1lbSA9IHBsYXRmb3JtX2dldF9y ZXNvdXJjZShwZGV2LCBJT1JFU09VUkNFX01FTSwgMCk7DQo+IC0JcHJpdmF0ZS0+Y29uZmlnX3Jl Z3MgPSBkZXZtX2lvcmVtYXBfcmVzb3VyY2UoZGV2LCBtZW0pOw0KPiAtCWlmIChJU19FUlIocHJp dmF0ZS0+Y29uZmlnX3JlZ3MpKSB7DQo+IC0JCXJldCA9IFBUUl9FUlIocHJpdmF0ZS0+Y29uZmln X3JlZ3MpOw0KPiAtCQlkZXZfZXJyKGRldiwgIkZhaWxlZCB0byBpb3JlbWFwIG1tc3lzLWNvbmZp ZyByZXNvdXJjZTogJWRcbiIsDQo+IC0JCQlyZXQpOw0KPiAtCQlyZXR1cm4gcmV0Ow0KPiArCXBy aXZhdGUtPm1tc3lzX2RldiA9IGRldi0+cGFyZW50Ow0KPiArCWlmICghcHJpdmF0ZS0+bW1zeXNf ZGV2KSB7DQo+ICsJCWRldl9lcnIoZGV2LCAiRmFpbGVkIHRvIGdldCBNTVNZUyBkZXZpY2VcbiIp Ow0KPiArCQlyZXR1cm4gLUVOT0RFVjsNCj4gIAl9DQo+ICANCj4gIAkvKiBJdGVyYXRlIG92ZXIg c2libGluZyBESVNQIGZ1bmN0aW9uIGJsb2NrcyAqLw0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2LmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kcnYuaA0KPiBpbmRleCAxN2JjOTliOWY1ZDQuLmI1YmU2M2U1MzE3NiAxMDA2NDQN Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2LmgNCj4gKysrIGIv ZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZHJ2LmgNCj4gQEAgLTM5LDcgKzM5LDcg QEAgc3RydWN0IG10a19kcm1fcHJpdmF0ZSB7DQo+ICANCj4gIAlzdHJ1Y3QgZGV2aWNlX25vZGUg Km11dGV4X25vZGU7DQo+ICAJc3RydWN0IGRldmljZSAqbXV0ZXhfZGV2Ow0KPiAtCXZvaWQgX19p b21lbSAqY29uZmlnX3JlZ3M7DQo+ICsJc3RydWN0IGRldmljZSAqbW1zeXNfZGV2Ow0KPiAgCXN0 cnVjdCBkZXZpY2Vfbm9kZSAqY29tcF9ub2RlW0REUF9DT01QT05FTlRfSURfTUFYXTsNCj4gIAlz dHJ1Y3QgbXRrX2RkcF9jb21wICpkZHBfY29tcFtERFBfQ09NUE9ORU5UX0lEX01BWF07DQo+ICAJ Y29uc3Qgc3RydWN0IG10a19tbXN5c19kcml2ZXJfZGF0YSAqZGF0YTsNCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5jIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsv bXRrLW1tc3lzLmMNCj4gaW5kZXggNDczY2RmNzMyZmI1Li5iYjk5YTA1ZmIyNzggMTAwNjQ0DQo+ IC0tLSBhL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5jDQo+ICsrKyBiL2RyaXZlcnMv c29jL21lZGlhdGVrL210ay1tbXN5cy5jDQo+IEBAIC01LDE0ICs1LDgxIEBADQo+ICAgKi8NCj4g IA0KPiAgI2luY2x1ZGUgPGxpbnV4L2Nsay1wcm92aWRlci5oPg0KPiArI2luY2x1ZGUgPGxpbnV4 L2RldmljZS5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L29mX2RldmljZS5oPg0KPiAgI2luY2x1ZGUg PGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPg0KPiArI2luY2x1ZGUgPGxpbnV4L3NvYy9tZWRpYXRl ay9tdGstbW1zeXMuaD4NCj4gIA0KPiAgI2luY2x1ZGUgIi4uLy4uL2Nsay9tZWRpYXRlay9jbGst Z2F0ZS5oIg0KPiAgI2luY2x1ZGUgIi4uLy4uL2Nsay9tZWRpYXRlay9jbGstbXRrLmgiDQo+ICsj aW5jbHVkZSAiLi4vLi4vZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcC5oIg0KPiArI2luY2x1 ZGUgIi4uLy4uL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5oIg0KPiAgDQo+ICAj aW5jbHVkZSA8ZHQtYmluZGluZ3MvY2xvY2svbXQ4MTczLWNsay5oPg0KPiAgDQo+ICsjZGVmaW5l IERJU1BfUkVHX0NPTkZJR19ESVNQX09WTDBfTU9VVF9FTgkweDA0MA0KPiArI2RlZmluZSBESVNQ X1JFR19DT05GSUdfRElTUF9PVkwxX01PVVRfRU4JMHgwNDQNCj4gKyNkZWZpbmUgRElTUF9SRUdf Q09ORklHX0RJU1BfT0RfTU9VVF9FTgkJMHgwNDgNCj4gKyNkZWZpbmUgRElTUF9SRUdfQ09ORklH X0RJU1BfR0FNTUFfTU9VVF9FTgkweDA0Yw0KPiArI2RlZmluZSBESVNQX1JFR19DT05GSUdfRElT UF9VRk9FX01PVVRfRU4JMHgwNTANCj4gKyNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RJU1BfQ09M T1IwX1NFTF9JTgkweDA4NA0KPiArI2RlZmluZSBESVNQX1JFR19DT05GSUdfRElTUF9DT0xPUjFf U0VMX0lOCTB4MDg4DQo+ICsjZGVmaW5lIERJU1BfUkVHX0NPTkZJR19EU0lFX1NFTF9JTgkJMHgw YTQNCj4gKyNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RTSU9fU0VMX0lOCQkweDBhOA0KPiArI2Rl ZmluZSBESVNQX1JFR19DT05GSUdfRFBJX1NFTF9JTgkJMHgwYWMNCj4gKyNkZWZpbmUgRElTUF9S RUdfQ09ORklHX0RJU1BfUkRNQTJfU09VVAkJMHgwYjgNCj4gKyNkZWZpbmUgRElTUF9SRUdfQ09O RklHX0RJU1BfUkRNQTBfU09VVF9FTgkweDBjNA0KPiArI2RlZmluZSBESVNQX1JFR19DT05GSUdf RElTUF9SRE1BMV9TT1VUX0VOCTB4MGM4DQo+ICsjZGVmaW5lIERJU1BfUkVHX0NPTkZJR19NTVNZ U19DR19DT04wCQkweDEwMA0KPiArDQo+ICsjZGVmaW5lIERJU1BfUkVHX0NPTkZJR19ESVNQX09W TF9NT1VUX0VOCTB4MDMwDQo+ICsjZGVmaW5lIERJU1BfUkVHX0NPTkZJR19PVVRfU0VMCQkJMHgw NGMNCj4gKyNkZWZpbmUgRElTUF9SRUdfQ09ORklHX0RTSV9TRUwJCQkweDA1MA0KPiArI2RlZmlu ZSBESVNQX1JFR19DT05GSUdfRFBJX1NFTAkJCTB4MDY0DQo+ICsNCj4gKyNkZWZpbmUgT1ZMMF9N T1VUX0VOX0NPTE9SMAkJCTB4MQ0KPiArI2RlZmluZSBPRF9NT1VUX0VOX1JETUEwCQkJMHgxDQo+ ICsjZGVmaW5lIE9EMV9NT1VUX0VOX1JETUExCQkJQklUKDE2KQ0KPiArI2RlZmluZSBVRk9FX01P VVRfRU5fRFNJMAkJCTB4MQ0KPiArI2RlZmluZSBDT0xPUjBfU0VMX0lOX09WTDAJCQkweDENCj4g KyNkZWZpbmUgT1ZMMV9NT1VUX0VOX0NPTE9SMQkJCTB4MQ0KPiArI2RlZmluZSBHQU1NQV9NT1VU X0VOX1JETUExCQkJMHgxDQo+ICsjZGVmaW5lIFJETUEwX1NPVVRfRFBJMAkJCQkweDINCj4gKyNk ZWZpbmUgUkRNQTBfU09VVF9EUEkxCQkJCTB4Mw0KPiArI2RlZmluZSBSRE1BMF9TT1VUX0RTSTEJ CQkJMHgxDQo+ICsjZGVmaW5lIFJETUEwX1NPVVRfRFNJMgkJCQkweDQNCj4gKyNkZWZpbmUgUkRN QTBfU09VVF9EU0kzCQkJCTB4NQ0KPiArI2RlZmluZSBSRE1BMV9TT1VUX0RQSTAJCQkJMHgyDQo+ ICsjZGVmaW5lIFJETUExX1NPVVRfRFBJMQkJCQkweDMNCj4gKyNkZWZpbmUgUkRNQTFfU09VVF9E U0kxCQkJCTB4MQ0KPiArI2RlZmluZSBSRE1BMV9TT1VUX0RTSTIJCQkJMHg0DQo+ICsjZGVmaW5l IFJETUExX1NPVVRfRFNJMwkJCQkweDUNCj4gKyNkZWZpbmUgUkRNQTJfU09VVF9EUEkwCQkJCTB4 Mg0KPiArI2RlZmluZSBSRE1BMl9TT1VUX0RQSTEJCQkJMHgzDQo+ICsjZGVmaW5lIFJETUEyX1NP VVRfRFNJMQkJCQkweDENCj4gKyNkZWZpbmUgUkRNQTJfU09VVF9EU0kyCQkJCTB4NA0KPiArI2Rl ZmluZSBSRE1BMl9TT1VUX0RTSTMJCQkJMHg1DQo+ICsjZGVmaW5lIERQSTBfU0VMX0lOX1JETUEx CQkJMHgxDQo+ICsjZGVmaW5lIERQSTBfU0VMX0lOX1JETUEyCQkJMHgzDQo+ICsjZGVmaW5lIERQ STFfU0VMX0lOX1JETUExCQkJKDB4MSA8PCA4KQ0KPiArI2RlZmluZSBEUEkxX1NFTF9JTl9SRE1B MgkJCSgweDMgPDwgOCkNCj4gKyNkZWZpbmUgRFNJMF9TRUxfSU5fUkRNQTEJCQkweDENCj4gKyNk ZWZpbmUgRFNJMF9TRUxfSU5fUkRNQTIJCQkweDQNCj4gKyNkZWZpbmUgRFNJMV9TRUxfSU5fUkRN QTEJCQkweDENCj4gKyNkZWZpbmUgRFNJMV9TRUxfSU5fUkRNQTIJCQkweDQNCj4gKyNkZWZpbmUg RFNJMl9TRUxfSU5fUkRNQTEJCQkoMHgxIDw8IDE2KQ0KPiArI2RlZmluZSBEU0kyX1NFTF9JTl9S RE1BMgkJCSgweDQgPDwgMTYpDQo+ICsjZGVmaW5lIERTSTNfU0VMX0lOX1JETUExCQkJKDB4MSA8 PCAxNikNCj4gKyNkZWZpbmUgRFNJM19TRUxfSU5fUkRNQTIJCQkoMHg0IDw8IDE2KQ0KPiArI2Rl ZmluZSBDT0xPUjFfU0VMX0lOX09WTDEJCQkweDENCj4gKw0KPiArI2RlZmluZSBPVkxfTU9VVF9F Tl9SRE1BCQkJMHgxDQo+ICsjZGVmaW5lIEJMU19UT19EU0lfUkRNQTFfVE9fRFBJMQkJMHg4DQo+ ICsjZGVmaW5lIEJMU19UT19EUElfUkRNQTFfVE9fRFNJCQkJMHgyDQo+ICsjZGVmaW5lIERTSV9T RUxfSU5fQkxTCQkJCTB4MA0KPiArI2RlZmluZSBEUElfU0VMX0lOX0JMUwkJCQkweDANCj4gKyNk ZWZpbmUgRFNJX1NFTF9JTl9SRE1BCQkJCTB4MQ0KPiArDQo+ICBzdGF0aWMgY29uc3Qgc3RydWN0 IG10a19nYXRlX3JlZ3MgbW0wX2NnX3JlZ3MgPSB7DQo+ICAJLnNldF9vZnMgPSAweDAxMDQsDQo+ ICAJLmNscl9vZnMgPSAweDAxMDgsDQo+IEBAIC0xMTAsMTMgKzE3NywyMjMgQEAgc3RhdGljIGNv bnN0IHN0cnVjdCBtdGtfbW1zeXNfZHJpdmVyX2RhdGEgbXQ4MTczX21tc3lzX2RyaXZlcl9kYXRh ID0gew0KPiAgCS5nYXRlc19udW0gPSBBUlJBWV9TSVpFKG10ODE3M19tbV9jbGtzKSwNCj4gIH07 DQo+ICANCj4gK3N0YXRpYyB1bnNpZ25lZCBpbnQgbXRrX21tc3lzX2RkcF9tb3V0X2VuKGVudW0g bXRrX2RkcF9jb21wX2lkIGN1ciwNCj4gKwkJCQkJICBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0 LA0KPiArCQkJCQkgIHVuc2lnbmVkIGludCAqYWRkcikNCj4gK3sNCj4gKwl1bnNpZ25lZCBpbnQg dmFsdWU7DQo+ICsNCj4gKwlpZiAoY3VyID09IEREUF9DT01QT05FTlRfT1ZMMCAmJiBuZXh0ID09 IEREUF9DT01QT05FTlRfQ09MT1IwKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJ U1BfT1ZMMF9NT1VUX0VOOw0KPiArCQl2YWx1ZSA9IE9WTDBfTU9VVF9FTl9DT0xPUjA7DQo+ICsJ fSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9PVkwwICYmIG5leHQgPT0gRERQX0NPTVBP TkVOVF9SRE1BMCkgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX09WTF9NT1VU X0VOOw0KPiArCQl2YWx1ZSA9IE9WTF9NT1VUX0VOX1JETUE7DQo+ICsJfSBlbHNlIGlmIChjdXIg PT0gRERQX0NPTVBPTkVOVF9PRDAgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX1JETUEwKSB7DQo+ ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfT0RfTU9VVF9FTjsNCj4gKwkJdmFsdWUg PSBPRF9NT1VUX0VOX1JETUEwOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRf VUZPRSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMCkgew0KPiArCQkqYWRkciA9IERJU1Bf UkVHX0NPTkZJR19ESVNQX1VGT0VfTU9VVF9FTjsNCj4gKwkJdmFsdWUgPSBVRk9FX01PVVRfRU5f RFNJMDsNCj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX09WTDEgJiYgbmV4dCA9 PSBERFBfQ09NUE9ORU5UX0NPTE9SMSkgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19E SVNQX09WTDFfTU9VVF9FTjsNCj4gKwkJdmFsdWUgPSBPVkwxX01PVVRfRU5fQ09MT1IxOw0KPiAr CX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfR0FNTUEgJiYgbmV4dCA9PSBERFBfQ09N UE9ORU5UX1JETUExKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfR0FNTUFf TU9VVF9FTjsNCj4gKwkJdmFsdWUgPSBHQU1NQV9NT1VUX0VOX1JETUExOw0KPiArCX0gZWxzZSBp ZiAoY3VyID09IEREUF9DT01QT05FTlRfT0QxICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9SRE1B MSkgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX09EX01PVVRfRU47DQo+ICsJ CXZhbHVlID0gT0QxX01PVVRfRU5fUkRNQTE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NP TVBPTkVOVF9SRE1BMCAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMCkgew0KPiArCQkqYWRk ciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUEwX1NPVVRfRU47DQo+ICsJCXZhbHVlID0gUkRN QTBfU09VVF9EUEkwOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTAg JiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTEpIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19D T05GSUdfRElTUF9SRE1BMF9TT1VUX0VOOw0KPiArCQl2YWx1ZSA9IFJETUEwX1NPVVRfRFBJMTsN Cj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEwICYmIG5leHQgPT0gRERQ X0NPTVBPTkVOVF9EU0kxKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRN QTBfU09VVF9FTjsNCj4gKwkJdmFsdWUgPSBSRE1BMF9TT1VUX0RTSTE7DQo+ICsJfSBlbHNlIGlm IChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMCAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJ Mikgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUEwX1NPVVRfRU47DQo+ ICsJCXZhbHVlID0gUkRNQTBfU09VVF9EU0kyOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9D T01QT05FTlRfUkRNQTAgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTMpIHsNCj4gKwkJKmFk ZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9SRE1BMF9TT1VUX0VOOw0KPiArCQl2YWx1ZSA9IFJE TUEwX1NPVVRfRFNJMzsNCj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEx ICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kxKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdf Q09ORklHX0RJU1BfUkRNQTFfU09VVF9FTjsNCj4gKwkJdmFsdWUgPSBSRE1BMV9TT1VUX0RTSTE7 DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IERE UF9DT01QT05FTlRfRFNJMikgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19ESVNQX1JE TUExX1NPVVRfRU47DQo+ICsJCXZhbHVlID0gUkRNQTFfU09VVF9EU0kyOw0KPiArCX0gZWxzZSBp ZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RT STMpIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9SRE1BMV9TT1VUX0VOOw0K PiArCQl2YWx1ZSA9IFJETUExX1NPVVRfRFNJMzsNCj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBf Q09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkwKSB7DQo+ICsJCSph ZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTFfU09VVF9FTjsNCj4gKwkJdmFsdWUgPSBS RE1BMV9TT1VUX0RQSTA7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1B MSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgew0KPiArCQkqYWRkciA9IERJU1BfUkVH X0NPTkZJR19ESVNQX1JETUExX1NPVVRfRU47DQo+ICsJCXZhbHVlID0gUkRNQTFfU09VVF9EUEkx Ow0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYgbmV4dCA9PSBE RFBfQ09NUE9ORU5UX0RQSTApIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9S RE1BMl9TT1VUOw0KPiArCQl2YWx1ZSA9IFJETUEyX1NPVVRfRFBJMDsNCj4gKwl9IGVsc2UgaWYg KGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkx KSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTJfU09VVDsNCj4gKwkJ dmFsdWUgPSBSRE1BMl9TT1VUX0RQSTE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBP TkVOVF9SRE1BMiAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMSkgew0KPiArCQkqYWRkciA9 IERJU1BfUkVHX0NPTkZJR19ESVNQX1JETUEyX1NPVVQ7DQo+ICsJCXZhbHVlID0gUkRNQTJfU09V VF9EU0kxOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYgbmV4 dCA9PSBERFBfQ09NUE9ORU5UX0RTSTIpIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdf RElTUF9SRE1BMl9TT1VUOw0KPiArCQl2YWx1ZSA9IFJETUEyX1NPVVRfRFNJMjsNCj4gKwl9IGVs c2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVO VF9EU0kzKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfUkRNQTJfU09VVDsN Cj4gKwkJdmFsdWUgPSBSRE1BMl9TT1VUX0RTSTM7DQo+ICsJfSBlbHNlIHsNCj4gKwkJdmFsdWUg PSAwOw0KPiArCX0NCj4gKw0KPiArCXJldHVybiB2YWx1ZTsNCj4gK30NCj4gKw0KPiArc3RhdGlj IHVuc2lnbmVkIGludCBtdGtfbW1zeXNfZGRwX3NlbF9pbihlbnVtIG10a19kZHBfY29tcF9pZCBj dXIsDQo+ICsJCQkJCSBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0LA0KPiArCQkJCQkgdW5zaWdu ZWQgaW50ICphZGRyKQ0KPiArew0KPiArCXVuc2lnbmVkIGludCB2YWx1ZTsNCj4gKw0KPiArCWlm IChjdXIgPT0gRERQX0NPTVBPTkVOVF9PVkwwICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9DT0xP UjApIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRElTUF9DT0xPUjBfU0VMX0lOOw0K PiArCQl2YWx1ZSA9IENPTE9SMF9TRUxfSU5fT1ZMMDsNCj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBE RFBfQ09NUE9ORU5UX1JETUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EUEkwKSB7DQo+ICsJ CSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RQSV9TRUxfSU47DQo+ICsJCXZhbHVlID0gRFBJMF9T RUxfSU5fUkRNQTE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMSAm JiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMSkgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NP TkZJR19EUElfU0VMX0lOOw0KPiArCQl2YWx1ZSA9IERQSTFfU0VMX0lOX1JETUExOw0KPiArCX0g ZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9O RU5UX0RTSTApIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFNJRV9TRUxfSU47DQo+ ICsJCXZhbHVlID0gRFNJMF9TRUxfSU5fUkRNQTE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQ X0NPTVBPTkVOVF9SRE1BMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMSkgew0KPiArCQkq YWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lPX1NFTF9JTjsNCj4gKwkJdmFsdWUgPSBEU0kxX1NF TF9JTl9SRE1BMTsNCj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUExICYm IG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kyKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09O RklHX0RTSUVfU0VMX0lOOw0KPiArCQl2YWx1ZSA9IERTSTJfU0VMX0lOX1JETUExOw0KPiArCX0g ZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9O RU5UX0RTSTMpIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05GSUdfRFNJT19TRUxfSU47DQo+ ICsJCXZhbHVlID0gRFNJM19TRUxfSU5fUkRNQTE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQ X0NPTVBPTkVOVF9SRE1BMiAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFBJMCkgew0KPiArCQkq YWRkciA9IERJU1BfUkVHX0NPTkZJR19EUElfU0VMX0lOOw0KPiArCQl2YWx1ZSA9IERQSTBfU0VM X0lOX1JETUEyOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTIgJiYg bmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTEpIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JFR19DT05G SUdfRFBJX1NFTF9JTjsNCj4gKwkJdmFsdWUgPSBEUEkxX1NFTF9JTl9SRE1BMjsNCj4gKwl9IGVs c2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVO VF9EU0kwKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RTSUVfU0VMX0lOOw0KPiAr CQl2YWx1ZSA9IERTSTBfU0VMX0lOX1JETUEyOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9D T01QT05FTlRfUkRNQTIgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTEpIHsNCj4gKwkJKmFk ZHIgPSBESVNQX1JFR19DT05GSUdfRFNJT19TRUxfSU47DQo+ICsJCXZhbHVlID0gRFNJMV9TRUxf SU5fUkRNQTI7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9SRE1BMiAmJiBu ZXh0ID09IEREUF9DT01QT05FTlRfRFNJMikgew0KPiArCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJ R19EU0lFX1NFTF9JTjsNCj4gKwkJdmFsdWUgPSBEU0kyX1NFTF9JTl9SRE1BMjsNCj4gKwl9IGVs c2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JETUEyICYmIG5leHQgPT0gRERQX0NPTVBPTkVO VF9EU0kzKSB7DQo+ICsJCSphZGRyID0gRElTUF9SRUdfQ09ORklHX0RTSUVfU0VMX0lOOw0KPiAr CQl2YWx1ZSA9IERTSTNfU0VMX0lOX1JETUEyOw0KPiArCX0gZWxzZSBpZiAoY3VyID09IEREUF9D T01QT05FTlRfT1ZMMSAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfQ09MT1IxKSB7DQo+ICsJCSph ZGRyID0gRElTUF9SRUdfQ09ORklHX0RJU1BfQ09MT1IxX1NFTF9JTjsNCj4gKwkJdmFsdWUgPSBD T0xPUjFfU0VMX0lOX09WTDE7DQo+ICsJfSBlbHNlIGlmIChjdXIgPT0gRERQX0NPTVBPTkVOVF9C TFMgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RTSTApIHsNCj4gKwkJKmFkZHIgPSBESVNQX1JF R19DT05GSUdfRFNJX1NFTDsNCj4gKwkJdmFsdWUgPSBEU0lfU0VMX0lOX0JMUzsNCj4gKwl9IGVs c2Ugew0KPiArCQl2YWx1ZSA9IDA7DQo+ICsJfQ0KPiArDQo+ICsJcmV0dXJuIHZhbHVlOw0KPiAr fQ0KPiArDQo+ICtzdGF0aWMgdm9pZCBtdGtfbW1zeXNfZGRwX3NvdXRfc2VsKHZvaWQgX19pb21l bSAqY29uZmlnX3JlZ3MsDQo+ICsJCQkJICAgZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLA0KPiAr CQkJCSAgIGVudW0gbXRrX2RkcF9jb21wX2lkIG5leHQpDQo+ICt7DQo+ICsJaWYgKGN1ciA9PSBE RFBfQ09NUE9ORU5UX0JMUyAmJiBuZXh0ID09IEREUF9DT01QT05FTlRfRFNJMCkgew0KPiArCQl3 cml0ZWxfcmVsYXhlZChCTFNfVE9fRFNJX1JETUExX1RPX0RQSTEsDQo+ICsJCQkgICAgICAgY29u ZmlnX3JlZ3MgKyBESVNQX1JFR19DT05GSUdfT1VUX1NFTCk7DQo+ICsJfSBlbHNlIGlmIChjdXIg PT0gRERQX0NPTVBPTkVOVF9CTFMgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTApIHsNCj4g KwkJd3JpdGVsX3JlbGF4ZWQoQkxTX1RPX0RQSV9SRE1BMV9UT19EU0ksDQo+ICsJCQkgICAgICAg Y29uZmlnX3JlZ3MgKyBESVNQX1JFR19DT05GSUdfT1VUX1NFTCk7DQo+ICsJCXdyaXRlbF9yZWxh eGVkKERTSV9TRUxfSU5fUkRNQSwNCj4gKwkJCSAgICAgICBjb25maWdfcmVncyArIERJU1BfUkVH X0NPTkZJR19EU0lfU0VMKTsNCj4gKwkJd3JpdGVsX3JlbGF4ZWQoRFBJX1NFTF9JTl9CTFMsDQo+ ICsJCQkgICAgICAgY29uZmlnX3JlZ3MgKyBESVNQX1JFR19DT05GSUdfRFBJX1NFTCk7DQo+ICsJ fQ0KPiArfQ0KPiArDQo+ICt2b2lkIG10a19tbXN5c19kZHBfY29ubmVjdChzdHJ1Y3QgZGV2aWNl ICpkZXYsDQo+ICsJCQkgICBlbnVtIG10a19kZHBfY29tcF9pZCBjdXIsDQo+ICsJCQkgICBlbnVt IG10a19kZHBfY29tcF9pZCBuZXh0KQ0KPiArew0KPiArCXZvaWQgX19pb21lbSAqY29uZmlnX3Jl Z3MgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gKwl1bnNpZ25lZCBpbnQgYWRkciwgdmFsdWUs IHJlZzsNCj4gKw0KPiArCXZhbHVlID0gbXRrX21tc3lzX2RkcF9tb3V0X2VuKGN1ciwgbmV4dCwg JmFkZHIpOw0KPiArCWlmICh2YWx1ZSkgew0KPiArCQlyZWcgPSByZWFkbF9yZWxheGVkKGNvbmZp Z19yZWdzICsgYWRkcikgfCB2YWx1ZTsNCj4gKwkJd3JpdGVsX3JlbGF4ZWQocmVnLCBjb25maWdf cmVncyArIGFkZHIpOw0KPiArCX0NCj4gKw0KPiArCW10a19tbXN5c19kZHBfc291dF9zZWwoY29u ZmlnX3JlZ3MsIGN1ciwgbmV4dCk7DQo+ICsNCj4gKwl2YWx1ZSA9IG10a19tbXN5c19kZHBfc2Vs X2luKGN1ciwgbmV4dCwgJmFkZHIpOw0KPiArCWlmICh2YWx1ZSkgew0KPiArCQlyZWcgPSByZWFk bF9yZWxheGVkKGNvbmZpZ19yZWdzICsgYWRkcikgfCB2YWx1ZTsNCj4gKwkJd3JpdGVsX3JlbGF4 ZWQocmVnLCBjb25maWdfcmVncyArIGFkZHIpOw0KPiArCX0NCj4gK30NCj4gKw0KPiArdm9pZCBt dGtfbW1zeXNfZGRwX2Rpc2Nvbm5lY3Qoc3RydWN0IGRldmljZSAqZGV2LA0KPiArCQkJICAgICAg ZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLA0KPiArCQkJICAgICAgZW51bSBtdGtfZGRwX2NvbXBf aWQgbmV4dCkNCj4gK3sNCj4gKwl2b2lkIF9faW9tZW0gKmNvbmZpZ19yZWdzID0gZGV2X2dldF9k cnZkYXRhKGRldik7DQo+ICsJdW5zaWduZWQgaW50IGFkZHIsIHZhbHVlLCByZWc7DQo+ICsNCj4g Kwl2YWx1ZSA9IG10a19tbXN5c19kZHBfbW91dF9lbihjdXIsIG5leHQsICZhZGRyKTsNCj4gKwlp ZiAodmFsdWUpIHsNCj4gKwkJcmVnID0gcmVhZGxfcmVsYXhlZChjb25maWdfcmVncyArIGFkZHIp ICYgfnZhbHVlOw0KPiArCQl3cml0ZWxfcmVsYXhlZChyZWcsIGNvbmZpZ19yZWdzICsgYWRkcik7 DQo+ICsJfQ0KPiArDQo+ICsJdmFsdWUgPSBtdGtfbW1zeXNfZGRwX3NlbF9pbihjdXIsIG5leHQs ICZhZGRyKTsNCj4gKwlpZiAodmFsdWUpIHsNCj4gKwkJcmVnID0gcmVhZGxfcmVsYXhlZChjb25m aWdfcmVncyArIGFkZHIpICYgfnZhbHVlOw0KPiArCQl3cml0ZWxfcmVsYXhlZChyZWcsIGNvbmZp Z19yZWdzICsgYWRkcik7DQo+ICsJfQ0KPiArfQ0KPiArDQo+ICBzdGF0aWMgaW50IG10a19tbXN5 c19wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQ0KPiAgew0KPiAgCXN0cnVjdCBk ZXZpY2Vfbm9kZSAqbm9kZSA9IHBkZXYtPmRldi5vZl9ub2RlOw0KPiAgCWNvbnN0IHN0cnVjdCBt dGtfbW1zeXNfZHJpdmVyX2RhdGEgKmRhdGE7DQo+ICAJc3RydWN0IGNsa19vbmVjZWxsX2RhdGEg KmNsa19kYXRhOw0KPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9ICZwZGV2LT5kZXY7DQo+ICsJdm9p ZCBfX2lvbWVtICpjb25maWdfcmVnczsNCj4gKwlzdHJ1Y3QgcmVzb3VyY2UgKm1lbTsNCj4gIAlp bnQgcmV0Ow0KPiAgDQo+ICsJbWVtID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVT T1VSQ0VfTUVNLCAwKTsNCj4gKwljb25maWdfcmVncyA9IGRldm1faW9yZW1hcF9yZXNvdXJjZShk ZXYsIG1lbSk7DQo+ICsJaWYgKElTX0VSUihjb25maWdfcmVncykpIHsNCj4gKwkJcmV0ID0gUFRS X0VSUihjb25maWdfcmVncyk7DQo+ICsJCWRldl9lcnIoZGV2LCAiRmFpbGVkIHRvIGlvcmVtYXAg bW1zeXMtY29uZmlnIHJlc291cmNlOiAlZFxuIiwNCj4gKwkJCXJldCk7DQo+ICsJCXJldHVybiBy ZXQ7DQo+ICsJfQ0KPiArDQo+ICsJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgY29uZmlnX3Jl Z3MpOw0KPiArDQo+ICAJY2xrX2RhdGEgPSBtdGtfYWxsb2NfY2xrX2RhdGEoQ0xLX01NX05SX0NM Syk7DQo+ICAJaWYgKCFjbGtfZGF0YSkNCj4gIAkJcmV0dXJuIC1FTk9NRU07DQo+IGRpZmYgLS1n aXQgYS9pbmNsdWRlL2xpbnV4L3NvYy9tZWRpYXRlay9tdGstbW1zeXMuaCBiL2luY2x1ZGUvbGlu dXgvc29jL21lZGlhdGVrL210ay1tbXN5cy5oDQo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+IGlu ZGV4IDAwMDAwMDAwMDAwMC4uN2JhYjVkOWEzZDMxDQo+IC0tLSAvZGV2L251bGwNCj4gKysrIGIv aW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmgNCj4gQEAgLTAsMCArMSwyMCBA QA0KPiArLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAtb25seSAqLw0KPiArLyoN Cj4gKyAqIENvcHlyaWdodCAoYykgMjAxNSBNZWRpYVRlayBJbmMuDQo+ICsgKi8NCj4gKw0KPiAr I2lmbmRlZiBfX01US19NTVNZU19IDQo+ICsjZGVmaW5lIF9fTVRLX01NU1lTX0gNCj4gKw0KPiAr ZW51bSBtdGtfZGRwX2NvbXBfaWQ7DQo+ICtzdHJ1Y3QgZGV2aWNlOw0KPiArDQo+ICt2b2lkIG10 a19tbXN5c19kZHBfY29ubmVjdChzdHJ1Y3QgZGV2aWNlICpkZXYsDQo+ICsJCQkgICBlbnVtIG10 a19kZHBfY29tcF9pZCBjdXIsDQo+ICsJCQkgICBlbnVtIG10a19kZHBfY29tcF9pZCBuZXh0KTsN Cj4gKw0KPiArdm9pZCBtdGtfbW1zeXNfZGRwX2Rpc2Nvbm5lY3Qoc3RydWN0IGRldmljZSAqZGV2 LA0KPiArCQkJICAgICAgZW51bSBtdGtfZGRwX2NvbXBfaWQgY3VyLA0KPiArCQkJICAgICAgZW51 bSBtdGtfZGRwX2NvbXBfaWQgbmV4dCk7DQo+ICsNCj4gKyNlbmRpZiAvKiBfX01US19NTVNZU19I ICovDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A573C3F2D2 for ; Tue, 3 Mar 2020 02:53:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 487752166E for ; Tue, 3 Mar 2020 02:53:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WJN+7cis"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IeIo2aX6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 487752166E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZxO/g0rgwJ3bCcRANZQLfx02qzQg2zck9NsKyyuC8vo=; b=WJN+7cis//0zz+ jQiuAwLiVRpwYnlf/60Mky/+ZfC+jEJgWAMW88qVxY+ryzcB86gHERpBoPXZBiSrxL4h9HNjriwnr 1kBy6uxBCaEhm+I5tgt40GoF3XtbnYwCtJ6abgu31FagwmFQbnvfnRpqLUF50BsRvh231pOR8/kXc vo2kzokLtH3rZgFZggPaERNE2V5RK+GZRa22KVyX0zT+JZJMu9YGC91CNFxhGfbIMFsiNBTdtOtv3 FMcfJd9o7WE+18zg3/ZP2lzB+yYZe3cIxWSRDr2h4xsf+QHKhR5wg7wYoAPlBXjkh19Dr8kUqUEfM i4xuJUW4X0EIDiYkgd6g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8xgJ-0001km-Tt; Tue, 03 Mar 2020 02:53:15 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8xgF-0001jr-5i; Tue, 03 Mar 2020 02:53:14 +0000 X-UUID: 1c99fba7df034dc0959891b560222937-20200302 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=8MBDjgDUG1Gbtx2Z1NxKuR7GRGFbh/9SkGfjXkEMHUw=; b=IeIo2aX6B6hzdgZR7OSwsGO8J2OV4ELKx5UoRec4UE8hmpilVkjxoealeRwzSh93H3QpYs2o69mSujGJZpO+Zeg6EqwWfsSTpCqaQnk+LnqkJWX2oT99B9NEQ78j8HRgZFpa1ei0nadx7ZgV0jJNFnyXSDfNz5QTnV6zM9+KCcs=; X-UUID: 1c99fba7df034dc0959891b560222937-20200302 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1413421758; Mon, 02 Mar 2020 18:53:01 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Mar 2020 18:54:15 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Mar 2020 10:51:52 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Mar 2020 10:50:23 +0800 Message-ID: <1583203972.12858.4.camel@mtksdaap41> Subject: Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device From: CK Hu To: Enric Balletbo i Serra Date: Tue, 3 Mar 2020 10:52:52 +0800 In-Reply-To: <20200302110128.2664251-5-enric.balletbo@collabora.com> References: <20200302110128.2664251-1-enric.balletbo@collabora.com> <20200302110128.2664251-5-enric.balletbo@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 00B7F2C20D55390349F22FE86D820093B19171414C8131AE81267416E6CBFF342000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200302_185311_246818_9DC30FEC X-CRM114-Status: GOOD ( 24.23 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Kate Stewart , Minghsiu Tsai , Andrew-CT Chen , airlied@linux.ie, mturquette@baylibre.com, dri-devel@lists.freedesktop.org, Richard Fontana , laurent.pinchart@ideasonboard.com, ulrich.hecht+renesas@gmail.com, Collabora Kernel ML , linux-clk@vger.kernel.org, Weiyi Lu , wens@csie.org, linux-arm-kernel@lists.infradead.org, mtk01761 , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Daniel Vetter , frank-w@public-files.de, Seiya Wang , sean.wang@mediatek.com, Houlong Wei , robh+dt@kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Matthias Brugger , Thomas Gleixner , Mauro Carvalho Chehab , Allison Randal , Matthias Brugger , sboyd@kernel.org, Greg Kroah-Hartman , rdunlap@infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, matthias.bgg@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Enric: On Mon, 2020-03-02 at 12:01 +0100, Enric Balletbo i Serra wrote: > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > Those functions will allow DRM driver and others to control the data > path routing. > Reviewed-by: CK Hu But what is the base of this series? When I apply this patch to 5.6-rc1, some error happen, the apply --reject result is In drivers/gpu/drm/mediatek/mtk_drm_crtc.c.rej diff a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c (rejected hunks) @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) } for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, - mtk_crtc->ddp_comp[i]->id, - mtk_crtc->ddp_comp[i + 1]->id); + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, + mtk_crtc->ddp_comp[i]->id, + mtk_crtc->ddp_comp[i + 1]->id); mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); } I's trivial for me to fix this conflicts, so you have better to notice what is the base of this series in cover latter. Regards, CK > Signed-off-by: Enric Balletbo i Serra > Reviewed-by: Matthias Brugger > --- > > Changes in v11: > - Select CONFIG_MTK_MMSYS (CK) > - Pass device pointer of mmsys device instead of config regs (CK) > > Changes in v10: > - Introduced a new patch to move routing control into mmsys driver. > - Removed the patch to use regmap as is not needed anymore. > > Changes in v9: None > Changes in v8: None > Changes in v7: None > > drivers/gpu/drm/mediatek/Kconfig | 1 + > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 ---------------------- > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > drivers/soc/mediatek/mtk-mmsys.c | 277 ++++++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > 8 files changed, 314 insertions(+), 282 deletions(-) > create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > > diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig > index fa5ffc4fe823..c420f5a3d33b 100644 > --- a/drivers/gpu/drm/mediatek/Kconfig > +++ b/drivers/gpu/drm/mediatek/Kconfig > @@ -11,6 +11,7 @@ config DRM_MEDIATEK > select DRM_MIPI_DSI > select DRM_PANEL > select MEMORY > + select MTK_MMSYS > select MTK_SMI > select VIDEOMODE_HELPERS > help > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index fd4042de12f2..f63a885e063c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,7 +29,7 @@ > * @enabled: records whether crtc_enable succeeded > * @planes: array of 4 drm_plane structures, one for each overlay plane > * @pending_planes: whether any plane has pending changes to be applied > - * @config_regs: memory mapped mmsys configuration register space > + * @mmsys_dev: pointer to the mmsys device for configuration registers > * @mutex: handle to one of the ten disp_mutex streams > * @ddp_comp_nr: number of components in ddp_comp > * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc > @@ -50,7 +51,7 @@ struct mtk_drm_crtc { > u32 cmdq_event; > #endif > > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct mtk_disp_mutex *mutex; > unsigned int ddp_comp_nr; > struct mtk_ddp_comp **ddp_comp; > @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_add_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > mtk_crtc->ddp_comp[i]->id); > mtk_disp_mutex_disable(mtk_crtc->mutex); > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_remove_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -758,7 +759,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (!mtk_crtc) > return -ENOMEM; > > - mtk_crtc->config_regs = priv->config_regs; > + mtk_crtc->mmsys_dev = priv->mmsys_dev; > mtk_crtc->ddp_comp_nr = path_len; > mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, > sizeof(*mtk_crtc->ddp_comp), > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index b885f60f474c..014c1bbe1df2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -13,26 +13,6 @@ > #include "mtk_drm_ddp.h" > #include "mtk_drm_ddp_comp.h" > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > @@ -94,48 +74,6 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > > struct mtk_disp_mutex { > int id; > @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - mtk_ddp_sout_sel(config_regs, cur, next); > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > index 827be424a148..6b691a57be4a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > @@ -12,13 +12,6 @@ struct regmap; > struct device; > struct mtk_disp_mutex; > > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); > int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); > void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 8e2d3cb62ad5..208f9c5256ef 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_drm_private *private; > - struct resource *mem; > struct device_node *node; > struct component_match *match = NULL; > int ret; > @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev) > return -ENOMEM; > > private->data = of_device_get_match_data(dev); > - > - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - private->config_regs = devm_ioremap_resource(dev, mem); > - if (IS_ERR(private->config_regs)) { > - ret = PTR_ERR(private->config_regs); > - dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > - ret); > - return ret; > + private->mmsys_dev = dev->parent; > + if (!private->mmsys_dev) { > + dev_err(dev, "Failed to get MMSYS device\n"); > + return -ENODEV; > } > > /* Iterate over sibling DISP function blocks */ > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 17bc99b9f5d4..b5be63e53176 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -39,7 +39,7 @@ struct mtk_drm_private { > > struct device_node *mutex_node; > struct device *mutex_dev; > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; > struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; > const struct mtk_mmsys_driver_data *data; > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 473cdf732fb5..bb99a05fb278 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,14 +5,81 @@ > */ > > #include > +#include > #include > #include > +#include > > #include "../../clk/mediatek/clk-gate.h" > #include "../../clk/mediatek/clk-mtk.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > #include > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > static const struct mtk_gate_regs mm0_cg_regs = { > .set_ofs = 0x0104, > .clr_ofs = 0x0108, > @@ -110,13 +177,223 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .gates_num = ARRAY_SIZE(mt8173_mm_clks), > }; > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > struct device_node *node = pdev->dev.of_node; > const struct mtk_mmsys_driver_data *data; > struct clk_onecell_data *clk_data; > + struct device *dev = &pdev->dev; > + void __iomem *config_regs; > + struct resource *mem; > int ret; > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + config_regs = devm_ioremap_resource(dev, mem); > + if (IS_ERR(config_regs)) { > + ret = PTR_ERR(config_regs); > + dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > + ret); > + return ret; > + } > + > + platform_set_drvdata(pdev, config_regs); > + > clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); > if (!clk_data) > return -ENOMEM; > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > new file mode 100644 > index 000000000000..7bab5d9a3d31 > --- /dev/null > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + */ > + > +#ifndef __MTK_MMSYS_H > +#define __MTK_MMSYS_H > + > +enum mtk_ddp_comp_id; > +struct device; > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +#endif /* __MTK_MMSYS_H */ _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D381C3F2D2 for ; Tue, 3 Mar 2020 02:53:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB56921D56 for ; Tue, 3 Mar 2020 02:53:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EQs+Lxl2"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IeIo2aX6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB56921D56 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+c3xAlTz75YC6a3pd7zHExKFCLsjEZ6SBl3p2IRmb5k=; b=EQs+Lxl2IlFOIc ROhx87GTFvW3jahO5XNrYZvTVbclQQzVcx2Bm2eKUQ9LJO9D2+xy1uzK6GolbQJzTbyI17DExYP3/ dqCY7jN7PgYS7p5I/d4KlhxLV5VqxivXS//u/nQreDwWFzYW94yOfcsx3dyM6ZUAV0boN4oeRx6sn 3FpFXB5qjUGK4uCaFAGXMm/vcZqKhpIl2SAefIH0zkLl/mHWW0OFC2Tdd0jGuh3cxZibKoAtvJD17 pzpfRoGNDh7h4iFnZNjlAwQGecR4Q2h9QzLrRJUoHliF7Tf954EAd/0YnOGvu+zv58SNtKROAkdyE zV7HDAwTVrNsq6DxWrxA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8xgL-0001lX-0l; Tue, 03 Mar 2020 02:53:17 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1j8xgF-0001jr-5i; Tue, 03 Mar 2020 02:53:14 +0000 X-UUID: 1c99fba7df034dc0959891b560222937-20200302 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=8MBDjgDUG1Gbtx2Z1NxKuR7GRGFbh/9SkGfjXkEMHUw=; b=IeIo2aX6B6hzdgZR7OSwsGO8J2OV4ELKx5UoRec4UE8hmpilVkjxoealeRwzSh93H3QpYs2o69mSujGJZpO+Zeg6EqwWfsSTpCqaQnk+LnqkJWX2oT99B9NEQ78j8HRgZFpa1ei0nadx7ZgV0jJNFnyXSDfNz5QTnV6zM9+KCcs=; X-UUID: 1c99fba7df034dc0959891b560222937-20200302 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1413421758; Mon, 02 Mar 2020 18:53:01 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 2 Mar 2020 18:54:15 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Mar 2020 10:51:52 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Mar 2020 10:50:23 +0800 Message-ID: <1583203972.12858.4.camel@mtksdaap41> Subject: Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device From: CK Hu To: Enric Balletbo i Serra Date: Tue, 3 Mar 2020 10:52:52 +0800 In-Reply-To: <20200302110128.2664251-5-enric.balletbo@collabora.com> References: <20200302110128.2664251-1-enric.balletbo@collabora.com> <20200302110128.2664251-5-enric.balletbo@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 00B7F2C20D55390349F22FE86D820093B19171414C8131AE81267416E6CBFF342000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200302_185311_246818_9DC30FEC X-CRM114-Status: GOOD ( 24.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Kate Stewart , Minghsiu Tsai , Andrew-CT Chen , airlied@linux.ie, mturquette@baylibre.com, dri-devel@lists.freedesktop.org, Richard Fontana , laurent.pinchart@ideasonboard.com, ulrich.hecht+renesas@gmail.com, Collabora Kernel ML , linux-clk@vger.kernel.org, Weiyi Lu , wens@csie.org, linux-arm-kernel@lists.infradead.org, mtk01761 , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Daniel Vetter , frank-w@public-files.de, Seiya Wang , sean.wang@mediatek.com, Houlong Wei , robh+dt@kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Matthias Brugger , Thomas Gleixner , Mauro Carvalho Chehab , Allison Randal , Matthias Brugger , sboyd@kernel.org, Greg Kroah-Hartman , rdunlap@infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, matthias.bgg@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Enric: On Mon, 2020-03-02 at 12:01 +0100, Enric Balletbo i Serra wrote: > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > Those functions will allow DRM driver and others to control the data > path routing. > Reviewed-by: CK Hu But what is the base of this series? When I apply this patch to 5.6-rc1, some error happen, the apply --reject result is In drivers/gpu/drm/mediatek/mtk_drm_crtc.c.rej diff a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c (rejected hunks) @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) } for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, - mtk_crtc->ddp_comp[i]->id, - mtk_crtc->ddp_comp[i + 1]->id); + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, + mtk_crtc->ddp_comp[i]->id, + mtk_crtc->ddp_comp[i + 1]->id); mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); } I's trivial for me to fix this conflicts, so you have better to notice what is the base of this series in cover latter. Regards, CK > Signed-off-by: Enric Balletbo i Serra > Reviewed-by: Matthias Brugger > --- > > Changes in v11: > - Select CONFIG_MTK_MMSYS (CK) > - Pass device pointer of mmsys device instead of config regs (CK) > > Changes in v10: > - Introduced a new patch to move routing control into mmsys driver. > - Removed the patch to use regmap as is not needed anymore. > > Changes in v9: None > Changes in v8: None > Changes in v7: None > > drivers/gpu/drm/mediatek/Kconfig | 1 + > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 ---------------------- > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > drivers/soc/mediatek/mtk-mmsys.c | 277 ++++++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > 8 files changed, 314 insertions(+), 282 deletions(-) > create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > > diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig > index fa5ffc4fe823..c420f5a3d33b 100644 > --- a/drivers/gpu/drm/mediatek/Kconfig > +++ b/drivers/gpu/drm/mediatek/Kconfig > @@ -11,6 +11,7 @@ config DRM_MEDIATEK > select DRM_MIPI_DSI > select DRM_PANEL > select MEMORY > + select MTK_MMSYS > select MTK_SMI > select VIDEOMODE_HELPERS > help > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index fd4042de12f2..f63a885e063c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,7 +29,7 @@ > * @enabled: records whether crtc_enable succeeded > * @planes: array of 4 drm_plane structures, one for each overlay plane > * @pending_planes: whether any plane has pending changes to be applied > - * @config_regs: memory mapped mmsys configuration register space > + * @mmsys_dev: pointer to the mmsys device for configuration registers > * @mutex: handle to one of the ten disp_mutex streams > * @ddp_comp_nr: number of components in ddp_comp > * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc > @@ -50,7 +51,7 @@ struct mtk_drm_crtc { > u32 cmdq_event; > #endif > > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct mtk_disp_mutex *mutex; > unsigned int ddp_comp_nr; > struct mtk_ddp_comp **ddp_comp; > @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_add_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > mtk_crtc->ddp_comp[i]->id); > mtk_disp_mutex_disable(mtk_crtc->mutex); > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_remove_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -758,7 +759,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (!mtk_crtc) > return -ENOMEM; > > - mtk_crtc->config_regs = priv->config_regs; > + mtk_crtc->mmsys_dev = priv->mmsys_dev; > mtk_crtc->ddp_comp_nr = path_len; > mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, > sizeof(*mtk_crtc->ddp_comp), > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index b885f60f474c..014c1bbe1df2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -13,26 +13,6 @@ > #include "mtk_drm_ddp.h" > #include "mtk_drm_ddp_comp.h" > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > @@ -94,48 +74,6 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > > struct mtk_disp_mutex { > int id; > @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - mtk_ddp_sout_sel(config_regs, cur, next); > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > index 827be424a148..6b691a57be4a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > @@ -12,13 +12,6 @@ struct regmap; > struct device; > struct mtk_disp_mutex; > > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); > int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); > void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 8e2d3cb62ad5..208f9c5256ef 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_drm_private *private; > - struct resource *mem; > struct device_node *node; > struct component_match *match = NULL; > int ret; > @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev) > return -ENOMEM; > > private->data = of_device_get_match_data(dev); > - > - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - private->config_regs = devm_ioremap_resource(dev, mem); > - if (IS_ERR(private->config_regs)) { > - ret = PTR_ERR(private->config_regs); > - dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > - ret); > - return ret; > + private->mmsys_dev = dev->parent; > + if (!private->mmsys_dev) { > + dev_err(dev, "Failed to get MMSYS device\n"); > + return -ENODEV; > } > > /* Iterate over sibling DISP function blocks */ > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 17bc99b9f5d4..b5be63e53176 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -39,7 +39,7 @@ struct mtk_drm_private { > > struct device_node *mutex_node; > struct device *mutex_dev; > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; > struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; > const struct mtk_mmsys_driver_data *data; > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 473cdf732fb5..bb99a05fb278 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,14 +5,81 @@ > */ > > #include > +#include > #include > #include > +#include > > #include "../../clk/mediatek/clk-gate.h" > #include "../../clk/mediatek/clk-mtk.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > #include > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > static const struct mtk_gate_regs mm0_cg_regs = { > .set_ofs = 0x0104, > .clr_ofs = 0x0108, > @@ -110,13 +177,223 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .gates_num = ARRAY_SIZE(mt8173_mm_clks), > }; > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > struct device_node *node = pdev->dev.of_node; > const struct mtk_mmsys_driver_data *data; > struct clk_onecell_data *clk_data; > + struct device *dev = &pdev->dev; > + void __iomem *config_regs; > + struct resource *mem; > int ret; > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + config_regs = devm_ioremap_resource(dev, mem); > + if (IS_ERR(config_regs)) { > + ret = PTR_ERR(config_regs); > + dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > + ret); > + return ret; > + } > + > + platform_set_drvdata(pdev, config_regs); > + > clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); > if (!clk_data) > return -ENOMEM; > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > new file mode 100644 > index 000000000000..7bab5d9a3d31 > --- /dev/null > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + */ > + > +#ifndef __MTK_MMSYS_H > +#define __MTK_MMSYS_H > + > +enum mtk_ddp_comp_id; > +struct device; > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +#endif /* __MTK_MMSYS_H */ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB28CC3F2CD for ; Tue, 3 Mar 2020 02:53:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80D722166E for ; Tue, 3 Mar 2020 02:53:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IeIo2aX6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80D722166E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 18A246E965; Tue, 3 Mar 2020 02:53:13 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by gabe.freedesktop.org (Postfix) with ESMTP id E3FEB6E965 for ; Tue, 3 Mar 2020 02:53:10 +0000 (UTC) X-UUID: 171917e35e774b8f97a5fdb24639db00-20200303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=8MBDjgDUG1Gbtx2Z1NxKuR7GRGFbh/9SkGfjXkEMHUw=; b=IeIo2aX6B6hzdgZR7OSwsGO8J2OV4ELKx5UoRec4UE8hmpilVkjxoealeRwzSh93H3QpYs2o69mSujGJZpO+Zeg6EqwWfsSTpCqaQnk+LnqkJWX2oT99B9NEQ78j8HRgZFpa1ei0nadx7ZgV0jJNFnyXSDfNz5QTnV6zM9+KCcs=; X-UUID: 171917e35e774b8f97a5fdb24639db00-20200303 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2143834874; Tue, 03 Mar 2020 10:53:05 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 3 Mar 2020 10:51:52 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 3 Mar 2020 10:50:23 +0800 Message-ID: <1583203972.12858.4.camel@mtksdaap41> Subject: Re: [PATCH v11 4/5] soc / drm: mediatek: Move routing control to mmsys device From: CK Hu To: Enric Balletbo i Serra Date: Tue, 3 Mar 2020 10:52:52 +0800 In-Reply-To: <20200302110128.2664251-5-enric.balletbo@collabora.com> References: <20200302110128.2664251-1-enric.balletbo@collabora.com> <20200302110128.2664251-5-enric.balletbo@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 00B7F2C20D55390349F22FE86D820093B19171414C8131AE81267416E6CBFF342000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Kate Stewart , Minghsiu Tsai , Andrew-CT Chen , airlied@linux.ie, mturquette@baylibre.com, dri-devel@lists.freedesktop.org, Richard Fontana , laurent.pinchart@ideasonboard.com, ulrich.hecht+renesas@gmail.com, Collabora Kernel ML , linux-clk@vger.kernel.org, Weiyi Lu , wens@csie.org, linux-arm-kernel@lists.infradead.org, mtk01761 , linux-media@vger.kernel.org, devicetree@vger.kernel.org, frank-w@public-files.de, Seiya Wang , sean.wang@mediatek.com, Houlong Wei , robh+dt@kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Matthias Brugger , Thomas Gleixner , Mauro Carvalho Chehab , Allison Randal , Matthias Brugger , sboyd@kernel.org, Greg Kroah-Hartman , rdunlap@infradead.org, linux-kernel@vger.kernel.org, matthias.bgg@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Enric: On Mon, 2020-03-02 at 12:01 +0100, Enric Balletbo i Serra wrote: > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). > Those functions will allow DRM driver and others to control the data > path routing. > Reviewed-by: CK Hu But what is the base of this series? When I apply this patch to 5.6-rc1, some error happen, the apply --reject result is In drivers/gpu/drm/mediatek/mtk_drm_crtc.c.rej diff a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c (rejected hunks) @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) } for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, - mtk_crtc->ddp_comp[i]->id, - mtk_crtc->ddp_comp[i + 1]->id); + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, + mtk_crtc->ddp_comp[i]->id, + mtk_crtc->ddp_comp[i + 1]->id); mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); } I's trivial for me to fix this conflicts, so you have better to notice what is the base of this series in cover latter. Regards, CK > Signed-off-by: Enric Balletbo i Serra > Reviewed-by: Matthias Brugger > --- > > Changes in v11: > - Select CONFIG_MTK_MMSYS (CK) > - Pass device pointer of mmsys device instead of config regs (CK) > > Changes in v10: > - Introduced a new patch to move routing control into mmsys driver. > - Removed the patch to use regmap as is not needed anymore. > > Changes in v9: None > Changes in v8: None > Changes in v7: None > > drivers/gpu/drm/mediatek/Kconfig | 1 + > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 256 ---------------------- > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 - > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 14 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- > drivers/soc/mediatek/mtk-mmsys.c | 277 ++++++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 20 ++ > 8 files changed, 314 insertions(+), 282 deletions(-) > create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h > > diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig > index fa5ffc4fe823..c420f5a3d33b 100644 > --- a/drivers/gpu/drm/mediatek/Kconfig > +++ b/drivers/gpu/drm/mediatek/Kconfig > @@ -11,6 +11,7 @@ config DRM_MEDIATEK > select DRM_MIPI_DSI > select DRM_PANEL > select MEMORY > + select MTK_MMSYS > select MTK_SMI > select VIDEOMODE_HELPERS > help > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index fd4042de12f2..f63a885e063c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,7 +29,7 @@ > * @enabled: records whether crtc_enable succeeded > * @planes: array of 4 drm_plane structures, one for each overlay plane > * @pending_planes: whether any plane has pending changes to be applied > - * @config_regs: memory mapped mmsys configuration register space > + * @mmsys_dev: pointer to the mmsys device for configuration registers > * @mutex: handle to one of the ten disp_mutex streams > * @ddp_comp_nr: number of components in ddp_comp > * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc > @@ -50,7 +51,7 @@ struct mtk_drm_crtc { > u32 cmdq_event; > #endif > > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct mtk_disp_mutex *mutex; > unsigned int ddp_comp_nr; > struct mtk_ddp_comp **ddp_comp; > @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_add_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > mtk_crtc->ddp_comp[i]->id); > mtk_disp_mutex_disable(mtk_crtc->mutex); > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > - mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, > - mtk_crtc->ddp_comp[i]->id, > - mtk_crtc->ddp_comp[i + 1]->id); > + mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, > + mtk_crtc->ddp_comp[i]->id, > + mtk_crtc->ddp_comp[i + 1]->id); > mtk_disp_mutex_remove_comp(mtk_crtc->mutex, > mtk_crtc->ddp_comp[i]->id); > } > @@ -758,7 +759,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, > if (!mtk_crtc) > return -ENOMEM; > > - mtk_crtc->config_regs = priv->config_regs; > + mtk_crtc->mmsys_dev = priv->mmsys_dev; > mtk_crtc->ddp_comp_nr = path_len; > mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, > sizeof(*mtk_crtc->ddp_comp), > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index b885f60f474c..014c1bbe1df2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -13,26 +13,6 @@ > #include "mtk_drm_ddp.h" > #include "mtk_drm_ddp_comp.h" > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > @@ -94,48 +74,6 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > > struct mtk_disp_mutex { > int id; > @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - mtk_ddp_sout_sel(config_regs, cur, next); > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) | value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - unsigned int addr, value, reg; > - > - value = mtk_ddp_mout_en(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > - > - value = mtk_ddp_sel_in(cur, next, &addr); > - if (value) { > - reg = readl_relaxed(config_regs + addr) & ~value; > - writel_relaxed(reg, config_regs + addr); > - } > -} > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > index 827be424a148..6b691a57be4a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > @@ -12,13 +12,6 @@ struct regmap; > struct device; > struct mtk_disp_mutex; > > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next); > - > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); > int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); > void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 8e2d3cb62ad5..208f9c5256ef 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_drm_private *private; > - struct resource *mem; > struct device_node *node; > struct component_match *match = NULL; > int ret; > @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev) > return -ENOMEM; > > private->data = of_device_get_match_data(dev); > - > - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - private->config_regs = devm_ioremap_resource(dev, mem); > - if (IS_ERR(private->config_regs)) { > - ret = PTR_ERR(private->config_regs); > - dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > - ret); > - return ret; > + private->mmsys_dev = dev->parent; > + if (!private->mmsys_dev) { > + dev_err(dev, "Failed to get MMSYS device\n"); > + return -ENODEV; > } > > /* Iterate over sibling DISP function blocks */ > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 17bc99b9f5d4..b5be63e53176 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -39,7 +39,7 @@ struct mtk_drm_private { > > struct device_node *mutex_node; > struct device *mutex_dev; > - void __iomem *config_regs; > + struct device *mmsys_dev; > struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; > struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; > const struct mtk_mmsys_driver_data *data; > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 473cdf732fb5..bb99a05fb278 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,14 +5,81 @@ > */ > > #include > +#include > #include > #include > +#include > > #include "../../clk/mediatek/clk-gate.h" > #include "../../clk/mediatek/clk-mtk.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > #include > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > static const struct mtk_gate_regs mm0_cg_regs = { > .set_ofs = 0x0104, > .clr_ofs = 0x0108, > @@ -110,13 +177,223 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .gates_num = ARRAY_SIZE(mt8173_mm_clks), > }; > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) | value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + void __iomem *config_regs = dev_get_drvdata(dev); > + unsigned int addr, value, reg; > + > + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > + > + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(config_regs + addr) & ~value; > + writel_relaxed(reg, config_regs + addr); > + } > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > struct device_node *node = pdev->dev.of_node; > const struct mtk_mmsys_driver_data *data; > struct clk_onecell_data *clk_data; > + struct device *dev = &pdev->dev; > + void __iomem *config_regs; > + struct resource *mem; > int ret; > > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + config_regs = devm_ioremap_resource(dev, mem); > + if (IS_ERR(config_regs)) { > + ret = PTR_ERR(config_regs); > + dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", > + ret); > + return ret; > + } > + > + platform_set_drvdata(pdev, config_regs); > + > clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); > if (!clk_data) > return -ENOMEM; > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > new file mode 100644 > index 000000000000..7bab5d9a3d31 > --- /dev/null > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + */ > + > +#ifndef __MTK_MMSYS_H > +#define __MTK_MMSYS_H > + > +enum mtk_ddp_comp_id; > +struct device; > + > +void mtk_mmsys_ddp_connect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +void mtk_mmsys_ddp_disconnect(struct device *dev, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > + > +#endif /* __MTK_MMSYS_H */ _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel