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Tue, 31 Mar 2020 00:38:32 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 01:28:45 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 16:28:41 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 31 Mar 2020 16:28:40 +0800 Message-ID: <1585643322.27082.3.camel@mtksdaap41> Subject: Re: [PATCH v11 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Nicolas Boichat , Lee Jones Date: Tue, 31 Mar 2020 16:28:42 +0800 In-Reply-To: References: <1585627657-3265-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1585627657-3265-4-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 66156411AC7C6987A565DE837C979D90C593ABB3BD713E9063DE777D8BE22B722000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200331_013854_086410_EE26A3ED X-CRM114-Status: GOOD ( 25.28 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alessandro Zummo , Alexandre Belloni , srv_heupstream , Frank Wunderlich , Josef Friedl , Ran Bi , Sean Wang , Sebastian Reichel , lkml , Richard Fontana , Devicetree List , Rob Herring , "moderated list:ARM/Mediatek SoC support" , linux-arm Mailing List , "open list:THERMAL" , Matthias Brugger , Thomas Gleixner , Eddie Huang , Kate Stewart , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Sirs On Tue, 2020-03-31 at 15:36 +0800, Nicolas Boichat wrote: > On Tue, Mar 31, 2020 at 12:07 PM Hsin-Hsiung Wang > wrote: > > > > This adds support for the MediaTek MT6358 PMIC. This is a > > multifunction device with the following sub modules: > > > > - Regulator > > - RTC > > - Codec > > - Interrupt > > > > It is interfaced to the host controller using SPI interface > > by a proprietary hardware called PMIC wrapper or pwrap. > > MT6358 MFD is a child device of the pwrap. > > > > Signed-off-by: Hsin-Hsiung Wang > > Reviewed-by: Nicolas Boichat > > This is missing a few comments from Lee Jones on v10, actually, repeated below: > https://patchwork.kernel.org/patch/11431239/#23244041 > So sorry for missing this comment.I will reply it later. Thanks a lot. > > --- > > drivers/mfd/Makefile | 2 +- > > drivers/mfd/mt6358-irq.c | 236 +++++++++++++++++++++++++++++ > > drivers/mfd/mt6397-core.c | 55 ++++++- > > include/linux/mfd/mt6358/core.h | 158 ++++++++++++++++++++ > > include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++++++++++ > > include/linux/mfd/mt6397/core.h | 3 + > > 6 files changed, 731 insertions(+), 5 deletions(-) > > create mode 100644 drivers/mfd/mt6358-irq.c > > create mode 100644 include/linux/mfd/mt6358/core.h > > create mode 100644 include/linux/mfd/mt6358/registers.h > > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > index b83f172..9af1414 100644 > > --- a/drivers/mfd/Makefile > > +++ b/drivers/mfd/Makefile > > @@ -238,7 +238,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o > > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > -mt6397-objs := mt6397-core.o mt6397-irq.o > > +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > > diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c > > new file mode 100644 > > index 0000000..022e5f5 > > --- /dev/null > > +++ b/drivers/mfd/mt6358-irq.c > > @@ -0,0 +1,236 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2019 MediaTek Inc. > > 2020 > > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static struct irq_top_t mt6358_ints[] = { > > + MT6358_TOP_GEN(BUCK), > > + MT6358_TOP_GEN(LDO), > > + MT6358_TOP_GEN(PSC), > > + MT6358_TOP_GEN(SCK), > > + MT6358_TOP_GEN(BM), > > + MT6358_TOP_GEN(HK), > > + MT6358_TOP_GEN(AUD), > > + MT6358_TOP_GEN(MISC), > > +}; > > + > > +static void pmic_irq_enable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = true; > > +} > > + > > +static void pmic_irq_disable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = false; > > +} > > + > > +static void pmic_irq_lock(struct irq_data *data) > > +{ > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + > > + mutex_lock(&chip->irqlock); > > +} > > + > > +static void pmic_irq_sync_unlock(struct irq_data *data) > > +{ > > + unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + for (i = 0; i < irqd->num_pmic_irqs; i++) { > > + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) > > + continue; > > + > > + /* Find out the IRQ group */ > > + top_gp = 0; > > + while ((top_gp + 1) < irqd->num_top && > > + i >= mt6358_ints[top_gp + 1].hwirq_base) > > + top_gp++; > > + > > + /* Find the irq registers */ > > From Lee Jones: 'Nit: "IRQ"' > > > + gp_offset = i - mt6358_ints[top_gp].hwirq_base; > > + int_regs = gp_offset / MT6358_REG_WIDTH; > > + shift = gp_offset % MT6358_REG_WIDTH; > > + en_reg = mt6358_ints[top_gp].en_reg + > > + (mt6358_ints[top_gp].en_reg_shift * int_regs); > > + > [...] > > +static const struct irq_domain_ops mt6358_irq_domain_ops = { > > + .map = pmic_irq_domain_map, > > + .xlate = irq_domain_xlate_twocell, > > +}; > > + > > +int mt6358_irq_init(struct mt6397_chip *chip) > > +{ > > + int i, j, ret; > > + struct pmic_irq_data *irqd; > > + > > + irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *), > > From Lee Jones: 'sizeof(*irqd)' > > > + GFP_KERNEL); > > + if (!irqd) > > + return -ENOMEM; > > + > > + chip->irq_data = irqd; > > + > [...] > > @@ -154,19 +184,33 @@ static int mt6397_probe(struct platform_device *pdev) > > if (pmic->irq <= 0) > > return pmic->irq; > > > > - ret = mt6397_irq_init(pmic); > > - if (ret) > > - return ret; > > - > > switch (pmic->chip_id) { > > case MT6323_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6323_devs, ARRAY_SIZE(mt6323_devs), > > NULL, 0, pmic->irq_domain); > > break; > > > > + case MT6358_CHIP_ID: > > + ret = mt6358_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > + mt6358_devs, ARRAY_SIZE(mt6358_devs), > > + NULL, 0, pmic->irq_domain); > > + break; > > From Lee Jones: "In a subsequent patch you can choose the correct > mtXXXX_devs structure to pass and call devm_mfd_add_devices() only > once below the switch()." > > Can you look into that as a follow-up patch? > > > > + > > case MT6391_CHIP_ID: > > case MT6397_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6397_devs, ARRAY_SIZE(mt6397_devs), > > NULL, 0, pmic->irq_domain); > > [snip] _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from 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<1585643322.27082.3.camel@mtksdaap41> Subject: Re: [PATCH v11 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Nicolas Boichat , Lee Jones CC: Rob Herring , Matthias Brugger , Alexandre Belloni , Mark Rutland , "Sean Wang" , Sebastian Reichel , "Eddie Huang" , Alessandro Zummo , Kate Stewart , Richard Fontana , Frank Wunderlich , "Josef Friedl" , Thomas Gleixner , "Ran Bi" , Devicetree List , linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , lkml , "open list:THERMAL" , , srv_heupstream Date: Tue, 31 Mar 2020 16:28:42 +0800 In-Reply-To: References: <1585627657-3265-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1585627657-3265-4-git-send-email-hsin-hsiung.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 66156411AC7C6987A565DE837C979D90C593ABB3BD713E9063DE777D8BE22B722000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org SGksIFNpcnMNCg0KT24gVHVlLCAyMDIwLTAzLTMxIGF0IDE1OjM2ICswODAwLCBOaWNvbGFzIEJv aWNoYXQgd3JvdGU6DQo+IE9uIFR1ZSwgTWFyIDMxLCAyMDIwIGF0IDEyOjA3IFBNIEhzaW4tSHNp dW5nIFdhbmcNCj4gPGhzaW4taHNpdW5nLndhbmdAbWVkaWF0ZWsuY29tPiB3cm90ZToNCj4gPg0K PiA+IFRoaXMgYWRkcyBzdXBwb3J0IGZvciB0aGUgTWVkaWFUZWsgTVQ2MzU4IFBNSUMuIFRoaXMg aXMgYQ0KPiA+IG11bHRpZnVuY3Rpb24gZGV2aWNlIHdpdGggdGhlIGZvbGxvd2luZyBzdWIgbW9k dWxlczoNCj4gPg0KPiA+IC0gUmVndWxhdG9yDQo+ID4gLSBSVEMNCj4gPiAtIENvZGVjDQo+ID4g LSBJbnRlcnJ1cHQNCj4gPg0KPiA+IEl0IGlzIGludGVyZmFjZWQgdG8gdGhlIGhvc3QgY29udHJv bGxlciB1c2luZyBTUEkgaW50ZXJmYWNlDQo+ID4gYnkgYSBwcm9wcmlldGFyeSBoYXJkd2FyZSBj YWxsZWQgUE1JQyB3cmFwcGVyIG9yIHB3cmFwLg0KPiA+IE1UNjM1OCBNRkQgaXMgYSBjaGlsZCBk ZXZpY2Ugb2YgdGhlIHB3cmFwLg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogSHNpbi1Ic2l1bmcg V2FuZyA8aHNpbi1oc2l1bmcud2FuZ0BtZWRpYXRlay5jb20+DQo+ID4gUmV2aWV3ZWQtYnk6IE5p Y29sYXMgQm9pY2hhdCA8ZHJpbmtjYXRAY2hyb21pdW0ub3JnPg0KPiANCj4gVGhpcyBpcyBtaXNz aW5nIGEgZmV3IGNvbW1lbnRzIGZyb20gTGVlIEpvbmVzIG9uIHYxMCwgYWN0dWFsbHksIHJlcGVh dGVkIGJlbG93Og0KPiBodHRwczovL3BhdGNod29yay5rZXJuZWwub3JnL3BhdGNoLzExNDMxMjM5 LyMyMzI0NDA0MQ0KPiANCg0KU28gc29ycnkgZm9yIG1pc3NpbmcgdGhpcyBjb21tZW50Lkkgd2ls bCByZXBseSBpdCBsYXRlci4NClRoYW5rcyBhIGxvdC4NCg0KPiA+IC0tLQ0KPiA+ICBkcml2ZXJz L21mZC9NYWtlZmlsZSAgICAgICAgICAgICAgICAgfCAgIDIgKy0NCj4gPiAgZHJpdmVycy9tZmQv bXQ2MzU4LWlycS5jICAgICAgICAgICAgIHwgMjM2ICsrKysrKysrKysrKysrKysrKysrKysrKysr KysrDQo+ID4gIGRyaXZlcnMvbWZkL210NjM5Ny1jb3JlLmMgICAgICAgICAgICB8ICA1NSArKysr KystDQo+ID4gIGluY2x1ZGUvbGludXgvbWZkL210NjM1OC9jb3JlLmggICAgICB8IDE1OCArKysr KysrKysrKysrKysrKysrKw0KPiA+ICBpbmNsdWRlL2xpbnV4L21mZC9tdDYzNTgvcmVnaXN0ZXJz LmggfCAyODIgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysNCj4gPiAgaW5jbHVk ZS9saW51eC9tZmQvbXQ2Mzk3L2NvcmUuaCAgICAgIHwgICAzICsNCj4gPiAgNiBmaWxlcyBjaGFu Z2VkLCA3MzEgaW5zZXJ0aW9ucygrKSwgNSBkZWxldGlvbnMoLSkNCj4gPiAgY3JlYXRlIG1vZGUg MTAwNjQ0IGRyaXZlcnMvbWZkL210NjM1OC1pcnEuYw0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQg aW5jbHVkZS9saW51eC9tZmQvbXQ2MzU4L2NvcmUuaA0KPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQg aW5jbHVkZS9saW51eC9tZmQvbXQ2MzU4L3JlZ2lzdGVycy5oDQo+ID4NCj4gPiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9tZmQvTWFrZWZpbGUgYi9kcml2ZXJzL21mZC9NYWtlZmlsZQ0KPiA+IGluZGV4 IGI4M2YxNzIuLjlhZjE0MTQgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9tZmQvTWFrZWZpbGUN Cj4gPiArKysgYi9kcml2ZXJzL21mZC9NYWtlZmlsZQ0KPiA+IEBAIC0yMzgsNyArMjM4LDcgQEAg b2JqLSQoQ09ORklHX0lOVEVMX1NPQ19QTUlDKSAgICAgICAgKz0gaW50ZWwtc29jLXBtaWMubw0K PiA+ICBvYmotJChDT05GSUdfSU5URUxfU09DX1BNSUNfQlhUV0MpICAgICArPSBpbnRlbF9zb2Nf cG1pY19ieHR3Yy5vDQo+ID4gIG9iai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQ19DSFRXQykgICAg ICs9IGludGVsX3NvY19wbWljX2NodHdjLm8NCj4gPiAgb2JqLSQoQ09ORklHX0lOVEVMX1NPQ19Q TUlDX0NIVERDX1RJKSAgKz0gaW50ZWxfc29jX3BtaWNfY2h0ZGNfdGkubw0KPiA+IC1tdDYzOTct b2JqcyAgICA6PSBtdDYzOTctY29yZS5vIG10NjM5Ny1pcnEubw0KPiA+ICttdDYzOTctb2JqcyAg ICAgICAgICAgICAgICAgICAgOj0gbXQ2Mzk3LWNvcmUubyBtdDYzOTctaXJxLm8gbXQ2MzU4LWly cS5vDQo+ID4gIG9iai0kKENPTkZJR19NRkRfTVQ2Mzk3KSAgICAgICArPSBtdDYzOTcubw0KPiA+ ICBvYmotJChDT05GSUdfSU5URUxfU09DX1BNSUNfTVJGTEQpICAgICArPSBpbnRlbF9zb2NfcG1p Y19tcmZsZC5vDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tZmQvbXQ2MzU4LWlycS5j IGIvZHJpdmVycy9tZmQvbXQ2MzU4LWlycS5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4g PiBpbmRleCAwMDAwMDAwLi4wMjJlNWY1DQo+ID4gLS0tIC9kZXYvbnVsbA0KPiA+ICsrKyBiL2Ry aXZlcnMvbWZkL210NjM1OC1pcnEuYw0KPiA+IEBAIC0wLDAgKzEsMjM2IEBADQo+ID4gKy8vIFNQ RFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wDQo+ID4gKy8vDQo+ID4gKy8vIENvcHlyaWdo dCAoYykgMjAxOSBNZWRpYVRlayBJbmMuDQo+IA0KPiAyMDIwDQo+IA0KPiA+ICsNCj4gPiArI2lu Y2x1ZGUgPGxpbnV4L2ludGVycnVwdC5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvbWZkL210NjM1 OC9jb3JlLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9tZmQvbXQ2MzU4L3JlZ2lzdGVycy5oPg0K PiA+ICsjaW5jbHVkZSA8bGludXgvbWZkL210NjM5Ny9jb3JlLmg+DQo+ID4gKyNpbmNsdWRlIDxs aW51eC9tb2R1bGUuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L29mLmg+DQo+ID4gKyNpbmNsdWRl IDxsaW51eC9vZl9kZXZpY2UuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L29mX2lycS5oPg0KPiA+ ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51 eC9yZWdtYXAuaD4NCj4gPiArDQo+ID4gK3N0YXRpYyBzdHJ1Y3QgaXJxX3RvcF90IG10NjM1OF9p bnRzW10gPSB7DQo+ID4gKyAgICAgICBNVDYzNThfVE9QX0dFTihCVUNLKSwNCj4gPiArICAgICAg IE1UNjM1OF9UT1BfR0VOKExETyksDQo+ID4gKyAgICAgICBNVDYzNThfVE9QX0dFTihQU0MpLA0K PiA+ICsgICAgICAgTVQ2MzU4X1RPUF9HRU4oU0NLKSwNCj4gPiArICAgICAgIE1UNjM1OF9UT1Bf R0VOKEJNKSwNCj4gPiArICAgICAgIE1UNjM1OF9UT1BfR0VOKEhLKSwNCj4gPiArICAgICAgIE1U NjM1OF9UT1BfR0VOKEFVRCksDQo+ID4gKyAgICAgICBNVDYzNThfVE9QX0dFTihNSVNDKSwNCj4g PiArfTsNCj4gPiArDQo+ID4gK3N0YXRpYyB2b2lkIHBtaWNfaXJxX2VuYWJsZShzdHJ1Y3QgaXJx X2RhdGEgKmRhdGEpDQo+ID4gK3sNCj4gPiArICAgICAgIHVuc2lnbmVkIGludCBod2lycSA9IGly cWRfdG9faHdpcnEoZGF0YSk7DQo+ID4gKyAgICAgICBzdHJ1Y3QgbXQ2Mzk3X2NoaXAgKmNoaXAg PSBpcnFfZGF0YV9nZXRfaXJxX2NoaXBfZGF0YShkYXRhKTsNCj4gPiArICAgICAgIHN0cnVjdCBw bWljX2lycV9kYXRhICppcnFkID0gY2hpcC0+aXJxX2RhdGE7DQo+ID4gKw0KPiA+ICsgICAgICAg aXJxZC0+ZW5hYmxlX2h3aXJxW2h3aXJxXSA9IHRydWU7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0 YXRpYyB2b2lkIHBtaWNfaXJxX2Rpc2FibGUoc3RydWN0IGlycV9kYXRhICpkYXRhKQ0KPiA+ICt7 DQo+ID4gKyAgICAgICB1bnNpZ25lZCBpbnQgaHdpcnEgPSBpcnFkX3RvX2h3aXJxKGRhdGEpOw0K PiA+ICsgICAgICAgc3RydWN0IG10NjM5N19jaGlwICpjaGlwID0gaXJxX2RhdGFfZ2V0X2lycV9j aGlwX2RhdGEoZGF0YSk7DQo+ID4gKyAgICAgICBzdHJ1Y3QgcG1pY19pcnFfZGF0YSAqaXJxZCA9 IGNoaXAtPmlycV9kYXRhOw0KPiA+ICsNCj4gPiArICAgICAgIGlycWQtPmVuYWJsZV9od2lycVto d2lycV0gPSBmYWxzZTsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIHZvaWQgcG1pY19pcnFf bG9jayhzdHJ1Y3QgaXJxX2RhdGEgKmRhdGEpDQo+ID4gK3sNCj4gPiArICAgICAgIHN0cnVjdCBt dDYzOTdfY2hpcCAqY2hpcCA9IGlycV9kYXRhX2dldF9pcnFfY2hpcF9kYXRhKGRhdGEpOw0KPiA+ ICsNCj4gPiArICAgICAgIG11dGV4X2xvY2soJmNoaXAtPmlycWxvY2spOw0KPiA+ICt9DQo+ID4g Kw0KPiA+ICtzdGF0aWMgdm9pZCBwbWljX2lycV9zeW5jX3VubG9jayhzdHJ1Y3QgaXJxX2RhdGEg KmRhdGEpDQo+ID4gK3sNCj4gPiArICAgICAgIHVuc2lnbmVkIGludCBpLCB0b3BfZ3AsIGdwX29m ZnNldCwgZW5fcmVnLCBpbnRfcmVncywgc2hpZnQ7DQo+ID4gKyAgICAgICBzdHJ1Y3QgbXQ2Mzk3 X2NoaXAgKmNoaXAgPSBpcnFfZGF0YV9nZXRfaXJxX2NoaXBfZGF0YShkYXRhKTsNCj4gPiArICAg ICAgIHN0cnVjdCBwbWljX2lycV9kYXRhICppcnFkID0gY2hpcC0+aXJxX2RhdGE7DQo+ID4gKw0K PiA+ICsgICAgICAgZm9yIChpID0gMDsgaSA8IGlycWQtPm51bV9wbWljX2lycXM7IGkrKykgew0K PiA+ICsgICAgICAgICAgICAgICBpZiAoaXJxZC0+ZW5hYmxlX2h3aXJxW2ldID09IGlycWQtPmNh Y2hlX2h3aXJxW2ldKQ0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGNvbnRpbnVlOw0KPiA+ ICsNCj4gPiArICAgICAgICAgICAgICAgLyogRmluZCBvdXQgdGhlIElSUSBncm91cCAqLw0KPiA+ ICsgICAgICAgICAgICAgICB0b3BfZ3AgPSAwOw0KPiA+ICsgICAgICAgICAgICAgICB3aGlsZSAo KHRvcF9ncCArIDEpIDwgaXJxZC0+bnVtX3RvcCAmJg0KPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgaSA+PSBtdDYzNThfaW50c1t0b3BfZ3AgKyAxXS5od2lycV9iYXNlKQ0KPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgIHRvcF9ncCsrOw0KPiA+ICsNCj4gPiArICAgICAgICAgICAgICAgLyog RmluZCB0aGUgaXJxIHJlZ2lzdGVycyAqLw0KPiANCj4gRnJvbSBMZWUgSm9uZXM6ICdOaXQ6ICJJ UlEiJw0KPiANCj4gPiArICAgICAgICAgICAgICAgZ3Bfb2Zmc2V0ID0gaSAtIG10NjM1OF9pbnRz W3RvcF9ncF0uaHdpcnFfYmFzZTsNCj4gPiArICAgICAgICAgICAgICAgaW50X3JlZ3MgPSBncF9v ZmZzZXQgLyBNVDYzNThfUkVHX1dJRFRIOw0KPiA+ICsgICAgICAgICAgICAgICBzaGlmdCA9IGdw X29mZnNldCAlIE1UNjM1OF9SRUdfV0lEVEg7DQo+ID4gKyAgICAgICAgICAgICAgIGVuX3JlZyA9 IG10NjM1OF9pbnRzW3RvcF9ncF0uZW5fcmVnICsNCj4gPiArICAgICAgICAgICAgICAgICAgICAg ICAgKG10NjM1OF9pbnRzW3RvcF9ncF0uZW5fcmVnX3NoaWZ0ICogaW50X3JlZ3MpOw0KPiA+ICsN Cj4gWy4uLl0NCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBpcnFfZG9tYWluX29wcyBtdDYzNThf aXJxX2RvbWFpbl9vcHMgPSB7DQo+ID4gKyAgICAgICAubWFwID0gcG1pY19pcnFfZG9tYWluX21h cCwNCj4gPiArICAgICAgIC54bGF0ZSA9IGlycV9kb21haW5feGxhdGVfdHdvY2VsbCwNCj4gPiAr fTsNCj4gPiArDQo+ID4gK2ludCBtdDYzNThfaXJxX2luaXQoc3RydWN0IG10NjM5N19jaGlwICpj aGlwKQ0KPiA+ICt7DQo+ID4gKyAgICAgICBpbnQgaSwgaiwgcmV0Ow0KPiA+ICsgICAgICAgc3Ry dWN0IHBtaWNfaXJxX2RhdGEgKmlycWQ7DQo+ID4gKw0KPiA+ICsgICAgICAgaXJxZCA9IGRldm1f a3phbGxvYyhjaGlwLT5kZXYsIHNpemVvZihzdHJ1Y3QgcG1pY19pcnFfZGF0YSAqKSwNCj4gDQo+ IEZyb20gTGVlIEpvbmVzOiAnc2l6ZW9mKCppcnFkKScNCj4gDQo+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgIEdGUF9LRVJORUwpOw0KPiA+ICsgICAgICAgaWYgKCFpcnFkKQ0KPiA+ICsg ICAgICAgICAgICAgICByZXR1cm4gLUVOT01FTTsNCj4gPiArDQo+ID4gKyAgICAgICBjaGlwLT5p cnFfZGF0YSA9IGlycWQ7DQo+ID4gKw0KPiBbLi4uXQ0KPiA+IEBAIC0xNTQsMTkgKzE4NCwzMyBA QCBzdGF0aWMgaW50IG10NjM5N19wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQ0K PiA+ICAgICAgICAgaWYgKHBtaWMtPmlycSA8PSAwKQ0KPiA+ICAgICAgICAgICAgICAgICByZXR1 cm4gcG1pYy0+aXJxOw0KPiA+DQo+ID4gLSAgICAgICByZXQgPSBtdDYzOTdfaXJxX2luaXQocG1p Yyk7DQo+ID4gLSAgICAgICBpZiAocmV0KQ0KPiA+IC0gICAgICAgICAgICAgICByZXR1cm4gcmV0 Ow0KPiA+IC0NCj4gPiAgICAgICAgIHN3aXRjaCAocG1pYy0+Y2hpcF9pZCkgew0KPiA+ICAgICAg ICAgY2FzZSBNVDYzMjNfQ0hJUF9JRDoNCj4gPiArICAgICAgICAgICAgICAgcmV0ID0gbXQ2Mzk3 X2lycV9pbml0KHBtaWMpOw0KPiA+ICsgICAgICAgICAgICAgICBpZiAocmV0KQ0KPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgIHJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICAgICAgICAgICAgICAg ICByZXQgPSBkZXZtX21mZF9hZGRfZGV2aWNlcygmcGRldi0+ZGV2LCBQTEFURk9STV9ERVZJRF9O T05FLA0KPiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBtdDYz MjNfZGV2cywgQVJSQVlfU0laRShtdDYzMjNfZGV2cyksDQo+ID4gICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIE5VTEwsIDAsIHBtaWMtPmlycV9kb21haW4pOw0KPiA+ ICAgICAgICAgICAgICAgICBicmVhazsNCj4gPg0KPiA+ICsgICAgICAgY2FzZSBNVDYzNThfQ0hJ UF9JRDoNCj4gPiArICAgICAgICAgICAgICAgcmV0ID0gbXQ2MzU4X2lycV9pbml0KHBtaWMpOw0K PiA+ICsgICAgICAgICAgICAgICBpZiAocmV0KQ0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAg IHJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICsgICAgICAgICAgICAgICByZXQgPSBkZXZtX21mZF9h ZGRfZGV2aWNlcygmcGRldi0+ZGV2LCBQTEFURk9STV9ERVZJRF9OT05FLA0KPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBtdDYzNThfZGV2cywgQVJSQVlfU0la RShtdDYzNThfZGV2cyksDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIE5VTEwsIDAsIHBtaWMtPmlycV9kb21haW4pOw0KPiA+ICsgICAgICAgICAgICAgICBi cmVhazsNCj4gDQo+IEZyb20gTGVlIEpvbmVzOiAiSW4gYSBzdWJzZXF1ZW50IHBhdGNoIHlvdSBj YW4gY2hvb3NlIHRoZSBjb3JyZWN0DQo+IG10WFhYWF9kZXZzIHN0cnVjdHVyZSB0byBwYXNzIGFu ZCBjYWxsIGRldm1fbWZkX2FkZF9kZXZpY2VzKCkgb25seQ0KPiBvbmNlIGJlbG93IHRoZSBzd2l0 Y2goKS4iDQo+IA0KPiBDYW4geW91IGxvb2sgaW50byB0aGF0IGFzIGEgZm9sbG93LXVwIHBhdGNo Pw0KPiANCj4gDQo+ID4gKw0KPiA+ICAgICAgICAgY2FzZSBNVDYzOTFfQ0hJUF9JRDoNCj4gPiAg ICAgICAgIGNhc2UgTVQ2Mzk3X0NISVBfSUQ6DQo+ID4gKyAgICAgICAgICAgICAgIHJldCA9IG10 NjM5N19pcnFfaW5pdChwbWljKTsNCj4gPiArICAgICAgICAgICAgICAgaWYgKHJldCkNCj4gPiAr ICAgICAgICAgICAgICAgICAgICAgICByZXR1cm4gcmV0Ow0KPiA+ICsNCj4gPiAgICAgICAgICAg ICAgICAgcmV0ID0gZGV2bV9tZmRfYWRkX2RldmljZXMoJnBkZXYtPmRldiwgUExBVEZPUk1fREVW SURfTk9ORSwNCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg bXQ2Mzk3X2RldnMsIEFSUkFZX1NJWkUobXQ2Mzk3X2RldnMpLA0KPiA+ICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBOVUxMLCAwLCBwbWljLT5pcnFfZG9tYWluKTsN Cj4gDQo+IFtzbmlwXQ0KDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by 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(172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 01:28:45 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 31 Mar 2020 16:28:41 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 31 Mar 2020 16:28:40 +0800 Message-ID: <1585643322.27082.3.camel@mtksdaap41> Subject: Re: [PATCH v11 3/5] mfd: Add support for the MediaTek MT6358 PMIC From: Hsin-hsiung Wang To: Nicolas Boichat , Lee Jones Date: Tue, 31 Mar 2020 16:28:42 +0800 In-Reply-To: References: <1585627657-3265-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1585627657-3265-4-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 66156411AC7C6987A565DE837C979D90C593ABB3BD713E9063DE777D8BE22B722000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200331_013854_086410_EE26A3ED X-CRM114-Status: GOOD ( 25.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Alessandro Zummo , Alexandre Belloni , srv_heupstream , Frank Wunderlich , Josef Friedl , Ran Bi , Sean Wang , Sebastian Reichel , lkml , Richard Fontana , Devicetree List , Rob Herring , "moderated list:ARM/Mediatek SoC support" , linux-arm Mailing List , "open list:THERMAL" , Matthias Brugger , Thomas Gleixner , Eddie Huang , Kate Stewart , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Sirs On Tue, 2020-03-31 at 15:36 +0800, Nicolas Boichat wrote: > On Tue, Mar 31, 2020 at 12:07 PM Hsin-Hsiung Wang > wrote: > > > > This adds support for the MediaTek MT6358 PMIC. This is a > > multifunction device with the following sub modules: > > > > - Regulator > > - RTC > > - Codec > > - Interrupt > > > > It is interfaced to the host controller using SPI interface > > by a proprietary hardware called PMIC wrapper or pwrap. > > MT6358 MFD is a child device of the pwrap. > > > > Signed-off-by: Hsin-Hsiung Wang > > Reviewed-by: Nicolas Boichat > > This is missing a few comments from Lee Jones on v10, actually, repeated below: > https://patchwork.kernel.org/patch/11431239/#23244041 > So sorry for missing this comment.I will reply it later. Thanks a lot. > > --- > > drivers/mfd/Makefile | 2 +- > > drivers/mfd/mt6358-irq.c | 236 +++++++++++++++++++++++++++++ > > drivers/mfd/mt6397-core.c | 55 ++++++- > > include/linux/mfd/mt6358/core.h | 158 ++++++++++++++++++++ > > include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++++++++++ > > include/linux/mfd/mt6397/core.h | 3 + > > 6 files changed, 731 insertions(+), 5 deletions(-) > > create mode 100644 drivers/mfd/mt6358-irq.c > > create mode 100644 include/linux/mfd/mt6358/core.h > > create mode 100644 include/linux/mfd/mt6358/registers.h > > > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > > index b83f172..9af1414 100644 > > --- a/drivers/mfd/Makefile > > +++ b/drivers/mfd/Makefile > > @@ -238,7 +238,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o > > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o > > -mt6397-objs := mt6397-core.o mt6397-irq.o > > +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o > > obj-$(CONFIG_MFD_MT6397) += mt6397.o > > obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o > > > > diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c > > new file mode 100644 > > index 0000000..022e5f5 > > --- /dev/null > > +++ b/drivers/mfd/mt6358-irq.c > > @@ -0,0 +1,236 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2019 MediaTek Inc. > > 2020 > > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static struct irq_top_t mt6358_ints[] = { > > + MT6358_TOP_GEN(BUCK), > > + MT6358_TOP_GEN(LDO), > > + MT6358_TOP_GEN(PSC), > > + MT6358_TOP_GEN(SCK), > > + MT6358_TOP_GEN(BM), > > + MT6358_TOP_GEN(HK), > > + MT6358_TOP_GEN(AUD), > > + MT6358_TOP_GEN(MISC), > > +}; > > + > > +static void pmic_irq_enable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = true; > > +} > > + > > +static void pmic_irq_disable(struct irq_data *data) > > +{ > > + unsigned int hwirq = irqd_to_hwirq(data); > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + irqd->enable_hwirq[hwirq] = false; > > +} > > + > > +static void pmic_irq_lock(struct irq_data *data) > > +{ > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + > > + mutex_lock(&chip->irqlock); > > +} > > + > > +static void pmic_irq_sync_unlock(struct irq_data *data) > > +{ > > + unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; > > + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); > > + struct pmic_irq_data *irqd = chip->irq_data; > > + > > + for (i = 0; i < irqd->num_pmic_irqs; i++) { > > + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) > > + continue; > > + > > + /* Find out the IRQ group */ > > + top_gp = 0; > > + while ((top_gp + 1) < irqd->num_top && > > + i >= mt6358_ints[top_gp + 1].hwirq_base) > > + top_gp++; > > + > > + /* Find the irq registers */ > > From Lee Jones: 'Nit: "IRQ"' > > > + gp_offset = i - mt6358_ints[top_gp].hwirq_base; > > + int_regs = gp_offset / MT6358_REG_WIDTH; > > + shift = gp_offset % MT6358_REG_WIDTH; > > + en_reg = mt6358_ints[top_gp].en_reg + > > + (mt6358_ints[top_gp].en_reg_shift * int_regs); > > + > [...] > > +static const struct irq_domain_ops mt6358_irq_domain_ops = { > > + .map = pmic_irq_domain_map, > > + .xlate = irq_domain_xlate_twocell, > > +}; > > + > > +int mt6358_irq_init(struct mt6397_chip *chip) > > +{ > > + int i, j, ret; > > + struct pmic_irq_data *irqd; > > + > > + irqd = devm_kzalloc(chip->dev, sizeof(struct pmic_irq_data *), > > From Lee Jones: 'sizeof(*irqd)' > > > + GFP_KERNEL); > > + if (!irqd) > > + return -ENOMEM; > > + > > + chip->irq_data = irqd; > > + > [...] > > @@ -154,19 +184,33 @@ static int mt6397_probe(struct platform_device *pdev) > > if (pmic->irq <= 0) > > return pmic->irq; > > > > - ret = mt6397_irq_init(pmic); > > - if (ret) > > - return ret; > > - > > switch (pmic->chip_id) { > > case MT6323_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6323_devs, ARRAY_SIZE(mt6323_devs), > > NULL, 0, pmic->irq_domain); > > break; > > > > + case MT6358_CHIP_ID: > > + ret = mt6358_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > + mt6358_devs, ARRAY_SIZE(mt6358_devs), > > + NULL, 0, pmic->irq_domain); > > + break; > > From Lee Jones: "In a subsequent patch you can choose the correct > mtXXXX_devs structure to pass and call devm_mfd_add_devices() only > once below the switch()." > > Can you look into that as a follow-up patch? > > > > + > > case MT6391_CHIP_ID: > > case MT6397_CHIP_ID: > > + ret = mt6397_irq_init(pmic); > > + if (ret) > > + return ret; > > + > > ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, > > mt6397_devs, ARRAY_SIZE(mt6397_devs), > > NULL, 0, pmic->irq_domain); > > [snip] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel