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Sun, 10 May 2020 22:07:47 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 May 2020 23:03:09 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 11 May 2020 14:03:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 11 May 2020 14:03:09 +0800 Message-ID: <1589176989.21832.10.camel@mtksdaap41> Subject: Re: [PATCH v14 04/11] soc: mediatek: Remove infracfg misc driver support From: Weiyi Lu To: Enric Balletbo i Serra Date: Mon, 11 May 2020 14:03:09 +0800 In-Reply-To: <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> References: <1588752963-19934-1-git-send-email-weiyi.lu@mediatek.com> <1588752963-19934-5-git-send-email-weiyi.lu@mediatek.com> <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200510_230757_381365_EB37B22C X-CRM114-Status: GOOD ( 23.75 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Nicolas Boichat , srv_heupstream@mediatek.com, Rob Herring , Enric Balletbo Serra , linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-05-06 at 23:00 +0200, Enric Balletbo i Serra wrote: > Hi Weiyi, > > Thank you for your patch. > > On 6/5/20 10:15, Weiyi Lu wrote: > > The functions provided by infracfg misc driver have no other user except > > the scpsys driver so move those into scpsys driver directly. > > And then, remove infracfg misc drvier which is no longer being used. > > Typo: s/drvier/driver/ I'll fix it, thank you. > > > BTW, in next patch, we're going to extend the bus protection functions > > with more customized arguments. > > > > Signed-off-by: Weiyi Lu > > Reviewed-by: Enric Balletbo i Serra > Thanks for your reviewing. > > --- > > drivers/soc/mediatek/Kconfig | 10 ----- > > drivers/soc/mediatek/Makefile | 1 - > > drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- > > drivers/soc/mediatek/mtk-scpsys.c | 66 +++++++++++++++++++++++++---- > > include/linux/soc/mediatek/infracfg.h | 39 ----------------- > > 5 files changed, 57 insertions(+), 138 deletions(-) > > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c > > delete mode 100644 include/linux/soc/mediatek/infracfg.h > > > > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig > > index 2114b56..f837b3c 100644 > > --- a/drivers/soc/mediatek/Kconfig > > +++ b/drivers/soc/mediatek/Kconfig > > @@ -10,21 +10,12 @@ config MTK_CMDQ > > depends on ARCH_MEDIATEK || COMPILE_TEST > > select MAILBOX > > select MTK_CMDQ_MBOX > > - select MTK_INFRACFG > > help > > Say yes here to add support for the MediaTek Command Queue (CMDQ) > > driver. The CMDQ is used to help read/write registers with critical > > time limitation, such as updating display configuration during the > > vblank. > > > > -config MTK_INFRACFG > > - bool "MediaTek INFRACFG Support" > > - select REGMAP > > - help > > - Say yes here to add support for the MediaTek INFRACFG controller. The > > - INFRACFG controller contains various infrastructure registers not > > - directly associated to any device. > > - > > config MTK_PMIC_WRAP > > tristate "MediaTek PMIC Wrapper Support" > > depends on RESET_CONTROLLER > > @@ -38,7 +29,6 @@ config MTK_SCPSYS > > bool "MediaTek SCPSYS Support" > > default ARCH_MEDIATEK > > select REGMAP > > - select MTK_INFRACFG > > select PM_GENERIC_DOMAINS if PM > > help > > Say yes here to add support for the MediaTek SCPSYS power domain > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index b017330..2b2c2537 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -1,5 +1,4 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c > > deleted file mode 100644 > > index 341c7ac..0000000 > > --- a/drivers/soc/mediatek/mtk-infracfg.c > > +++ /dev/null > > @@ -1,79 +0,0 @@ > > -// SPDX-License-Identifier: GPL-2.0-only > > -/* > > - * Copyright (c) 2015 Pengutronix, Sascha Hauer > > - */ > > - > > -#include > > -#include > > -#include > > -#include > > -#include > > - > > -#define MTK_POLL_DELAY_US 10 > > -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) > > - > > -#define INFRA_TOPAXI_PROTECTEN 0x0220 > > -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > - > > -/** > > - * mtk_infracfg_set_bus_protection - enable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be enabled. > > - * @reg_update: The boolean flag determines to set the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with set register(PROTECTEN_SET). > > - * > > - * This function enables the bus protection bits for disabled power > > - * domains so that the system does not hang when some unit accesses the > > - * bus while in power down. > > - */ > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - u32 val; > > - int ret; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > - mask); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, (val & mask) == mask, > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > - > > -/** > > - * mtk_infracfg_clear_bus_protection - disable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be disabled. > > - * @reg_update: The boolean flag determines to clear the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with clear register(PROTECTEN_CLR). > > - * > > - * This function disables the bus protection bits previously enabled with > > - * mtk_infracfg_set_bus_protection. > > - */ > > - > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - int ret; > > - u32 val; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, !(val & mask), > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c > > index c9c3cf7..b603af7 100644 > > --- a/drivers/soc/mediatek/mtk-scpsys.c > > +++ b/drivers/soc/mediatek/mtk-scpsys.c > > @@ -10,8 +10,8 @@ > > #include > > #include > > #include > > +#include > > #include > > -#include > > > > #include > > #include > > @@ -78,6 +78,29 @@ > > #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ > > #define PWR_STATUS_WB BIT(27) /* MT7622 */ > > > > +#define INFRA_TOPAXI_PROTECTEN 0x0220 > > +#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > +#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > +#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > + > > +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > + > > +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > + BIT(28)) > > +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > + BIT(7) | BIT(8)) > > + > > +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > + > > #define MAX_CLKS 3 > > > > /** > > @@ -251,25 +274,50 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) > > static int scpsys_bus_protect_enable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_set_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > + mask); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, (val & mask) == mask, > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_bus_protect_disable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_clear_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, !(val & mask), > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_power_on(struct generic_pm_domain *genpd) > > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h > > deleted file mode 100644 > > index fd25f01..0000000 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ /dev/null > > @@ -1,39 +0,0 @@ > > -/* SPDX-License-Identifier: GPL-2.0 */ > > -#ifndef __SOC_MEDIATEK_INFRACFG_H > > -#define __SOC_MEDIATEK_INFRACFG_H > > - > > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) > > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) > > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) > > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) > > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) > > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) > > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > - > > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > - > > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > - BIT(28)) > > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > - BIT(7) | BIT(8)) > > - > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -#endif /* __SOC_MEDIATEK_INFRACFG_H */ > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F383C47255 for ; Mon, 11 May 2020 06:08:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C808D2080C for ; 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bh=U+zyaXCjeWA/QnQwgJfP/AK+Tn0+3JKceonniVGdi+0=; b=iC0aMSlU76sHo/ETSsvyveFdFLPneOespX9BkjcAcPySyPocGUxhZreZQdl0pXFxKCTnv4kUUuqjNCCIaP0gZbhM+sklVHADIgZCkCjDzpYSWFnmN9cQvzwZIgw4dWsanqWiy0CSCtq0QXsVU3CP51ilYnwbCm862izDIPIPDiA=; X-UUID: cdcec821e41848cb9ede0519575e75e0-20200510 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 34349766; Sun, 10 May 2020 22:07:47 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 May 2020 23:03:09 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 11 May 2020 14:03:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 11 May 2020 14:03:09 +0800 Message-ID: <1589176989.21832.10.camel@mtksdaap41> Subject: Re: [PATCH v14 04/11] soc: mediatek: Remove infracfg misc driver support From: Weiyi Lu To: Enric Balletbo i Serra Date: Mon, 11 May 2020 14:03:09 +0800 In-Reply-To: <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> References: <1588752963-19934-1-git-send-email-weiyi.lu@mediatek.com> <1588752963-19934-5-git-send-email-weiyi.lu@mediatek.com> <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200510_230757_381365_EB37B22C X-CRM114-Status: GOOD ( 23.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Nicolas Boichat , srv_heupstream@mediatek.com, Rob Herring , Enric Balletbo Serra , linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Sascha Hauer , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-05-06 at 23:00 +0200, Enric Balletbo i Serra wrote: > Hi Weiyi, > > Thank you for your patch. > > On 6/5/20 10:15, Weiyi Lu wrote: > > The functions provided by infracfg misc driver have no other user except > > the scpsys driver so move those into scpsys driver directly. > > And then, remove infracfg misc drvier which is no longer being used. > > Typo: s/drvier/driver/ I'll fix it, thank you. > > > BTW, in next patch, we're going to extend the bus protection functions > > with more customized arguments. > > > > Signed-off-by: Weiyi Lu > > Reviewed-by: Enric Balletbo i Serra > Thanks for your reviewing. > > --- > > drivers/soc/mediatek/Kconfig | 10 ----- > > drivers/soc/mediatek/Makefile | 1 - > > drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- > > drivers/soc/mediatek/mtk-scpsys.c | 66 +++++++++++++++++++++++++---- > > include/linux/soc/mediatek/infracfg.h | 39 ----------------- > > 5 files changed, 57 insertions(+), 138 deletions(-) > > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c > > delete mode 100644 include/linux/soc/mediatek/infracfg.h > > > > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig > > index 2114b56..f837b3c 100644 > > --- a/drivers/soc/mediatek/Kconfig > > +++ b/drivers/soc/mediatek/Kconfig > > @@ -10,21 +10,12 @@ config MTK_CMDQ > > depends on ARCH_MEDIATEK || COMPILE_TEST > > select MAILBOX > > select MTK_CMDQ_MBOX > > - select MTK_INFRACFG > > help > > Say yes here to add support for the MediaTek Command Queue (CMDQ) > > driver. The CMDQ is used to help read/write registers with critical > > time limitation, such as updating display configuration during the > > vblank. > > > > -config MTK_INFRACFG > > - bool "MediaTek INFRACFG Support" > > - select REGMAP > > - help > > - Say yes here to add support for the MediaTek INFRACFG controller. The > > - INFRACFG controller contains various infrastructure registers not > > - directly associated to any device. > > - > > config MTK_PMIC_WRAP > > tristate "MediaTek PMIC Wrapper Support" > > depends on RESET_CONTROLLER > > @@ -38,7 +29,6 @@ config MTK_SCPSYS > > bool "MediaTek SCPSYS Support" > > default ARCH_MEDIATEK > > select REGMAP > > - select MTK_INFRACFG > > select PM_GENERIC_DOMAINS if PM > > help > > Say yes here to add support for the MediaTek SCPSYS power domain > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index b017330..2b2c2537 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -1,5 +1,4 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c > > deleted file mode 100644 > > index 341c7ac..0000000 > > --- a/drivers/soc/mediatek/mtk-infracfg.c > > +++ /dev/null > > @@ -1,79 +0,0 @@ > > -// SPDX-License-Identifier: GPL-2.0-only > > -/* > > - * Copyright (c) 2015 Pengutronix, Sascha Hauer > > - */ > > - > > -#include > > -#include > > -#include > > -#include > > -#include > > - > > -#define MTK_POLL_DELAY_US 10 > > -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) > > - > > -#define INFRA_TOPAXI_PROTECTEN 0x0220 > > -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > - > > -/** > > - * mtk_infracfg_set_bus_protection - enable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be enabled. > > - * @reg_update: The boolean flag determines to set the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with set register(PROTECTEN_SET). > > - * > > - * This function enables the bus protection bits for disabled power > > - * domains so that the system does not hang when some unit accesses the > > - * bus while in power down. > > - */ > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - u32 val; > > - int ret; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > - mask); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, (val & mask) == mask, > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > - > > -/** > > - * mtk_infracfg_clear_bus_protection - disable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be disabled. > > - * @reg_update: The boolean flag determines to clear the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with clear register(PROTECTEN_CLR). > > - * > > - * This function disables the bus protection bits previously enabled with > > - * mtk_infracfg_set_bus_protection. > > - */ > > - > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - int ret; > > - u32 val; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, !(val & mask), > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c > > index c9c3cf7..b603af7 100644 > > --- a/drivers/soc/mediatek/mtk-scpsys.c > > +++ b/drivers/soc/mediatek/mtk-scpsys.c > > @@ -10,8 +10,8 @@ > > #include > > #include > > #include > > +#include > > #include > > -#include > > > > #include > > #include > > @@ -78,6 +78,29 @@ > > #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ > > #define PWR_STATUS_WB BIT(27) /* MT7622 */ > > > > +#define INFRA_TOPAXI_PROTECTEN 0x0220 > > +#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > +#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > +#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > + > > +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > + > > +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > + BIT(28)) > > +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > + BIT(7) | BIT(8)) > > + > > +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > + > > #define MAX_CLKS 3 > > > > /** > > @@ -251,25 +274,50 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) > > static int scpsys_bus_protect_enable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_set_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > + mask); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, (val & mask) == mask, > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_bus_protect_disable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_clear_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, !(val & mask), > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_power_on(struct generic_pm_domain *genpd) > > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h > > deleted file mode 100644 > > index fd25f01..0000000 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ /dev/null > > @@ -1,39 +0,0 @@ > > -/* SPDX-License-Identifier: GPL-2.0 */ > > -#ifndef __SOC_MEDIATEK_INFRACFG_H > > -#define __SOC_MEDIATEK_INFRACFG_H > > - > > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) > > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) > > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) > > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) > > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) > > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) > > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > - > > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > - > > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > - BIT(28)) > > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > - BIT(7) | BIT(8)) > > - > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -#endif /* __SOC_MEDIATEK_INFRACFG_H */ > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45E7AC47255 for ; Mon, 11 May 2020 06:03:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by 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b=iC0aMSlU76sHo/ETSsvyveFdFLPneOespX9BkjcAcPySyPocGUxhZreZQdl0pXFxKCTnv4kUUuqjNCCIaP0gZbhM+sklVHADIgZCkCjDzpYSWFnmN9cQvzwZIgw4dWsanqWiy0CSCtq0QXsVU3CP51ilYnwbCm862izDIPIPDiA=; X-UUID: 02d2321070a54bb9b8955c2a0ebb2cbb-20200511 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1085074419; Mon, 11 May 2020 14:03:10 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 11 May 2020 14:03:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 11 May 2020 14:03:09 +0800 Message-ID: <1589176989.21832.10.camel@mtksdaap41> Subject: Re: [PATCH v14 04/11] soc: mediatek: Remove infracfg misc driver support From: Weiyi Lu To: Enric Balletbo i Serra CC: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer , James Liao , , , Fan Chen , , Date: Mon, 11 May 2020 14:03:09 +0800 In-Reply-To: <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> References: <1588752963-19934-1-git-send-email-weiyi.lu@mediatek.com> <1588752963-19934-5-git-send-email-weiyi.lu@mediatek.com> <321bcdff-06ea-b51d-d287-444bcdb20cba@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DQpPbiBXZWQsIDIwMjAtMDUtMDYgYXQgMjM6MDAgKzAyMDAsIEVucmljIEJhbGxldGJvIGkgU2Vy cmEgd3JvdGU6DQo+IEhpIFdlaXlpLA0KPiANCj4gVGhhbmsgeW91IGZvciB5b3VyIHBhdGNoLg0K PiANCj4gT24gNi81LzIwIDEwOjE1LCBXZWl5aSBMdSB3cm90ZToNCj4gPiBUaGUgZnVuY3Rpb25z IHByb3ZpZGVkIGJ5IGluZnJhY2ZnIG1pc2MgZHJpdmVyIGhhdmUgbm8gb3RoZXIgdXNlciBleGNl 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