From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35B16C433E0 for ; Thu, 28 May 2020 03:36:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0873120888 for ; Thu, 28 May 2020 03:36:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="PkP+nxSO"; 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Wed, 27 May 2020 19:36:40 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 May 2020 20:36:38 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 May 2020 11:36:30 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 11:36:29 +0800 Message-ID: <1590636882.8804.474.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus Date: Thu, 28 May 2020 11:34:42 +0800 In-Reply-To: <20200527211628.GT7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 0450CC54ABF4AD762CD5AF3FD76B1C4256091870E9459F877A5F0726FFA223302000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_203642_287889_CB0606C5 X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Rob Herring , Andy Shevchenko , srv_heupstream , devicetree@vger.kernel.org, Linus Walleij , Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?= , Tomasz Figa , Bartosz Golaszewski , Sj Huang , Nicolas Boichat , "moderated list:ARM/Mediatek SoC support" , dongchun.zhu@mediatek.com, Louis Kuo , Matthias Brugger , Cao Bing Bu , Mauro Carvalho Chehab , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Sakari, Rob, On Thu, 2020-05-28 at 00:16 +0300, Sakari Ailus wrote: > Hi Rob, Dongchun, > > On Wed, May 27, 2020 at 09:27:22AM -0600, Rob Herring wrote: > > > > > + properties: > > > > > + endpoint: > > > > > + type: object > > > > > + additionalProperties: false > > > > > + > > > > > + properties: > > > > > > Actually I wonder whether we need to declare 'clock-lanes' here? > > > > Yes, if you are using it. > > Dongchun, can you confirm the chip has a single data and a single clock > lane and that it does not support lane reordering? > >From the datasheet, 'MIPI inside the OV02A10 provides one single uni-directional clock lane and one bi-directional data lane solution for communication links between components inside a mobile device. The data lane has full support for HS(uni-directional) and LP(bi-directional) data transfer mode.' The sensor doesn't support lane reordering, so 'clock-lanes' property would not be added in next release. > So if there's nothing to convey to the driver, also the data-lanes should > be removed IMO. > However, 'data-lanes' property may still be required. It is known that either data-lanes or clock-lanes is an array of physical data lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g., for 1-lane MIPI CSI-2 bus we could have "data-lanes = <1>;", assuming the clock lane is on hardware lane 0. As mentioned earlier, the OV02A10 sensor supports only 1C1D and does not support lane reordering, so here we shall use 'data-lanes = <1>' as there is only a clock lane for OV02A10. Reminder: If 'data-lanes' property is not present, the driver would assume four-lane operation. This means for one-lane or two-lane operation, this property must be present and set to the right physical lane indexes. If the hardware does not support lane reordering, monotonically incremented values shall be used from 0 or 1 onwards, depending on whether or not there is also a clock lane. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC40C433DF for ; Thu, 28 May 2020 03:36:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2153212CC for ; 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bh=B6mKHMDfrymV2HHPTTa5aBOQ9ky9BHCqAwadTmNHccs=; b=TUF7+Zf5fFkb6aXHGMEhOvrn6uow7lzAU5G7sk4CucFjAx5XmRNTxiOSavhADjZZgnbktTj4YfccuA5vOhv4SsB0Ep6nE+0404oRJHcWMTTDkZF/LTCSb97CqMMW19Q2giNFgEXIP4A9EpTGZuGD4oRvEz2lZry1RBMzK3xlxKI=; X-UUID: faa115bcb225478a870f95e80bf2edc4-20200527 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 491293446; Wed, 27 May 2020 19:36:40 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 May 2020 20:36:38 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 May 2020 11:36:30 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 11:36:29 +0800 Message-ID: <1590636882.8804.474.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus Date: Thu, 28 May 2020 11:34:42 +0800 In-Reply-To: <20200527211628.GT7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 0450CC54ABF4AD762CD5AF3FD76B1C4256091870E9459F877A5F0726FFA223302000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_203642_287889_CB0606C5 X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Rob Herring , Andy Shevchenko , srv_heupstream , devicetree@vger.kernel.org, Linus Walleij , Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?= , Tomasz Figa , Bartosz Golaszewski , Sj Huang , Nicolas Boichat , "moderated list:ARM/Mediatek SoC support" , dongchun.zhu@mediatek.com, Louis Kuo , Matthias Brugger , Cao Bing Bu , Mauro Carvalho Chehab , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sakari, Rob, On Thu, 2020-05-28 at 00:16 +0300, Sakari Ailus wrote: > Hi Rob, Dongchun, > > On Wed, May 27, 2020 at 09:27:22AM -0600, Rob Herring wrote: > > > > > + properties: > > > > > + endpoint: > > > > > + type: object > > > > > + additionalProperties: false > > > > > + > > > > > + properties: > > > > > > Actually I wonder whether we need to declare 'clock-lanes' here? > > > > Yes, if you are using it. > > Dongchun, can you confirm the chip has a single data and a single clock > lane and that it does not support lane reordering? > >From the datasheet, 'MIPI inside the OV02A10 provides one single uni-directional clock lane and one bi-directional data lane solution for communication links between components inside a mobile device. The data lane has full support for HS(uni-directional) and LP(bi-directional) data transfer mode.' The sensor doesn't support lane reordering, so 'clock-lanes' property would not be added in next release. > So if there's nothing to convey to the driver, also the data-lanes should > be removed IMO. > However, 'data-lanes' property may still be required. It is known that either data-lanes or clock-lanes is an array of physical data lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g., for 1-lane MIPI CSI-2 bus we could have "data-lanes = <1>;", assuming the clock lane is on hardware lane 0. As mentioned earlier, the OV02A10 sensor supports only 1C1D and does not support lane reordering, so here we shall use 'data-lanes = <1>' as there is only a clock lane for OV02A10. Reminder: If 'data-lanes' property is not present, the driver would assume four-lane operation. This means for one-lane or two-lane operation, this property must be present and set to the right physical lane indexes. If the hardware does not support lane reordering, monotonically incremented values shall be used from 0 or 1 onwards, depending on whether or not there is also a clock lane. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4770C433DF for ; Thu, 28 May 2020 03:36:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A525A20890 for ; Thu, 28 May 2020 03:36:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="J5mqIO3i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727073AbgE1Dgm (ORCPT ); Wed, 27 May 2020 23:36:42 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:18815 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726563AbgE1Dgl (ORCPT ); Wed, 27 May 2020 23:36:41 -0400 X-UUID: a5cac07ea31b4faba7a316b4ffe3c253-20200528 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=B6mKHMDfrymV2HHPTTa5aBOQ9ky9BHCqAwadTmNHccs=; b=J5mqIO3iYbIOVAxIlzQF4xZo0RIX2sVBC7z/jcr084EvpH6E0byjfF9dpJiUHyYGQfyAiMDzqNXbpkNXgEB1ao0nJyQLNfzC0BUIkPbYMNjyy0iPbyaD1cNoSNNyMMu7AAJMPLlT8X7hHmVxShRR1ojFos1bVxmWL2Lt794W1hU=; X-UUID: a5cac07ea31b4faba7a316b4ffe3c253-20200528 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 630452014; Thu, 28 May 2020 11:36:36 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 May 2020 11:36:30 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 11:36:29 +0800 Message-ID: <1590636882.8804.474.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus CC: Rob Herring , Linus Walleij , Bartosz Golaszewski , Mauro Carvalho Chehab , Andy Shevchenko , Mark Rutland , Nicolas Boichat , Tomasz Figa , Matthias Brugger , Cao Bing Bu , srv_heupstream , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Sj Huang , Linux Media Mailing List , , Louis Kuo , "Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?=" , Date: Thu, 28 May 2020 11:34:42 +0800 In-Reply-To: <20200527211628.GT7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 0450CC54ABF4AD762CD5AF3FD76B1C4256091870E9459F877A5F0726FFA223302000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SGkgU2FrYXJpLCBSb2IsDQoNCk9uIFRodSwgMjAyMC0wNS0yOCBhdCAwMDoxNiArMDMwMCwgU2Fr YXJpIEFpbHVzIHdyb3RlOg0KPiBIaSBSb2IsIERvbmdjaHVuLA0KPiANCj4gT24gV2VkLCBNYXkg MjcsIDIwMjAgYXQgMDk6Mjc6MjJBTSAtMDYwMCwgUm9iIEhlcnJpbmcgd3JvdGU6DQo+ID4gPiA+ ID4gKyAgICBwcm9wZXJ0aWVzOg0KPiA+ID4gPiA+ICsgICAgICBlbmRwb2ludDoNCj4gPiA+ID4g PiArICAgICAgICB0eXBlOiBvYmplY3QNCj4gPiA+ID4gPiArICAgICAgICBhZGRpdGlvbmFsUHJv cGVydGllczogZmFsc2UNCj4gPiA+ID4gPiArDQo+ID4gPiA+ID4gKyAgICAgICAgcHJvcGVydGll czoNCj4gPiA+DQo+ID4gPiBBY3R1YWxseSBJIHdvbmRlciB3aGV0aGVyIHdlIG5lZWQgdG8gZGVj bGFyZSAnY2xvY2stbGFuZXMnIGhlcmU/DQo+ID4gDQo+ID4gWWVzLCBpZiB5b3UgYXJlIHVzaW5n IGl0Lg0KPiANCj4gRG9uZ2NodW4sIGNhbiB5b3UgY29uZmlybSB0aGUgY2hpcCBoYXMgYSBzaW5n bGUgZGF0YSBhbmQgYSBzaW5nbGUgY2xvY2sNCj4gbGFuZSBhbmQgdGhhdCBpdCBkb2VzIG5vdCBz dXBwb3J0IGxhbmUgcmVvcmRlcmluZz8NCj4gDQoNCkZyb20gdGhlIGRhdGFzaGVldCwgJ01JUEkg aW5zaWRlIHRoZSBPVjAyQTEwIHByb3ZpZGVzIG9uZSBzaW5nbGUNCnVuaS1kaXJlY3Rpb25hbCBj bG9jayBsYW5lIGFuZCBvbmUgYmktZGlyZWN0aW9uYWwgZGF0YSBsYW5lIHNvbHV0aW9uIGZvcg0K Y29tbXVuaWNhdGlvbiBsaW5rcyBiZXR3ZWVuIGNvbXBvbmVudHMgaW5zaWRlIGEgbW9iaWxlIGRl dmljZS4NClRoZSBkYXRhIGxhbmUgaGFzIGZ1bGwgc3VwcG9ydCBmb3IgSFModW5pLWRpcmVjdGlv bmFsKSBhbmQNCkxQKGJpLWRpcmVjdGlvbmFsKSBkYXRhIHRyYW5zZmVyIG1vZGUuJw0KDQpUaGUg c2Vuc29yIGRvZXNuJ3Qgc3VwcG9ydCBsYW5lIHJlb3JkZXJpbmcsIHNvICdjbG9jay1sYW5lcycg cHJvcGVydHkNCndvdWxkIG5vdCBiZSBhZGRlZCBpbiBuZXh0IHJlbGVhc2UuDQoNCj4gU28gaWYg dGhlcmUncyBub3RoaW5nIHRvIGNvbnZleSB0byB0aGUgZHJpdmVyLCBhbHNvIHRoZSBkYXRhLWxh bmVzIHNob3VsZA0KPiBiZSByZW1vdmVkIElNTy4NCj4gDQoNCkhvd2V2ZXIsICdkYXRhLWxhbmVz JyBwcm9wZXJ0eSBtYXkgc3RpbGwgYmUgcmVxdWlyZWQuDQpJdCBpcyBrbm93biB0aGF0IGVpdGhl ciBkYXRhLWxhbmVzIG9yIGNsb2NrLWxhbmVzIGlzIGFuIGFycmF5IG9mDQpwaHlzaWNhbCBkYXRh IGxhbmUgaW5kZXhlcy4gUG9zaXRpb24gb2YgYW4gZW50cnkgZGV0ZXJtaW5lcyB0aGUgbG9naWNh bA0KbGFuZSBudW1iZXIsIHdoaWxlIHRoZSB2YWx1ZSBvZiBhbiBlbnRyeSBpbmRpY2F0ZXMgcGh5 c2ljYWwgbGFuZSwgZS5nLiwNCmZvciAxLWxhbmUgTUlQSSBDU0ktMiBidXMgd2UgY291bGQgaGF2 ZSAiZGF0YS1sYW5lcyA9IDwxPjsiLCBhc3N1bWluZw0KdGhlIGNsb2NrIGxhbmUgaXMgb24gaGFy ZHdhcmUgbGFuZSAwLg0KDQpBcyBtZW50aW9uZWQgZWFybGllciwgdGhlIE9WMDJBMTAgc2Vuc29y IHN1cHBvcnRzIG9ubHkgMUMxRCBhbmQgZG9lcyBub3QNCnN1cHBvcnQgbGFuZSByZW9yZGVyaW5n LCBzbyBoZXJlIHdlIHNoYWxsIHVzZSAnZGF0YS1sYW5lcyA9IDwxPicgYXMNCnRoZXJlIGlzIG9u bHkgYSBjbG9jayBsYW5lIGZvciBPVjAyQTEwLg0KDQpSZW1pbmRlcjoNCklmICdkYXRhLWxhbmVz JyBwcm9wZXJ0eSBpcyBub3QgcHJlc2VudCwgdGhlIGRyaXZlciB3b3VsZCBhc3N1bWUNCmZvdXIt bGFuZSBvcGVyYXRpb24uIFRoaXMgbWVhbnMgZm9yIG9uZS1sYW5lIG9yIHR3by1sYW5lIG9wZXJh dGlvbiwgdGhpcw0KcHJvcGVydHkgbXVzdCBiZSBwcmVzZW50IGFuZCBzZXQgdG8gdGhlIHJpZ2h0 IHBoeXNpY2FsIGxhbmUgaW5kZXhlcy4NCklmIHRoZSBoYXJkd2FyZSBkb2VzIG5vdCBzdXBwb3J0 IGxhbmUgcmVvcmRlcmluZywgbW9ub3RvbmljYWxseQ0KaW5jcmVtZW50ZWQgdmFsdWVzIHNoYWxs IGJlIHVzZWQgZnJvbSAwIG9yIDEgb253YXJkcywgZGVwZW5kaW5nIG9uDQp3aGV0aGVyIG9yIG5v dCB0aGVyZSBpcyBhbHNvIGEgY2xvY2sgbGFuZS4NCg0K