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Content-Type: text/plain X-TM-SNTS-SMTP: 28BF5888AD7FFF42060F79C9FA90991FFD4F7B771B1152B8920DEC76B1682A922000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org QWRkIGRldmljZXRyZWUgYmluZGluZ3MgZm9yIE1lZGlhdGVrIG10Njc3OSBTb0MgUGluIENvbnRy b2xsZXIuDQoNCkFja2VkLWJ5OiBTZWFuIFdhbmcgPHNlYW4ud2FuZ0BrZXJuZWwub3JnPg0KU2ln bmVkLW9mZi1ieTogSGFua3MgQ2hlbiA8aGFua3MuY2hlbkBtZWRpYXRlay5jb20+DQpTaWduZWQt b2ZmLWJ5OiBNYXJzIENoZW5nIDxtYXJzLmNoZW5nQG1lZGlhdGVrLmNvbT4NClNpZ25lZC1vZmYt Ynk6IEFuZHkgVGVuZyA8YW5keS50ZW5nQG1lZGlhdGVrLmNvbT4NCi0tLQ0KIGluY2x1ZGUvZHQt YmluZGluZ3MvcGluY3RybC9tdDY3NzktcGluZnVuYy5oIHwgMTI0MiArKysrKysrKysrKysrKysr KysrKysrKysrKw0KIDEgZmlsZSBjaGFuZ2VkLCAxMjQyIGluc2VydGlvbnMoKykNCiBjcmVhdGUg bW9kZSAxMDA2NDQgaW5jbHVkZS9kdC1iaW5kaW5ncy9waW5jdHJsL210Njc3OS1waW5mdW5jLmgN Cg0KZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHQtYmluZGluZ3MvcGluY3RybC9tdDY3NzktcGluZnVu Yy5oIGIvaW5jbHVkZS9kdC1iaW5kaW5ncy9waW5jdHJsL210Njc3OS1waW5mdW5jLmgNCm5ldyBm aWxlIG1vZGUgMTAwNjQ0DQppbmRleCAwMDAwMDAwLi44N2ZkYzQzDQotLS0gL2Rldi9udWxsDQor KysgYi9pbmNsdWRlL2R0LWJpbmRpbmdzL3BpbmN0cmwvbXQ2Nzc5LXBpbmZ1bmMuaA0KQEAgLTAs MCArMSwxMjQyIEBADQorLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAgKi8NCisv Kg0KKyAqIENvcHlyaWdodCAoQykgMjAxOSBNZWRpYVRlayBJbmMuDQorICogQXV0aG9yOiBBbmR5 IFRlbmcgPGFuZHkudGVuZ0BtZWRpYXRlay5jb20+DQorICoNCisgKi8NCisNCisjaWZuZGVmIF9f TVQ2Nzc5X1BJTkZVTkNfSA0KKyNkZWZpbmUgX19NVDY3NzlfUElORlVOQ19IDQorDQorI2luY2x1 ZGUgPGR0LWJpbmRpbmdzL3BpbmN0cmwvbXQ2NXh4Lmg+DQorDQorI2RlZmluZSBQSU5NVVhfR1BJ TzBfX0ZVTkNfR1BJTzAgKE1US19QSU5fTk8oMCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8w X19GVU5DX1NQSTZfTUkgKE1US19QSU5fTk8oMCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8w X19GVU5DX0kyUzVfTFJDSyAoTVRLX1BJTl9OTygwKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzBfX0ZVTkNfVERNX0xSQ0tfMk5EIChNVEtfUElOX05PKDApIHwgMykNCisjZGVmaW5lIFBJTk1V WF9HUElPMF9fRlVOQ19QQ00xX1NZTkMgKE1US19QSU5fTk8oMCkgfCA0KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8wX19GVU5DX1NDTF82MzA2IChNVEtfUElOX05PKDApIHwgNSkNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMF9fRlVOQ19UUF9HUElPMF9BTyAoTVRLX1BJTl9OTygwKSB8IDYpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzBfX0ZVTkNfUFRBX1JYRCAoTVRLX1BJTl9OTygwKSB8IDcpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzFfX0ZVTkNfR1BJTzEgKE1US19QSU5fTk8oMSkgfCAwKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xX19GVU5DX1NQSTZfQ1NCIChNVEtfUElOX05PKDEpIHwgMSkNCisjZGVm aW5lIFBJTk1VWF9HUElPMV9fRlVOQ19JMlM1X0RPIChNVEtfUElOX05PKDEpIHwgMikNCisjZGVm aW5lIFBJTk1VWF9HUElPMV9fRlVOQ19URE1fREFUQTBfMk5EIChNVEtfUElOX05PKDEpIHwgMykN CisjZGVmaW5lIFBJTk1VWF9HUElPMV9fRlVOQ19QQ00xX0RPMCAoTVRLX1BJTl9OTygxKSB8IDQp DQorI2RlZmluZSBQSU5NVVhfR1BJTzFfX0ZVTkNfU0RBXzYzMDYgKE1US19QSU5fTk8oMSkgfCA1 KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xX19GVU5DX1RQX0dQSU8xX0FPIChNVEtfUElOX05PKDEp IHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMV9fRlVOQ19QVEFfVFhEIChNVEtfUElOX05PKDEp IHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMl9fRlVOQ19HUElPMiAoTVRLX1BJTl9OTygy KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzJfX0ZVTkNfU1BJNl9NTyAoTVRLX1BJTl9OTygy KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzJfX0ZVTkNfSTJTNV9CQ0sgKE1US19QSU5fTk8o MikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yX19GVU5DX1RETV9CQ0tfMk5EIChNVEtfUElO X05PKDIpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMl9fRlVOQ19QQ00xX0NMSyAoTVRLX1BJ Tl9OTygyKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzJfX0ZVTkNfTURfSU5UMV9DMktfVUlN MF9IT1RfUExVRyAoTVRLX1BJTl9OTygyKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzJfX0ZV TkNfVFBfR1BJTzJfQU8gKE1US19QSU5fTk8oMikgfCA2KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQ SU8zX19GVU5DX0dQSU8zIChNVEtfUElOX05PKDMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP M19fRlVOQ19TUEk2X0NMSyAoTVRLX1BJTl9OTygzKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzNfX0ZVTkNfSTJTNV9NQ0sgKE1US19QSU5fTk8oMykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8zX19GVU5DX1RETV9NQ0tfMk5EIChNVEtfUElOX05PKDMpIHwgMykNCisjZGVmaW5lIFBJTk1V WF9HUElPM19fRlVOQ19FWFRfRlJBTUVfU1lOQyAoTVRLX1BJTl9OTygzKSB8IDQpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzNfX0ZVTkNfTURfSU5UMl9DMktfVUlNMV9IT1RfUExVRyAoTVRLX1BJTl9O TygzKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzNfX0ZVTkNfVFBfR1BJTzNfQU8gKE1US19Q SU5fTk8oMykgfCA2KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU80X19GVU5DX0dQSU80IChNVEtf UElOX05PKDQpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNF9fRlVOQ19TUEk3X01JIChNVEtf UElOX05PKDQpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNF9fRlVOQ19JMlMwX01DSyAoTVRL X1BJTl9OTyg0KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzRfX0ZVTkNfVERNX0RBVEExXzJO RCAoTVRLX1BJTl9OTyg0KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzRfX0ZVTkNfUENNMV9E TzEgKE1US19QSU5fTk8oNCkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80X19GVU5DX0RNSUMx X0NMSyAoTVRLX1BJTl9OTyg0KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzRfX0ZVTkNfVFBf R1BJTzRfQU8gKE1US19QSU5fTk8oNCkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80X19GVU5D X1NDTDggKE1US19QSU5fTk8oNCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81X19GVU5D X0dQSU81IChNVEtfUElOX05PKDUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNV9fRlVOQ19T UEk3X0NTQiAoTVRLX1BJTl9OTyg1KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzVfX0ZVTkNf STJTMF9CQ0sgKE1US19QSU5fTk8oNSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81X19GVU5D X1RETV9EQVRBMl8yTkQgKE1US19QSU5fTk8oNSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81 X19GVU5DX1BDTTFfRE8yIChNVEtfUElOX05PKDUpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElP NV9fRlVOQ19ETUlDMV9EQVQgKE1US19QSU5fTk8oNSkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU81X19GVU5DX1RQX0dQSU81X0FPIChNVEtfUElOX05PKDUpIHwgNikNCisjZGVmaW5lIFBJTk1V WF9HUElPNV9fRlVOQ19TREE4IChNVEtfUElOX05PKDUpIHwgNykNCisNCisjZGVmaW5lIFBJTk1V WF9HUElPNl9fRlVOQ19HUElPNiAoTVRLX1BJTl9OTyg2KSB8IDApDQorI2RlZmluZSBQSU5NVVhf R1BJTzZfX0ZVTkNfU1BJN19NTyAoTVRLX1BJTl9OTyg2KSB8IDEpDQorI2RlZmluZSBQSU5NVVhf R1BJTzZfX0ZVTkNfSTJTMF9MUkNLIChNVEtfUElOX05PKDYpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPNl9fRlVOQ19URE1fREFUQTNfMk5EIChNVEtfUElOX05PKDYpIHwgMykNCisjZGVmaW5l IFBJTk1VWF9HUElPNl9fRlVOQ19QQ00xX0RJIChNVEtfUElOX05PKDYpIHwgNCkNCisjZGVmaW5l IFBJTk1VWF9HUElPNl9fRlVOQ19ETUlDX0NMSyAoTVRLX1BJTl9OTyg2KSB8IDUpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzZfX0ZVTkNfVFBfR1BJTzZfQU8gKE1US19QSU5fTk8oNikgfCA2KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU82X19GVU5DX1NDTDkgKE1US19QSU5fTk8oNikgfCA3KQ0KKw0KKyNk ZWZpbmUgUElOTVVYX0dQSU83X19GVU5DX0dQSU83IChNVEtfUElOX05PKDcpIHwgMCkNCisjZGVm aW5lIFBJTk1VWF9HUElPN19fRlVOQ19TUEk3X0NMSyAoTVRLX1BJTl9OTyg3KSB8IDEpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzdfX0ZVTkNfSTJTMF9ESSAoTVRLX1BJTl9OTyg3KSB8IDIpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzdfX0ZVTkNfU1JDTEtFTkFJMSAoTVRLX1BJTl9OTyg3KSB8IDMpDQor I2RlZmluZSBQSU5NVVhfR1BJTzdfX0ZVTkNfRFZGU1JDX0VYVF9SRVEgKE1US19QSU5fTk8oNykg fCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83X19GVU5DX0RNSUNfREFUIChNVEtfUElOX05PKDcp IHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPN19fRlVOQ19UUF9HUElPN19BTyAoTVRLX1BJTl9O Tyg3KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzdfX0ZVTkNfU0RBOSAoTVRLX1BJTl9OTyg3 KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzhfX0ZVTkNfR1BJTzggKE1US19QSU5fTk8o OCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84X19GVU5DX1BXTV8wIChNVEtfUElOX05PKDgp IHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPOF9fRlVOQ19JMlMyX0RJMiAoTVRLX1BJTl9OTyg4 KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzhfX0ZVTkNfU1JDTEtFTkFJMCAoTVRLX1BJTl9O Tyg4KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzhfX0ZVTkNfVVJYRDEgKE1US19QSU5fTk8o OCkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84X19GVU5DX0kyUzBfTUNLIChNVEtfUElOX05P KDgpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPOF9fRlVOQ19DT05OX01DVV9EQkdBQ0tfTiAo TVRLX1BJTl9OTyg4KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzhfX0ZVTkNfSURESUcgKE1U S19QSU5fTk8oOCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU85X19GVU5DX0dQSU85IChN VEtfUElOX05PKDkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPOV9fRlVOQ19QV01fMyAoTVRL X1BJTl9OTyg5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzlfX0ZVTkNfTURfSU5UMCAoTVRL X1BJTl9OTyg5KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzlfX0ZVTkNfU1JDTEtFTkFJMSAo TVRLX1BJTl9OTyg5KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzlfX0ZVTkNfVVRYRDEgKE1U S19QSU5fTk8oOSkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU85X19GVU5DX0kyUzBfQkNLIChN VEtfUElOX05PKDkpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPOV9fRlVOQ19DT05OX01DVV9U UlNUX0IgKE1US19QSU5fTk8oOSkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU85X19GVU5DX1VT Ql9EUlZWQlVTIChNVEtfUElOX05PKDkpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTBf X0ZVTkNfR1BJTzEwIChNVEtfUElOX05PKDEwKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEw X19GVU5DX01TREMxX0NMS19BIChNVEtfUElOX05PKDEwKSB8IDEpDQorI2RlZmluZSBQSU5NVVhf R1BJTzEwX19GVU5DX1RQX1VSWEQxX0FPIChNVEtfUElOX05PKDEwKSB8IDIpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzEwX19GVU5DX0kyUzFfTFJDSyAoTVRLX1BJTl9OTygxMCkgfCAzKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMF9fRlVOQ19VQ1RTMCAoTVRLX1BJTl9OTygxMCkgfCA0KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMF9fRlVOQ19ETUlDMV9DTEsgKE1US19QSU5fTk8oMTApIHwgNSkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTBfX0ZVTkNfS1BDT0wyIChNVEtfUElOX05PKDEwKSB8IDYpDQor I2RlZmluZSBQSU5NVVhfR1BJTzEwX19GVU5DX1NDTDggKE1US19QSU5fTk8oMTApIHwgNykNCisN CisjZGVmaW5lIFBJTk1VWF9HUElPMTFfX0ZVTkNfR1BJTzExIChNVEtfUElOX05PKDExKSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzExX19GVU5DX01TREMxX0NNRF9BIChNVEtfUElOX05PKDEx KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzExX19GVU5DX1RQX1VUWEQxX0FPIChNVEtfUElO X05PKDExKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzExX19GVU5DX0kyUzFfRE8gKE1US19Q SU5fTk8oMTEpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTFfX0ZVTkNfVVJUUzAgKE1US19Q SU5fTk8oMTEpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTFfX0ZVTkNfRE1JQzFfREFUIChN VEtfUElOX05PKDExKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzExX19GVU5DX0tQUk9XMiAo TVRLX1BJTl9OTygxMSkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMV9fRlVOQ19TREE4IChN VEtfUElOX05PKDExKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyX19GVU5DX0dQSU8x MiAoTVRLX1BJTl9OTygxMikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMl9fRlVOQ19NU0RD MV9EQVQzX0EgKE1US19QSU5fTk8oMTIpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTJfX0ZV TkNfVFBfVVJYRDJfQU8gKE1US19QSU5fTk8oMTIpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElP MTJfX0ZVTkNfSTJTMV9NQ0sgKE1US19QSU5fTk8oMTIpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9H UElPMTJfX0ZVTkNfVUNUUzEgKE1US19QSU5fTk8oMTIpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTJfX0ZVTkNfRE1JQ19DTEsgKE1US19QSU5fTk8oMTIpIHwgNSkNCisjZGVmaW5lIFBJTk1V WF9HUElPMTJfX0ZVTkNfQU5UX1NFTDkgKE1US19QSU5fTk8oMTIpIHwgNikNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTJfX0ZVTkNfU0NMOSAoTVRLX1BJTl9OTygxMikgfCA3KQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU8xM19fRlVOQ19HUElPMTMgKE1US19QSU5fTk8oMTMpIHwgMCkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTNfX0ZVTkNfTVNEQzFfREFUMF9BIChNVEtfUElOX05PKDEzKSB8IDEpDQor I2RlZmluZSBQSU5NVVhfR1BJTzEzX19GVU5DX1RQX1VUWEQyX0FPIChNVEtfUElOX05PKDEzKSB8 IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzX19GVU5DX0kyUzFfQkNLIChNVEtfUElOX05PKDEz KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzX19GVU5DX1VSVFMxIChNVEtfUElOX05PKDEz KSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzX19GVU5DX0RNSUNfREFUIChNVEtfUElOX05P KDEzKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzX19GVU5DX0FOVF9TRUwxMCAoTVRLX1BJ Tl9OTygxMykgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xM19fRlVOQ19TREE5IChNVEtfUElO X05PKDEzKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0X19GVU5DX0dQSU8xNCAoTVRL X1BJTl9OTygxNCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNF9fRlVOQ19NU0RDMV9EQVQy X0EgKE1US19QSU5fTk8oMTQpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTRfX0ZVTkNfUFdN XzMgKE1US19QSU5fTk8oMTQpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTRfX0ZVTkNfSURE SUcgKE1US19QSU5fTk8oMTQpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTRfX0ZVTkNfTURf SU5UMCAoTVRLX1BJTl9OTygxNCkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNF9fRlVOQ19Q VEFfUlhEIChNVEtfUElOX05PKDE0KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0X19GVU5D X0FOVF9TRUwxMSAoTVRLX1BJTl9OTygxNCkgfCA2KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x NV9fRlVOQ19HUElPMTUgKE1US19QSU5fTk8oMTUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTVfX0ZVTkNfTVNEQzFfREFUMV9BIChNVEtfUElOX05PKDE1KSB8IDEpDQorI2RlZmluZSBQSU5N VVhfR1BJTzE1X19GVU5DX0RWRlNSQ19FWFRfUkVRIChNVEtfUElOX05PKDE1KSB8IDIpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzE1X19GVU5DX1VTQl9EUlZWQlVTIChNVEtfUElOX05PKDE1KSB8IDMp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE1X19GVU5DX01EX0lOVDFfQzJLX1VJTTBfSE9UX1BMVUcg KE1US19QSU5fTk8oMTUpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTVfX0ZVTkNfUFRBX1RY RCAoTVRLX1BJTl9OTygxNSkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNV9fRlVOQ19BTlRf U0VMMTIgKE1US19QSU5fTk8oMTUpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTZfX0ZV TkNfR1BJTzE2IChNVEtfUElOX05PKDE2KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE2X19G VU5DX1NSQ0xLRU5BSTAgKE1US19QSU5fTk8oMTYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTZfX0ZVTkNfRVhUX0ZSQU1FX1NZTkMgKE1US19QSU5fTk8oMTYpIHwgMikNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTZfX0ZVTkNfTUZHX0VKVEFHX1RSU1ROIChNVEtfUElOX05PKDE2KSB8IDMpDQor I2RlZmluZSBQSU5NVVhfR1BJTzE2X19GVU5DX01EX0lOVDJfQzJLX1VJTTFfSE9UX1BMVUcgKE1U S19QSU5fTk8oMTYpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTZfX0ZVTkNfQ09OTl9UQ1hP RU5BX1JFUSAoTVRLX1BJTl9OTygxNikgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNl9fRlVO Q19QV01fMiAoTVRLX1BJTl9OTygxNikgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNl9fRlVO Q19KVFJTVE5fU0VMMSAoTVRLX1BJTl9OTygxNikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xN19fRlVOQ19HUElPMTcgKE1US19QSU5fTk8oMTcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTdfX0ZVTkNfU1BJMF9BX01JIChNVEtfUElOX05PKDE3KSB8IDEpDQorI2RlZmluZSBQSU5N VVhfR1BJTzE3X19GVU5DX1NDUF9TUEkwX01JIChNVEtfUElOX05PKDE3KSB8IDIpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzE3X19GVU5DX01GR19FSlRBR19URE8gKE1US19QSU5fTk8oMTcpIHwgMykN CisjZGVmaW5lIFBJTk1VWF9HUElPMTdfX0ZVTkNfRFBJX0hTWU5DIChNVEtfUElOX05PKDE3KSB8 IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE3X19GVU5DX01GR19ERkRfSlRBR19URE8gKE1US19Q SU5fTk8oMTcpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTdfX0ZVTkNfREZEX1RETyAoTVRL X1BJTl9OTygxNykgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xN19fRlVOQ19KVERPX1NFTDEg KE1US19QSU5fTk8oMTcpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMThfX0ZVTkNfR1BJ TzE4IChNVEtfUElOX05PKDE4KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE4X19GVU5DX1NQ STBfQV9NTyAoTVRLX1BJTl9OTygxOCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOF9fRlVO Q19TQ1BfU1BJMF9NTyAoTVRLX1BJTl9OTygxOCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x OF9fRlVOQ19NRkdfRUpUQUdfVERJIChNVEtfUElOX05PKDE4KSB8IDMpDQorI2RlZmluZSBQSU5N VVhfR1BJTzE4X19GVU5DX0RQSV9WU1lOQyAoTVRLX1BJTl9OTygxOCkgfCA0KQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xOF9fRlVOQ19NRkdfREZEX0pUQUdfVERJIChNVEtfUElOX05PKDE4KSB8IDUp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE4X19GVU5DX0RGRF9UREkgKE1US19QSU5fTk8oMTgpIHwg NikNCisjZGVmaW5lIFBJTk1VWF9HUElPMThfX0ZVTkNfSlRESV9TRUwxIChNVEtfUElOX05PKDE4 KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5X19GVU5DX0dQSU8xOSAoTVRLX1BJTl9O TygxOSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOV9fRlVOQ19TUEkwX0FfQ1NCIChNVEtf UElOX05PKDE5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5X19GVU5DX1NDUF9TUEkwX0NT IChNVEtfUElOX05PKDE5KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5X19GVU5DX01GR19F SlRBR19UTVMgKE1US19QSU5fTk8oMTkpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTlfX0ZV TkNfRFBJX0RFIChNVEtfUElOX05PKDE5KSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5X19G VU5DX01GR19ERkRfSlRBR19UTVMgKE1US19QSU5fTk8oMTkpIHwgNSkNCisjZGVmaW5lIFBJTk1V WF9HUElPMTlfX0ZVTkNfREZEX1RNUyAoTVRLX1BJTl9OTygxOSkgfCA2KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xOV9fRlVOQ19KVE1TX1NFTDEgKE1US19QSU5fTk8oMTkpIHwgNykNCisNCisjZGVm aW5lIFBJTk1VWF9HUElPMjBfX0ZVTkNfR1BJTzIwIChNVEtfUElOX05PKDIwKSB8IDApDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzIwX19GVU5DX1NQSTBfQV9DTEsgKE1US19QSU5fTk8oMjApIHwgMSkN CisjZGVmaW5lIFBJTk1VWF9HUElPMjBfX0ZVTkNfU0NQX1NQSTBfQ0sgKE1US19QSU5fTk8oMjAp IHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMjBfX0ZVTkNfTUZHX0VKVEFHX1RDSyAoTVRLX1BJ Tl9OTygyMCkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMF9fRlVOQ19EUElfQ0sgKE1US19Q SU5fTk8oMjApIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjBfX0ZVTkNfTUZHX0RGRF9KVEFH X1RDSyAoTVRLX1BJTl9OTygyMCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMF9fRlVOQ19E RkRfVENLX1hJIChNVEtfUElOX05PKDIwKSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwX19G VU5DX0pUQ0tfU0VMMSAoTVRLX1BJTl9OTygyMCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQ SU8yMV9fRlVOQ19HUElPMjEgKE1US19QSU5fTk8oMjEpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMjFfX0ZVTkNfUFdNXzAgKE1US19QSU5fTk8oMjEpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9H UElPMjFfX0ZVTkNfQ01GTEFTSDAgKE1US19QSU5fTk8oMjEpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPMjFfX0ZVTkNfQ01WUkVGMiAoTVRLX1BJTl9OTygyMSkgfCAzKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8yMV9fRlVOQ19DTEtNMCAoTVRLX1BJTl9OTygyMSkgfCA0KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8yMV9fRlVOQ19BTlRfU0VMOSAoTVRLX1BJTl9OTygyMSkgfCA1KQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8yMV9fRlVOQ19DT05OX1RDWE9FTkFfUkVRIChNVEtfUElOX05PKDIxKSB8IDYp DQorI2RlZmluZSBQSU5NVVhfR1BJTzIxX19GVU5DX0RCR19NT05fQTI3IChNVEtfUElOX05PKDIx KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzIyX19GVU5DX0dQSU8yMiAoTVRLX1BJTl9O TygyMikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMl9fRlVOQ19QV01fMSAoTVRLX1BJTl9O TygyMikgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMl9fRlVOQ19DTUZMQVNIMSAoTVRLX1BJ Tl9OTygyMikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMl9fRlVOQ19DTVZSRUYzIChNVEtf UElOX05PKDIyKSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIyX19GVU5DX0NMS00xIChNVEtf UElOX05PKDIyKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIyX19GVU5DX0FOVF9TRUwxMCAo TVRLX1BJTl9OTygyMikgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMl9fRlVOQ19EQkdfTU9O X0EyOCAoTVRLX1BJTl9OTygyMikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8yM19fRlVO Q19HUElPMjMgKE1US19QSU5fTk8oMjMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjNfX0ZV TkNfUFdNXzIgKE1US19QSU5fTk8oMjMpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjNfX0ZV TkNfQ01GTEFTSDIgKE1US19QSU5fTk8oMjMpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMjNf X0ZVTkNfQ01WUkVGMCAoTVRLX1BJTl9OTygyMykgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8y M19fRlVOQ19DTEtNMiAoTVRLX1BJTl9OTygyMykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8y M19fRlVOQ19BTlRfU0VMMTEgKE1US19QSU5fTk8oMjMpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9H UElPMjNfX0ZVTkNfREJHX01PTl9BMjkgKE1US19QSU5fTk8oMjMpIHwgNykNCisNCisjZGVmaW5l IFBJTk1VWF9HUElPMjRfX0ZVTkNfR1BJTzI0IChNVEtfUElOX05PKDI0KSB8IDApDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzI0X19GVU5DX1BXTV8wIChNVEtfUElOX05PKDI0KSB8IDEpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzI0X19GVU5DX0NNRkxBU0gzIChNVEtfUElOX05PKDI0KSB8IDIpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzI0X19GVU5DX0NNVlJFRjEgKE1US19QSU5fTk8oMjQpIHwgMykNCisj ZGVmaW5lIFBJTk1VWF9HUElPMjRfX0ZVTkNfQ0xLTTMgKE1US19QSU5fTk8oMjQpIHwgNCkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMjRfX0ZVTkNfQU5UX1NFTDEyIChNVEtfUElOX05PKDI0KSB8IDUp DQorI2RlZmluZSBQSU5NVVhfR1BJTzI0X19GVU5DX0RCR19NT05fQTMwIChNVEtfUElOX05PKDI0 KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzI1X19GVU5DX0dQSU8yNSAoTVRLX1BJTl9O TygyNSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yNV9fRlVOQ19TUkNMS0VOQUkwIChNVEtf UElOX05PKDI1KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzI1X19GVU5DX1VDVFMwIChNVEtf UElOX05PKDI1KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzI1X19GVU5DX1NDTDggKE1US19Q SU5fTk8oMjUpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMjVfX0ZVTkNfQ01WUkVGNCAoTVRL X1BJTl9OTygyNSkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yNV9fRlVOQ19JMlMwX0xSQ0sg KE1US19QSU5fTk8oMjUpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjVfX0ZVTkNfQ09OTl9U Q1hPRU5BX1JFUSAoTVRLX1BJTl9OTygyNSkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yNV9f RlVOQ19EQkdfTU9OX0EzMSAoTVRLX1BJTl9OTygyNSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVY X0dQSU8yNl9fRlVOQ19HUElPMjYgKE1US19QSU5fTk8oMjYpIHwgMCkNCisjZGVmaW5lIFBJTk1V WF9HUElPMjZfX0ZVTkNfUFdNXzAgKE1US19QSU5fTk8oMjYpIHwgMSkNCisjZGVmaW5lIFBJTk1V WF9HUElPMjZfX0ZVTkNfVVJUUzAgKE1US19QSU5fTk8oMjYpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPMjZfX0ZVTkNfU0RBOCAoTVRLX1BJTl9OTygyNikgfCAzKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8yNl9fRlVOQ19DTEtNMCAoTVRLX1BJTl9OTygyNikgfCA0KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8yNl9fRlVOQ19JMlMwX0RJIChNVEtfUElOX05PKDI2KSB8IDUpDQorI2RlZmluZSBQSU5N VVhfR1BJTzI2X19GVU5DX0FHUFNfU1lOQyAoTVRLX1BJTl9OTygyNikgfCA2KQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8yNl9fRlVOQ19EQkdfTU9OX0EzMiAoTVRLX1BJTl9OTygyNikgfCA3KQ0KKw0K KyNkZWZpbmUgUElOTVVYX0dQSU8yN19fRlVOQ19HUElPMjcgKE1US19QSU5fTk8oMjcpIHwgMCkN CisjZGVmaW5lIFBJTk1VWF9HUElPMjdfX0ZVTkNfQVBfR09PRCAoTVRLX1BJTl9OTygyNykgfCAx KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8yOF9fRlVOQ19HUElPMjggKE1US19QSU5fTk8oMjgp IHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjhfX0ZVTkNfU0NMNSAoTVRLX1BJTl9OTygyOCkg fCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8yOV9fRlVOQ19HUElPMjkgKE1US19QSU5fTk8o MjkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjlfX0ZVTkNfU0RBNSAoTVRLX1BJTl9OTygy OSkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8zMF9fRlVOQ19HUElPMzAgKE1US19QSU5f Tk8oMzApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzBfX0ZVTkNfSTJTMV9NQ0sgKE1US19Q SU5fTk8oMzApIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzBfX0ZVTkNfSTJTM19NQ0sgKE1U S19QSU5fTk8oMzApIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMzBfX0ZVTkNfSTJTMl9NQ0sg KE1US19QSU5fTk8oMzApIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMzBfX0ZVTkNfRFBJX0Qw IChNVEtfUElOX05PKDMwKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzMwX19GVU5DX1NQSTRf TUkgKE1US19QSU5fTk8oMzApIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzBfX0ZVTkNfQ09O Tl9NQ1VfREJHSV9OIChNVEtfUElOX05PKDMwKSB8IDYpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJ TzMxX19GVU5DX0dQSU8zMSAoTVRLX1BJTl9OTygzMSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8zMV9fRlVOQ19JMlMxX0JDSyAoTVRLX1BJTl9OTygzMSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8zMV9fRlVOQ19JMlMzX0JDSyAoTVRLX1BJTl9OTygzMSkgfCAyKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8zMV9fRlVOQ19JMlMyX0JDSyAoTVRLX1BJTl9OTygzMSkgfCAzKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8zMV9fRlVOQ19EUElfRDEgKE1US19QSU5fTk8oMzEpIHwgNCkNCisjZGVmaW5l IFBJTk1VWF9HUElPMzFfX0ZVTkNfU1BJNF9DU0IgKE1US19QSU5fTk8oMzEpIHwgNSkNCisjZGVm aW5lIFBJTk1VWF9HUElPMzFfX0ZVTkNfQ09OTl9NQ1VfVERPIChNVEtfUElOX05PKDMxKSB8IDYp DQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzMyX19GVU5DX0dQSU8zMiAoTVRLX1BJTl9OTygzMikg fCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zMl9fRlVOQ19JMlMxX0xSQ0sgKE1US19QSU5fTk8o MzIpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzJfX0ZVTkNfSTJTM19MUkNLIChNVEtfUElO X05PKDMyKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzMyX19GVU5DX0kyUzJfTFJDSyAoTVRL X1BJTl9OTygzMikgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zMl9fRlVOQ19EUElfRDIgKE1U S19QSU5fTk8oMzIpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzJfX0ZVTkNfU1BJNF9NTyAo TVRLX1BJTl9OTygzMikgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zMl9fRlVOQ19DT05OX01D VV9UREkgKE1US19QSU5fTk8oMzIpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMzNfX0ZV TkNfR1BJTzMzIChNVEtfUElOX05PKDMzKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzMzX19G VU5DX0kyUzJfREkgKE1US19QSU5fTk8oMzMpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzNf X0ZVTkNfSTJTMF9ESSAoTVRLX1BJTl9OTygzMykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8z M19fRlVOQ19JMlM1X0RPIChNVEtfUElOX05PKDMzKSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzMzX19GVU5DX0RQSV9EMyAoTVRLX1BJTl9OTygzMykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8zM19fRlVOQ19TUEk0X0NMSyAoTVRLX1BJTl9OTygzMykgfCA1KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8zM19fRlVOQ19DT05OX01DVV9UTVMgKE1US19QSU5fTk8oMzMpIHwgNikNCisNCisjZGVm aW5lIFBJTk1VWF9HUElPMzRfX0ZVTkNfR1BJTzM0IChNVEtfUElOX05PKDM0KSB8IDApDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzM0X19GVU5DX0kyUzFfRE8gKE1US19QSU5fTk8oMzQpIHwgMSkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMzRfX0ZVTkNfSTJTM19ETyAoTVRLX1BJTl9OTygzNCkgfCAyKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU8zNF9fRlVOQ19JMlMyX0RJMiAoTVRLX1BJTl9OTygzNCkgfCAz KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zNF9fRlVOQ19EUElfRDQgKE1US19QSU5fTk8oMzQpIHwg NCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzRfX0ZVTkNfQUdQU19TWU5DIChNVEtfUElOX05PKDM0 KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM0X19GVU5DX0NPTk5fTUNVX1RDSyAoTVRLX1BJ Tl9OTygzNCkgfCA2KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8zNV9fRlVOQ19HUElPMzUgKE1U S19QSU5fTk8oMzUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzVfX0ZVTkNfVERNX0xSQ0sg KE1US19QSU5fTk8oMzUpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzVfX0ZVTkNfSTJTMV9M UkNLIChNVEtfUElOX05PKDM1KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM1X19GVU5DX0ky UzVfTFJDSyAoTVRLX1BJTl9OTygzNSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zNV9fRlVO Q19EUElfRDUgKE1US19QSU5fTk8oMzUpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzVfX0ZV TkNfU1BJNV9BX01PIChNVEtfUElOX05PKDM1KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM1 X19GVU5DX0lPX0pUQUdfVERJIChNVEtfUElOX05PKDM1KSB8IDYpDQorI2RlZmluZSBQSU5NVVhf R1BJTzM1X19GVU5DX1BXTV8yIChNVEtfUElOX05PKDM1KSB8IDcpDQorDQorI2RlZmluZSBQSU5N VVhfR1BJTzM2X19GVU5DX0dQSU8zNiAoTVRLX1BJTl9OTygzNikgfCAwKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8zNl9fRlVOQ19URE1fQkNLIChNVEtfUElOX05PKDM2KSB8IDEpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzM2X19GVU5DX0kyUzFfQkNLIChNVEtfUElOX05PKDM2KSB8IDIpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzM2X19GVU5DX0kyUzVfQkNLIChNVEtfUElOX05PKDM2KSB8IDMpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzM2X19GVU5DX0RQSV9ENiAoTVRLX1BJTl9OTygzNikgfCA0KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8zNl9fRlVOQ19TUEk1X0FfQ1NCIChNVEtfUElOX05PKDM2KSB8IDUp DQorI2RlZmluZSBQSU5NVVhfR1BJTzM2X19GVU5DX0lPX0pUQUdfVFJTVE4gKE1US19QSU5fTk8o MzYpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMzZfX0ZVTkNfU1JDTEtFTkFJMSAoTVRLX1BJ Tl9OTygzNikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8zN19fRlVOQ19HUElPMzcgKE1U S19QSU5fTk8oMzcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzdfX0ZVTkNfVERNX01DSyAo TVRLX1BJTl9OTygzNykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zN19fRlVOQ19JMlMxX01D SyAoTVRLX1BJTl9OTygzNykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zN19fRlVOQ19JMlM1 X01DSyAoTVRLX1BJTl9OTygzNykgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8zN19fRlVOQ19E UElfRDcgKE1US19QSU5fTk8oMzcpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzdfX0ZVTkNf U1BJNV9BX01JIChNVEtfUElOX05PKDM3KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM3X19G VU5DX0lPX0pUQUdfVENLIChNVEtfUElOX05PKDM3KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzM3X19GVU5DX1NSQ0xLRU5BSTAgKE1US19QSU5fTk8oMzcpIHwgNykNCisNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMzhfX0ZVTkNfR1BJTzM4IChNVEtfUElOX05PKDM4KSB8IDApDQorI2RlZmluZSBQ SU5NVVhfR1BJTzM4X19GVU5DX1RETV9EQVRBMCAoTVRLX1BJTl9OTygzOCkgfCAxKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8zOF9fRlVOQ19JMlMyX0RJIChNVEtfUElOX05PKDM4KSB8IDIpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzM4X19GVU5DX0kyUzVfRE8gKE1US19QSU5fTk8oMzgpIHwgMykNCisj ZGVmaW5lIFBJTk1VWF9HUElPMzhfX0ZVTkNfRFBJX0Q4IChNVEtfUElOX05PKDM4KSB8IDQpDQor I2RlZmluZSBQSU5NVVhfR1BJTzM4X19GVU5DX1NQSTVfQV9DTEsgKE1US19QSU5fTk8oMzgpIHwg NSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzhfX0ZVTkNfSU9fSlRBR19URE8gKE1US19QSU5fTk8o MzgpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMzhfX0ZVTkNfQ09OTl9UQ1hPRU5BX1JFUSAo TVRLX1BJTl9OTygzOCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8zOV9fRlVOQ19HUElP MzkgKE1US19QSU5fTk8oMzkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMzlfX0ZVTkNfVERN X0RBVEExIChNVEtfUElOX05PKDM5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM5X19GVU5D X0kyUzFfRE8gKE1US19QSU5fTk8oMzkpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMzlfX0ZV TkNfSTJTMl9ESTIgKE1US19QSU5fTk8oMzkpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMzlf X0ZVTkNfRFBJX0Q5IChNVEtfUElOX05PKDM5KSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzM5 X19GVU5DX0RWRlNSQ19FWFRfUkVRIChNVEtfUElOX05PKDM5KSB8IDUpDQorI2RlZmluZSBQSU5N VVhfR1BJTzM5X19GVU5DX0lPX0pUQUdfVE1TIChNVEtfUElOX05PKDM5KSB8IDYpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzM5X19GVU5DX0lERElHIChNVEtfUElOX05PKDM5KSB8IDcpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzQwX19GVU5DX0dQSU80MCAoTVRLX1BJTl9OTyg0MCkgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU80MF9fRlVOQ19URE1fREFUQTIgKE1US19QSU5fTk8oNDApIHwgMSkN CisjZGVmaW5lIFBJTk1VWF9HUElPNDBfX0ZVTkNfU0NMOSAoTVRLX1BJTl9OTyg0MCkgfCAyKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU80MF9fRlVOQ19QV01fMyAoTVRLX1BJTl9OTyg0MCkgfCAzKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU80MF9fRlVOQ19EUElfRDEwIChNVEtfUElOX05PKDQwKSB8IDQp DQorI2RlZmluZSBQSU5NVVhfR1BJTzQwX19GVU5DX1NSQ0xLRU5BSTAgKE1US19QSU5fTk8oNDAp IHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNDBfX0ZVTkNfREFQX01EMzJfU1dEIChNVEtfUElO X05PKDQwKSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzQwX19GVU5DX1VTQl9EUlZWQlVTIChN VEtfUElOX05PKDQwKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzQxX19GVU5DX0dQSU80 MSAoTVRLX1BJTl9OTyg0MSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80MV9fRlVOQ19URE1f REFUQTMgKE1US19QSU5fTk8oNDEpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNDFfX0ZVTkNf U0RBOSAoTVRLX1BJTl9OTyg0MSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80MV9fRlVOQ19Q V01fMSAoTVRLX1BJTl9OTyg0MSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80MV9fRlVOQ19E UElfRDExIChNVEtfUElOX05PKDQxKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzQxX19GVU5D X0NMS00xIChNVEtfUElOX05PKDQxKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzQxX19GVU5D X0RBUF9NRDMyX1NXQ0sgKE1US19QSU5fTk8oNDEpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9H UElPNDJfX0ZVTkNfR1BJTzQyIChNVEtfUElOX05PKDQyKSB8IDApDQorI2RlZmluZSBQSU5NVVhf R1BJTzQyX19GVU5DX0RJU1BfUFdNIChNVEtfUElOX05PKDQyKSB8IDEpDQorDQorI2RlZmluZSBQ SU5NVVhfR1BJTzQzX19GVU5DX0dQSU80MyAoTVRLX1BJTl9OTyg0MykgfCAwKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU80M19fRlVOQ19EU0lfVEUgKE1US19QSU5fTk8oNDMpIHwgMSkNCisNCisjZGVm aW5lIFBJTk1VWF9HUElPNDRfX0ZVTkNfR1BJTzQ0IChNVEtfUElOX05PKDQ0KSB8IDApDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzQ0X19GVU5DX0xDTV9SU1QgKE1US19QSU5fTk8oNDQpIHwgMSkNCisN CisjZGVmaW5lIFBJTk1VWF9HUElPNDVfX0ZVTkNfR1BJTzQ1IChNVEtfUElOX05PKDQ1KSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzQ1X19GVU5DX1NDTDYgKE1US19QSU5fTk8oNDUpIHwgMSkN CisjZGVmaW5lIFBJTk1VWF9HUElPNDVfX0ZVTkNfU0NQX1NDTDAgKE1US19QSU5fTk8oNDUpIHwg MikNCisjZGVmaW5lIFBJTk1VWF9HUElPNDVfX0ZVTkNfU0NQX1NDTDEgKE1US19QSU5fTk8oNDUp IHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPNDVfX0ZVTkNfU0NMXzYzMDYgKE1US19QSU5fTk8o NDUpIHwgNCkNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNDZfX0ZVTkNfR1BJTzQ2IChNVEtfUElO X05PKDQ2KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzQ2X19GVU5DX1NEQTYgKE1US19QSU5f Tk8oNDYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNDZfX0ZVTkNfU0NQX1NEQTAgKE1US19Q SU5fTk8oNDYpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPNDZfX0ZVTkNfU0NQX1NEQTEgKE1U S19QSU5fTk8oNDYpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPNDZfX0ZVTkNfU0RBXzYzMDYg KE1US19QSU5fTk8oNDYpIHwgNCkNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNDdfX0ZVTkNfR1BJ TzQ3IChNVEtfUElOX05PKDQ3KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzQ3X19GVU5DX1NQ STFfQV9NSSAoTVRLX1BJTl9OTyg0NykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80N19fRlVO Q19TQ1BfU1BJMV9BX01JIChNVEtfUElOX05PKDQ3KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzQ3X19GVU5DX0tQQ09MMiAoTVRLX1BJTl9OTyg0NykgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU80N19fRlVOQ19NRF9VUlhEMCAoTVRLX1BJTl9OTyg0NykgfCA0KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU80N19fRlVOQ19DT05OX1VBUlQwX1JYRCAoTVRLX1BJTl9OTyg0NykgfCA1KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU80N19fRlVOQ19TU1BNX1VSWERfQU8gKE1US19QSU5fTk8oNDcpIHwgNikN CisjZGVmaW5lIFBJTk1VWF9HUElPNDdfX0ZVTkNfREJHX01PTl9CMzIgKE1US19QSU5fTk8oNDcp IHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNDhfX0ZVTkNfR1BJTzQ4IChNVEtfUElOX05P KDQ4KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzQ4X19GVU5DX1NQSTFfQV9DU0IgKE1US19Q SU5fTk8oNDgpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNDhfX0ZVTkNfU0NQX1NQSTFfQV9D UyAoTVRLX1BJTl9OTyg0OCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OF9fRlVOQ19LUFJP VzIgKE1US19QSU5fTk8oNDgpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPNDhfX0ZVTkNfTURf VVRYRDAgKE1US19QSU5fTk8oNDgpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNDhfX0ZVTkNf Q09OTl9VQVJUMF9UWEQgKE1US19QSU5fTk8oNDgpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElP NDhfX0ZVTkNfU1NQTV9VVFhEX0FPIChNVEtfUElOX05PKDQ4KSB8IDYpDQorI2RlZmluZSBQSU5N VVhfR1BJTzQ4X19GVU5DX0RCR19NT05fQjMxIChNVEtfUElOX05PKDQ4KSB8IDcpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzQ5X19GVU5DX0dQSU80OSAoTVRLX1BJTl9OTyg0OSkgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19TUEkxX0FfTU8gKE1US19QSU5fTk8oNDkpIHwgMSkN CisjZGVmaW5lIFBJTk1VWF9HUElPNDlfX0ZVTkNfU0NQX1NQSTFfQV9NTyAoTVRLX1BJTl9OTyg0 OSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19VQ1RTMCAoTVRLX1BJTl9OTyg0 OSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19NRF9VUlhEMSAoTVRLX1BJTl9O Tyg0OSkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19QV01fMSAoTVRLX1BJTl9O Tyg0OSkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19UUF9VUlhEMl9BTyAoTVRL X1BJTl9OTyg0OSkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU80OV9fRlVOQ19EQkdfTU9OX0Iz MCAoTVRLX1BJTl9OTyg0OSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81MF9fRlVOQ19H UElPNTAgKE1US19QSU5fTk8oNTApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTBfX0ZVTkNf U1BJMV9BX0NMSyAoTVRLX1BJTl9OTyg1MCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81MF9f RlVOQ19TQ1BfU1BJMV9BX0NLIChNVEtfUElOX05PKDUwKSB8IDIpDQorI2RlZmluZSBQSU5NVVhf R1BJTzUwX19GVU5DX1VSVFMwIChNVEtfUElOX05PKDUwKSB8IDMpDQorI2RlZmluZSBQSU5NVVhf R1BJTzUwX19GVU5DX01EX1VUWEQxIChNVEtfUElOX05PKDUwKSB8IDQpDQorI2RlZmluZSBQSU5N VVhfR1BJTzUwX19GVU5DX1dJRklfVFhEIChNVEtfUElOX05PKDUwKSB8IDUpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzUwX19GVU5DX1RQX1VUWEQyX0FPIChNVEtfUElOX05PKDUwKSB8IDYpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzUwX19GVU5DX0RCR19NT05fQjI5IChNVEtfUElOX05PKDUwKSB8IDcp DQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzUxX19GVU5DX0dQSU81MSAoTVRLX1BJTl9OTyg1MSkg fCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81MV9fRlVOQ19TQ0wwIChNVEtfUElOX05PKDUxKSB8 IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzUyX19GVU5DX0dQSU81MiAoTVRLX1BJTl9OTyg1 MikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81Ml9fRlVOQ19TREEwIChNVEtfUElOX05PKDUy KSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzUzX19GVU5DX0dQSU81MyAoTVRLX1BJTl9O Tyg1MykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81M19fRlVOQ19VUlhEMCAoTVRLX1BJTl9O Tyg1MykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81M19fRlVOQ19VVFhEMCAoTVRLX1BJTl9O Tyg1MykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81M19fRlVOQ19NRF9VUlhEMCAoTVRLX1BJ Tl9OTyg1MykgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81M19fRlVOQ19NRF9VUlhEMSAoTVRL X1BJTl9OTyg1MykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81M19fRlVOQ19TU1BNX1VSWERf QU8gKE1US19QSU5fTk8oNTMpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTNfX0ZVTkNfQ09O Tl9VQVJUMF9SWEQgKE1US19QSU5fTk8oNTMpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElP NTRfX0ZVTkNfR1BJTzU0IChNVEtfUElOX05PKDU0KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJ TzU0X19GVU5DX1VUWEQwIChNVEtfUElOX05PKDU0KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzU0X19GVU5DX1VSWEQwIChNVEtfUElOX05PKDU0KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzU0X19GVU5DX01EX1VUWEQwIChNVEtfUElOX05PKDU0KSB8IDMpDQorI2RlZmluZSBQSU5NVVhf R1BJTzU0X19GVU5DX01EX1VUWEQxIChNVEtfUElOX05PKDU0KSB8IDQpDQorI2RlZmluZSBQSU5N VVhfR1BJTzU0X19GVU5DX1NTUE1fVVRYRF9BTyAoTVRLX1BJTl9OTyg1NCkgfCA1KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU81NF9fRlVOQ19XSUZJX1RYRCAoTVRLX1BJTl9OTyg1NCkgfCA2KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU81NF9fRlVOQ19DT05OX1VBUlQwX1RYRCAoTVRLX1BJTl9OTyg1NCkg fCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81NV9fRlVOQ19HUElPNTUgKE1US19QSU5fTk8o NTUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTVfX0ZVTkNfU0NMMyAoTVRLX1BJTl9OTyg1 NSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81NV9fRlVOQ19TQ1BfU0NMMCAoTVRLX1BJTl9O Tyg1NSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81NV9fRlVOQ19TQ1BfU0NMMSAoTVRLX1BJ Tl9OTyg1NSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81NV9fRlVOQ19TQ0xfNjMwNiAoTVRL X1BJTl9OTyg1NSkgfCA0KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81Nl9fRlVOQ19HUElPNTYg KE1US19QSU5fTk8oNTYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTZfX0ZVTkNfU0RBMyAo TVRLX1BJTl9OTyg1NikgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81Nl9fRlVOQ19TQ1BfU0RB MCAoTVRLX1BJTl9OTyg1NikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81Nl9fRlVOQ19TQ1Bf U0RBMSAoTVRLX1BJTl9OTyg1NikgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81Nl9fRlVOQ19T REFfNjMwNiAoTVRLX1BJTl9OTyg1NikgfCA0KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81N19f RlVOQ19HUElPNTcgKE1US19QSU5fTk8oNTcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTdf X0ZVTkNfS1BST1cxIChNVEtfUElOX05PKDU3KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzU3 X19GVU5DX1BXTV8xIChNVEtfUElOX05PKDU3KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzU3 X19GVU5DX0RWRlNSQ19FWFRfUkVRIChNVEtfUElOX05PKDU3KSB8IDMpDQorI2RlZmluZSBQSU5N VVhfR1BJTzU3X19GVU5DX0NMS00xIChNVEtfUElOX05PKDU3KSB8IDQpDQorI2RlZmluZSBQSU5N VVhfR1BJTzU3X19GVU5DX0lERElHIChNVEtfUElOX05PKDU3KSB8IDUpDQorI2RlZmluZSBQSU5N VVhfR1BJTzU3X19GVU5DX0NPTk5fVENYT0VOQV9SRVEgKE1US19QSU5fTk8oNTcpIHwgNikNCisj ZGVmaW5lIFBJTk1VWF9HUElPNTdfX0ZVTkNfTUJJU1RSRUFERU5fVFJJR0dFUiAoTVRLX1BJTl9O Tyg1NykgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU81OF9fRlVOQ19HUElPNTggKE1US19Q SU5fTk8oNTgpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNThfX0ZVTkNfS1BST1cwIChNVEtf UElOX05PKDU4KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzU4X19GVU5DX0RCR19NT05fQjI4 IChNVEtfUElOX05PKDU4KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzU5X19GVU5DX0dQ SU81OSAoTVRLX1BJTl9OTyg1OSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU81OV9fRlVOQ19L UENPTDAgKE1US19QSU5fTk8oNTkpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNTlfX0ZVTkNf REJHX01PTl9CMjcgKE1US19QSU5fTk8oNTkpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElP NjBfX0ZVTkNfR1BJTzYwIChNVEtfUElOX05PKDYwKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJ TzYwX19GVU5DX0tQQ09MMSAoTVRLX1BJTl9OTyg2MCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU82MF9fRlVOQ19QV01fMiAoTVRLX1BJTl9OTyg2MCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU82MF9fRlVOQ19VQ1RTMSAoTVRLX1BJTl9OTyg2MCkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU82MF9fRlVOQ19DTEtNMiAoTVRLX1BJTl9OTyg2MCkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU82MF9fRlVOQ19VU0JfRFJWVkJVUyAoTVRLX1BJTl9OTyg2MCkgfCA1KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU82MF9fRlVOQ19NQklTVFdSSVRFRU5fVFJJR0dFUiAoTVRLX1BJTl9OTyg2MCkgfCA3 KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU82MV9fRlVOQ19HUElPNjEgKE1US19QSU5fTk8oNjEp IHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjFfX0ZVTkNfU0NMMSAoTVRLX1BJTl9OTyg2MSkg fCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82MV9fRlVOQ19TQ1BfU0NMMCAoTVRLX1BJTl9OTyg2 MSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82MV9fRlVOQ19TQ1BfU0NMMSAoTVRLX1BJTl9O Tyg2MSkgfCAzKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU82Ml9fRlVOQ19HUElPNjIgKE1US19Q SU5fTk8oNjIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjJfX0ZVTkNfU0RBMSAoTVRLX1BJ Tl9OTyg2MikgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82Ml9fRlVOQ19TQ1BfU0RBMCAoTVRL X1BJTl9OTyg2MikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82Ml9fRlVOQ19TQ1BfU0RBMSAo TVRLX1BJTl9OTyg2MikgfCAzKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU82M19fRlVOQ19HUElP NjMgKE1US19QSU5fTk8oNjMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjNfX0ZVTkNfU1BJ Ml9NSSAoTVRLX1BJTl9OTyg2MykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82M19fRlVOQ19T Q1BfU1BJMl9NSSAoTVRLX1BJTl9OTyg2MykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82M19f RlVOQ19LUENPTDIgKE1US19QSU5fTk8oNjMpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPNjNf X0ZVTkNfTVJHX0RJIChNVEtfUElOX05PKDYzKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzYz X19GVU5DX01EX1VSWEQwIChNVEtfUElOX05PKDYzKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzYzX19GVU5DX0NPTk5fVUFSVDBfUlhEIChNVEtfUElOX05PKDYzKSB8IDYpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzYzX19GVU5DX0RCR19NT05fQjI2IChNVEtfUElOX05PKDYzKSB8IDcpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzY0X19GVU5DX0dQSU82NCAoTVRLX1BJTl9OTyg2NCkgfCAwKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU82NF9fRlVOQ19TUEkyX0NTQiAoTVRLX1BJTl9OTyg2NCkgfCAx KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82NF9fRlVOQ19TQ1BfU1BJMl9DUyAoTVRLX1BJTl9OTyg2 NCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82NF9fRlVOQ19LUFJPVzIgKE1US19QSU5fTk8o NjQpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPNjRfX0ZVTkNfTVJHX1NZTkMgKE1US19QSU5f Tk8oNjQpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjRfX0ZVTkNfTURfVVRYRDAgKE1US19Q SU5fTk8oNjQpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjRfX0ZVTkNfQ09OTl9VQVJUMF9U WEQgKE1US19QSU5fTk8oNjQpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPNjRfX0ZVTkNfREJH X01PTl9CMjUgKE1US19QSU5fTk8oNjQpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNjVf X0ZVTkNfR1BJTzY1IChNVEtfUElOX05PKDY1KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzY1 X19GVU5DX1NQSTJfTU8gKE1US19QSU5fTk8oNjUpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP NjVfX0ZVTkNfU0NQX1NQSTJfTU8gKE1US19QSU5fTk8oNjUpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPNjVfX0ZVTkNfU0NQX1NEQTEgKE1US19QSU5fTk8oNjUpIHwgMykNCisjZGVmaW5lIFBJ Tk1VWF9HUElPNjVfX0ZVTkNfTVJHX0RPIChNVEtfUElOX05PKDY1KSB8IDQpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzY1X19GVU5DX01EX1VSWEQxIChNVEtfUElOX05PKDY1KSB8IDUpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzY1X19GVU5DX1BXTV8zIChNVEtfUElOX05PKDY1KSB8IDYpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzY2X19GVU5DX0dQSU82NiAoTVRLX1BJTl9OTyg2NikgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU82Nl9fRlVOQ19TUEkyX0NMSyAoTVRLX1BJTl9OTyg2NikgfCAxKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU82Nl9fRlVOQ19TQ1BfU1BJMl9DSyAoTVRLX1BJTl9OTyg2Nikg fCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82Nl9fRlVOQ19TQ1BfU0NMMSAoTVRLX1BJTl9OTyg2 NikgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82Nl9fRlVOQ19NUkdfQ0xLIChNVEtfUElOX05P KDY2KSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY2X19GVU5DX01EX1VUWEQxIChNVEtfUElO X05PKDY2KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY2X19GVU5DX1dJRklfVFhEIChNVEtf UElOX05PKDY2KSB8IDYpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzY3X19GVU5DX0dQSU82NyAo TVRLX1BJTl9OTyg2NykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82N19fRlVOQ19JMlMzX0xS Q0sgKE1US19QSU5fTk8oNjcpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNjdfX0ZVTkNfSTJT MV9MUkNLIChNVEtfUElOX05PKDY3KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY3X19GVU5D X1VSWEQxIChNVEtfUElOX05PKDY3KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY3X19GVU5D X1BDTTBfU1lOQyAoTVRLX1BJTl9OTyg2NykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82N19f RlVOQ19JMlM1X0xSQ0sgKE1US19QSU5fTk8oNjcpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElP NjdfX0ZVTkNfQU5UX1NFTDkgKE1US19QSU5fTk8oNjcpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9H UElPNjdfX0ZVTkNfREJHX01PTl9CMTAgKE1US19QSU5fTk8oNjcpIHwgNykNCisNCisjZGVmaW5l IFBJTk1VWF9HUElPNjhfX0ZVTkNfR1BJTzY4IChNVEtfUElOX05PKDY4KSB8IDApDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzY4X19GVU5DX0kyUzNfRE8gKE1US19QSU5fTk8oNjgpIHwgMSkNCisjZGVm aW5lIFBJTk1VWF9HUElPNjhfX0ZVTkNfSTJTMV9ETyAoTVRLX1BJTl9OTyg2OCkgfCAyKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU82OF9fRlVOQ19VVFhEMSAoTVRLX1BJTl9OTyg2OCkgfCAzKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU82OF9fRlVOQ19QQ00wX0RPIChNVEtfUElOX05PKDY4KSB8IDQpDQor I2RlZmluZSBQSU5NVVhfR1BJTzY4X19GVU5DX0kyUzVfRE8gKE1US19QSU5fTk8oNjgpIHwgNSkN CisjZGVmaW5lIFBJTk1VWF9HUElPNjhfX0ZVTkNfQU5UX1NFTDEwIChNVEtfUElOX05PKDY4KSB8 IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY4X19GVU5DX0RCR19NT05fQjkgKE1US19QSU5fTk8o NjgpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNjlfX0ZVTkNfR1BJTzY5IChNVEtfUElO X05PKDY5KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzY5X19GVU5DX0kyUzNfTUNLIChNVEtf UElOX05PKDY5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY5X19GVU5DX0kyUzFfTUNLIChN VEtfUElOX05PKDY5KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY5X19GVU5DX1VSVFMxIChN VEtfUElOX05PKDY5KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzY5X19GVU5DX0FHUFNfU1lO QyAoTVRLX1BJTl9OTyg2OSkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82OV9fRlVOQ19JMlM1 X01DSyAoTVRLX1BJTl9OTyg2OSkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82OV9fRlVOQ19E VkZTUkNfRVhUX1JFUSAoTVRLX1BJTl9OTyg2OSkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU82 OV9fRlVOQ19EQkdfTU9OX0I4IChNVEtfUElOX05PKDY5KSB8IDcpDQorDQorI2RlZmluZSBQSU5N VVhfR1BJTzcwX19GVU5DX0dQSU83MCAoTVRLX1BJTl9OTyg3MCkgfCAwKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU83MF9fRlVOQ19JMlMwX0RJIChNVEtfUElOX05PKDcwKSB8IDEpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzcwX19GVU5DX0kyUzJfREkgKE1US19QSU5fTk8oNzApIHwgMikNCisjZGVmaW5l IFBJTk1VWF9HUElPNzBfX0ZVTkNfS1BDT0wyIChNVEtfUElOX05PKDcwKSB8IDMpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzcwX19GVU5DX1BDTTBfREkgKE1US19QSU5fTk8oNzApIHwgNCkNCisjZGVm aW5lIFBJTk1VWF9HUElPNzBfX0ZVTkNfSTJTMl9ESTIgKE1US19QSU5fTk8oNzApIHwgNSkNCisj ZGVmaW5lIFBJTk1VWF9HUElPNzBfX0ZVTkNfQU5UX1NFTDExIChNVEtfUElOX05PKDcwKSB8IDYp DQorI2RlZmluZSBQSU5NVVhfR1BJTzcwX19GVU5DX0RCR19NT05fQjcgKE1US19QSU5fTk8oNzAp IHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNzFfX0ZVTkNfR1BJTzcxIChNVEtfUElOX05P KDcxKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzcxX19GVU5DX0kyUzNfQkNLIChNVEtfUElO X05PKDcxKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzcxX19GVU5DX0kyUzFfQkNLIChNVEtf UElOX05PKDcxKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzcxX19GVU5DX0tQUk9XMiAoTVRL X1BJTl9OTyg3MSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83MV9fRlVOQ19QQ00wX0NMSyAo TVRLX1BJTl9OTyg3MSkgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83MV9fRlVOQ19JMlM1X0JD SyAoTVRLX1BJTl9OTyg3MSkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83MV9fRlVOQ19BTlRf U0VMMTIgKE1US19QSU5fTk8oNzEpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPNzFfX0ZVTkNf REJHX01PTl9CNiAoTVRLX1BJTl9OTyg3MSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU83 Ml9fRlVOQ19HUElPNzIgKE1US19QSU5fTk8oNzIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP NzJfX0ZVTkNfQlBJX0JVUzE5X09MQVQwIChNVEtfUElOX05PKDcyKSB8IDEpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzcyX19GVU5DX0NPTk5fQlBJX0JVUzE5X09MQVQwIChNVEtfUElOX05PKDcyKSB8 IDIpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzczX19GVU5DX0dQSU83MyAoTVRLX1BJTl9OTyg3 MykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83M19fRlVOQ19CUElfQlVTMThfUEFfVk0xIChN VEtfUElOX05PKDczKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzczX19GVU5DX0NPTk5fTUlQ STVfU0NMSyAoTVRLX1BJTl9OTyg3MykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83M19fRlVO Q19NSVBJNV9TQ0xLIChNVEtfUElOX05PKDczKSB8IDMpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJ Tzc0X19GVU5DX0dQSU83NCAoTVRLX1BJTl9OTyg3NCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU83NF9fRlVOQ19CUElfQlVTMTdfUEFfVk0wIChNVEtfUElOX05PKDc0KSB8IDEpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzc0X19GVU5DX0NPTk5fTUlQSTVfU0RBVEEgKE1US19QSU5fTk8oNzQpIHwg MikNCisjZGVmaW5lIFBJTk1VWF9HUElPNzRfX0ZVTkNfTUlQSTVfU0RBVEEgKE1US19QSU5fTk8o NzQpIHwgMykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPNzVfX0ZVTkNfR1BJTzc1IChNVEtfUElO X05PKDc1KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzc1X19GVU5DX0JQSV9CVVMyMF9PTEFU MSAoTVRLX1BJTl9OTyg3NSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83NV9fRlVOQ19DT05O X0JQSV9CVVMyMF9PTEFUMSAoTVRLX1BJTl9OTyg3NSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU83NV9fRlVOQ19SRklDMF9CU0lfRDIgKE1US19QSU5fTk8oNzUpIHwgMykNCisNCisjZGVmaW5l IFBJTk1VWF9HUElPNzZfX0ZVTkNfR1BJTzc2IChNVEtfUElOX05PKDc2KSB8IDApDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzc2X19GVU5DX1JGSUMwX0JTSV9EMSAoTVRLX1BJTl9OTyg3NikgfCAxKQ0K Kw0KKyNkZWZpbmUgUElOTVVYX0dQSU83N19fRlVOQ19HUElPNzcgKE1US19QSU5fTk8oNzcpIHwg MCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNzdfX0ZVTkNfUkZJQzBfQlNJX0QwIChNVEtfUElOX05P KDc3KSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzc4X19GVU5DX0dQSU83OCAoTVRLX1BJ Tl9OTyg3OCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83OF9fRlVOQ19CUElfQlVTNyAoTVRL X1BJTl9OTyg3OCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU83OF9fRlVOQ19EQkdfTU9OX0Iy NCAoTVRLX1BJTl9OTyg3OCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU83OV9fRlVOQ19H UElPNzkgKE1US19QSU5fTk8oNzkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPNzlfX0ZVTkNf QlBJX0JVUzYgKE1US19QSU5fTk8oNzkpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPNzlfX0ZV TkNfREJHX01PTl9CMjMgKE1US19QSU5fTk8oNzkpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9H UElPODBfX0ZVTkNfR1BJTzgwIChNVEtfUElOX05PKDgwKSB8IDApDQorI2RlZmluZSBQSU5NVVhf R1BJTzgwX19GVU5DX0JQSV9CVVM4IChNVEtfUElOX05PKDgwKSB8IDEpDQorI2RlZmluZSBQSU5N VVhfR1BJTzgwX19GVU5DX0RCR19NT05fQjIyIChNVEtfUElOX05PKDgwKSB8IDcpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzgxX19GVU5DX0dQSU84MSAoTVRLX1BJTl9OTyg4MSkgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU84MV9fRlVOQ19CUElfQlVTOSAoTVRLX1BJTl9OTyg4MSkgfCAxKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU84MV9fRlVOQ19EQkdfTU9OX0IyMSAoTVRLX1BJTl9OTyg4MSkg fCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU84Ml9fRlVOQ19HUElPODIgKE1US19QSU5fTk8o ODIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPODJfX0ZVTkNfQlBJX0JVUzEwIChNVEtfUElO X05PKDgyKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzgyX19GVU5DX0RCR19NT05fQjIwIChN VEtfUElOX05PKDgyKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzgzX19GVU5DX0dQSU84 MyAoTVRLX1BJTl9OTyg4MykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84M19fRlVOQ19CUElf QlVTMTEgKE1US19QSU5fTk8oODMpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPODNfX0ZVTkNf REJHX01PTl9CMTkgKE1US19QSU5fTk8oODMpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElP ODRfX0ZVTkNfR1BJTzg0IChNVEtfUElOX05PKDg0KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJ Tzg0X19GVU5DX0JQSV9CVVMxMiAoTVRLX1BJTl9OTyg4NCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU84NF9fRlVOQ19DT05OX0JQSV9CVVMxMiAoTVRLX1BJTl9OTyg4NCkgfCAyKQ0KKw0KKyNk ZWZpbmUgUElOTVVYX0dQSU84NV9fRlVOQ19HUElPODUgKE1US19QSU5fTk8oODUpIHwgMCkNCisj ZGVmaW5lIFBJTk1VWF9HUElPODVfX0ZVTkNfQlBJX0JVUzEzIChNVEtfUElOX05PKDg1KSB8IDEp DQorI2RlZmluZSBQSU5NVVhfR1BJTzg1X19GVU5DX0NPTk5fQlBJX0JVUzEzIChNVEtfUElOX05P KDg1KSB8IDIpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzg2X19GVU5DX0dQSU84NiAoTVRLX1BJ Tl9OTyg4NikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84Nl9fRlVOQ19CUElfQlVTMTQgKE1U S19QSU5fTk8oODYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPODZfX0ZVTkNfQ09OTl9CUElf QlVTMTQgKE1US19QSU5fTk8oODYpIHwgMikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPODdfX0ZV TkNfR1BJTzg3IChNVEtfUElOX05PKDg3KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzg3X19G VU5DX0JQSV9CVVMxNSAoTVRLX1BJTl9OTyg4NykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84 N19fRlVOQ19DT05OX0JQSV9CVVMxNSAoTVRLX1BJTl9OTyg4NykgfCAyKQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU84OF9fRlVOQ19HUElPODggKE1US19QSU5fTk8oODgpIHwgMCkNCisjZGVmaW5l IFBJTk1VWF9HUElPODhfX0ZVTkNfQlBJX0JVUzE2IChNVEtfUElOX05PKDg4KSB8IDEpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzg4X19GVU5DX0NPTk5fQlBJX0JVUzE2IChNVEtfUElOX05PKDg4KSB8 IDIpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzg5X19GVU5DX0dQSU84OSAoTVRLX1BJTl9OTyg4 OSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84OV9fRlVOQ19CUElfQlVTNSAoTVRLX1BJTl9O Tyg4OSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU84OV9fRlVOQ19EQkdfTU9OX0IxOCAoTVRL X1BJTl9OTyg4OSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU85MF9fRlVOQ19HUElPOTAg KE1US19QSU5fTk8oOTApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPOTBfX0ZVTkNfQlBJX0JV UzQgKE1US19QSU5fTk8oOTApIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPOTBfX0ZVTkNfREJH X01PTl9CMTcgKE1US19QSU5fTk8oOTApIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPOTFf X0ZVTkNfR1BJTzkxIChNVEtfUElOX05PKDkxKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzkx X19GVU5DX0JQSV9CVVMzIChNVEtfUElOX05PKDkxKSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhf R1BJTzkyX19GVU5DX0dQSU85MiAoTVRLX1BJTl9OTyg5MikgfCAwKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU85Ml9fRlVOQ19CUElfQlVTMiAoTVRLX1BJTl9OTyg5MikgfCAxKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU85Ml9fRlVOQ19EQkdfTU9OX0IxNiAoTVRLX1BJTl9OTyg5MikgfCA3KQ0KKw0KKyNk ZWZpbmUgUElOTVVYX0dQSU85M19fRlVOQ19HUElPOTMgKE1US19QSU5fTk8oOTMpIHwgMCkNCisj ZGVmaW5lIFBJTk1VWF9HUElPOTNfX0ZVTkNfQlBJX0JVUzEgKE1US19QSU5fTk8oOTMpIHwgMSkN CisNCisjZGVmaW5lIFBJTk1VWF9HUElPOTRfX0ZVTkNfR1BJTzk0IChNVEtfUElOX05PKDk0KSB8 IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzk0X19GVU5DX0JQSV9CVVMwIChNVEtfUElOX05PKDk0 KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzk0X19GVU5DX0RCR19NT05fQjE1IChNVEtfUElO X05PKDk0KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzk1X19GVU5DX0dQSU85NSAoTVRL X1BJTl9OTyg5NSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU85NV9fRlVOQ19NSVBJMF9TREFU QSAoTVRLX1BJTl9OTyg5NSkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU85Nl9fRlVOQ19H UElPOTYgKE1US19QSU5fTk8oOTYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPOTZfX0ZVTkNf TUlQSTBfU0NMSyAoTVRLX1BJTl9OTyg5NikgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU85 N19fRlVOQ19HUElPOTcgKE1US19QSU5fTk8oOTcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP OTdfX0ZVTkNfTUlQSTFfU0RBVEEgKE1US19QSU5fTk8oOTcpIHwgMSkNCisNCisjZGVmaW5lIFBJ Tk1VWF9HUElPOThfX0ZVTkNfR1BJTzk4IChNVEtfUElOX05PKDk4KSB8IDApDQorI2RlZmluZSBQ SU5NVVhfR1BJTzk4X19GVU5DX01JUEkxX1NDTEsgKE1US19QSU5fTk8oOTgpIHwgMSkNCisNCisj ZGVmaW5lIFBJTk1VWF9HUElPOTlfX0ZVTkNfR1BJTzk5IChNVEtfUElOX05PKDk5KSB8IDApDQor I2RlZmluZSBQSU5NVVhfR1BJTzk5X19GVU5DX01JUEkyX1NDTEsgKE1US19QSU5fTk8oOTkpIHwg MSkNCisjZGVmaW5lIFBJTk1VWF9HUElPOTlfX0ZVTkNfREJHX01PTl9CMTQgKE1US19QSU5fTk8o OTkpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTAwX19GVU5DX0dQSU8xMDAgKE1US19Q SU5fTk8oMTAwKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEwMF9fRlVOQ19NSVBJMl9TREFU QSAoTVRLX1BJTl9OTygxMDApIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTAwX19GVU5DX0RC R19NT05fQjEzIChNVEtfUElOX05PKDEwMCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MDFfX0ZVTkNfR1BJTzEwMSAoTVRLX1BJTl9OTygxMDEpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTAxX19GVU5DX01JUEkzX1NDTEsgKE1US19QSU5fTk8oMTAxKSB8IDEpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzEwMV9fRlVOQ19EQkdfTU9OX0IxMiAoTVRLX1BJTl9OTygxMDEpIHwgNykNCisN CisjZGVmaW5lIFBJTk1VWF9HUElPMTAyX19GVU5DX0dQSU8xMDIgKE1US19QSU5fTk8oMTAyKSB8 IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEwMl9fRlVOQ19NSVBJM19TREFUQSAoTVRLX1BJTl9O TygxMDIpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTAyX19GVU5DX0RCR19NT05fQjExIChN VEtfUElOX05PKDEwMikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMDNfX0ZVTkNfR1BJ TzEwMyAoTVRLX1BJTl9OTygxMDMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTAzX19GVU5D X01JUEk0X1NDTEsgKE1US19QSU5fTk8oMTAzKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEw M19fRlVOQ19DT05OX01JUEk0X1NDTEsgKE1US19QSU5fTk8oMTAzKSB8IDIpDQorDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzEwNF9fRlVOQ19HUElPMTA0IChNVEtfUElOX05PKDEwNCkgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMDRfX0ZVTkNfTUlQSTRfU0RBVEEgKE1US19QSU5fTk8oMTA0KSB8 IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEwNF9fRlVOQ19DT05OX01JUEk0X1NEQVRBIChNVEtf UElOX05PKDEwNCkgfCAyKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMDVfX0ZVTkNfR1BJTzEw NSAoTVRLX1BJTl9OTygxMDUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTA1X19GVU5DX0JQ SV9CVVMyMl9PTEFUMyAoTVRLX1BJTl9OTygxMDUpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTA1X19GVU5DX0NPTk5fQlBJX0JVUzIyX09MQVQzIChNVEtfUElOX05PKDEwNSkgfCAyKQ0KKw0K KyNkZWZpbmUgUElOTVVYX0dQSU8xMDZfX0ZVTkNfR1BJTzEwNiAoTVRLX1BJTl9OTygxMDYpIHwg MCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTA2X19GVU5DX0JQSV9CVVMyMV9PTEFUMiAoTVRLX1BJ Tl9OTygxMDYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTA2X19GVU5DX0NPTk5fQlBJX0JV UzIxX09MQVQyIChNVEtfUElOX05PKDEwNikgfCAyKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MDdfX0ZVTkNfR1BJTzEwNyAoTVRLX1BJTl9OTygxMDcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTA3X19GVU5DX0JQSV9CVVMyNF9BTlQxIChNVEtfUElOX05PKDEwNykgfCAxKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMDdfX0ZVTkNfQ09OTl9CUElfQlVTMjRfQU5UMSAoTVRLX1BJTl9OTygx MDcpIHwgMikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTA4X19GVU5DX0dQSU8xMDggKE1US19Q SU5fTk8oMTA4KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEwOF9fRlVOQ19CUElfQlVTMjVf QU5UMiAoTVRLX1BJTl9OTygxMDgpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTA4X19GVU5D X0NPTk5fQlBJX0JVUzI1X0FOVDIgKE1US19QSU5fTk8oMTA4KSB8IDIpDQorDQorI2RlZmluZSBQ SU5NVVhfR1BJTzEwOV9fRlVOQ19HUElPMTA5IChNVEtfUElOX05PKDEwOSkgfCAwKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMDlfX0ZVTkNfQlBJX0JVUzIzX0FOVDAgKE1US19QSU5fTk8oMTA5KSB8 IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEwOV9fRlVOQ19DT05OX0JQSV9CVVMyM19BTlQwIChN VEtfUElOX05PKDEwOSkgfCAyKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMTBfX0ZVTkNfR1BJ TzExMCAoTVRLX1BJTl9OTygxMTApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTEwX19GVU5D X1NDTDQgKE1US19QSU5fTk8oMTEwKSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzExMV9f RlVOQ19HUElPMTExIChNVEtfUElOX05PKDExMSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MTFfX0ZVTkNfU0RBNCAoTVRLX1BJTl9OTygxMTEpIHwgMSkNCisNCisjZGVmaW5lIFBJTk1VWF9H UElPMTEyX19GVU5DX0dQSU8xMTIgKE1US19QSU5fTk8oMTEyKSB8IDApDQorI2RlZmluZSBQSU5N VVhfR1BJTzExMl9fRlVOQ19TQ0wyIChNVEtfUElOX05PKDExMikgfCAxKQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU8xMTNfX0ZVTkNfR1BJTzExMyAoTVRLX1BJTl9OTygxMTMpIHwgMCkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTEzX19GVU5DX1NEQTIgKE1US19QSU5fTk8oMTEzKSB8IDEpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzExNF9fRlVOQ19HUElPMTE0IChNVEtfUElOX05PKDExNCkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMTRfX0ZVTkNfQ0xLTTAgKE1US19QSU5fTk8oMTE0KSB8 IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzExNF9fRlVOQ19TUEkzX01JIChNVEtfUElOX05PKDEx NCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMTRfX0ZVTkNfREJHX01PTl9CNSAoTVRLX1BJ Tl9OTygxMTQpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTE1X19GVU5DX0dQSU8xMTUg KE1US19QSU5fTk8oMTE1KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzExNV9fRlVOQ19DTEtN MSAoTVRLX1BJTl9OTygxMTUpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTE1X19GVU5DX1NQ STNfQ1NCIChNVEtfUElOX05PKDExNSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMTVfX0ZV TkNfREJHX01PTl9CNCAoTVRLX1BJTl9OTygxMTUpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9H UElPMTE2X19GVU5DX0dQSU8xMTYgKE1US19QSU5fTk8oMTE2KSB8IDApDQorI2RlZmluZSBQSU5N VVhfR1BJTzExNl9fRlVOQ19DTU1DTEswIChNVEtfUElOX05PKDExNikgfCAxKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xMTZfX0ZVTkNfREJHX01PTl9CMyAoTVRLX1BJTl9OTygxMTYpIHwgNykNCisN CisjZGVmaW5lIFBJTk1VWF9HUElPMTE3X19GVU5DX0dQSU8xMTcgKE1US19QSU5fTk8oMTE3KSB8 IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzExN19fRlVOQ19DTU1DTEsxIChNVEtfUElOX05PKDEx NykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMTdfX0ZVTkNfRFZGU1JDX0VYVF9SRVEgKE1U S19QSU5fTk8oMTE3KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzExN19fRlVOQ19EQkdfTU9O X0IyIChNVEtfUElOX05PKDExNykgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMThfX0ZV TkNfR1BJTzExOCAoTVRLX1BJTl9OTygxMTgpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTE4 X19GVU5DX0NMS00yIChNVEtfUElOX05PKDExOCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MThfX0ZVTkNfU1BJM19NTyAoTVRLX1BJTl9OTygxMTgpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9H UElPMTE4X19GVU5DX0RCR19NT05fQjEgKE1US19QSU5fTk8oMTE4KSB8IDcpDQorDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzExOV9fRlVOQ19HUElPMTE5IChNVEtfUElOX05PKDExOSkgfCAwKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMTlfX0ZVTkNfQ0xLTTMgKE1US19QSU5fTk8oMTE5KSB8IDEpDQor I2RlZmluZSBQSU5NVVhfR1BJTzExOV9fRlVOQ19TUEkzX0NMSyAoTVRLX1BJTl9OTygxMTkpIHwg MikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTE5X19GVU5DX0RCR19NT05fQjAgKE1US19QSU5fTk8o MTE5KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyMF9fRlVOQ19HUElPMTIwIChNVEtf UElOX05PKDEyMCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjBfX0ZVTkNfQ01NQ0xLMiAo TVRLX1BJTl9OTygxMjApIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTIwX19GVU5DX0NMS00y IChNVEtfUElOX05PKDEyMCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjBfX0ZVTkNfQU5U X1NFTDEyIChNVEtfUElOX05PKDEyMCkgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjBfX0ZV TkNfVFBfVUNUUzJfQU8gKE1US19QSU5fTk8oMTIwKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhf R1BJTzEyMV9fRlVOQ19HUElPMTIxIChNVEtfUElOX05PKDEyMSkgfCAwKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMjFfX0ZVTkNfQ01NQ0xLMyAoTVRLX1BJTl9OTygxMjEpIHwgMSkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTIxX19GVU5DX0NMS00zIChNVEtfUElOX05PKDEyMSkgfCAyKQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMjFfX0ZVTkNfRFZGU1JDX0VYVF9SRVEgKE1US19QSU5fTk8oMTIxKSB8 IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyMV9fRlVOQ19BTlRfU0VMMTEgKE1US19QSU5fTk8o MTIxKSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyMV9fRlVOQ19UUF9VUlRTMl9BTyAoTVRL X1BJTl9OTygxMjEpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTIyX19GVU5DX0dQSU8x MjIgKE1US19QSU5fTk8oMTIyKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyMl9fRlVOQ19D TVZSRUYxIChNVEtfUElOX05PKDEyMikgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjJfX0ZV TkNfUENNMF9TWU5DIChNVEtfUElOX05PKDEyMikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MjJfX0ZVTkNfU1JDTEtFTkFJMSAoTVRLX1BJTl9OTygxMjIpIHwgMykNCisjZGVmaW5lIFBJTk1V WF9HUElPMTIyX19GVU5DX0FHUFNfU1lOQyAoTVRLX1BJTl9OTygxMjIpIHwgNCkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTIyX19GVU5DX1BXTV8xIChNVEtfUElOX05PKDEyMikgfCA1KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMjJfX0ZVTkNfQU5UX1NFTDkgKE1US19QSU5fTk8oMTIyKSB8IDYpDQor I2RlZmluZSBQSU5NVVhfR1BJTzEyMl9fRlVOQ19UUF9VQ1RTMV9BTyAoTVRLX1BJTl9OTygxMjIp IHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTIzX19GVU5DX0dQSU8xMjMgKE1US19QSU5f Tk8oMTIzKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyM19fRlVOQ19QQ00wX0RJIChNVEtf UElOX05PKDEyMykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjNfX0ZVTkNfQURTUF9KVEFH X1RSU1ROIChNVEtfUElOX05PKDEyMykgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjNfX0ZV TkNfVlBVX1VESV9OVFJTVCAoTVRLX1BJTl9OTygxMjMpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTIzX19GVU5DX1NQTV9KVEFHX1RSU1ROIChNVEtfUElOX05PKDEyMykgfCA1KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMjNfX0ZVTkNfU1NQTV9KVEFHX1RSU1ROIChNVEtfUElOX05PKDEyMykg fCA2KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjRfX0ZVTkNfR1BJTzEyNCAoTVRLX1BJTl9O TygxMjQpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI0X19GVU5DX0NNVlJFRjIgKE1US19Q SU5fTk8oMTI0KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyNF9fRlVOQ19QQ00wX0NMSyAo TVRLX1BJTl9OTygxMjQpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI0X19GVU5DX01EX0lO VDAgKE1US19QSU5fTk8oMTI0KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyNF9fRlVOQ19F WFRfRlJBTUVfU1lOQyAoTVRLX1BJTl9OTygxMjQpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTI0X19GVU5DX1BXTV8yIChNVEtfUElOX05PKDEyNCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xMjRfX0ZVTkNfQU5UX1NFTDEwIChNVEtfUElOX05PKDEyNCkgfCA2KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMjRfX0ZVTkNfVFBfVVJUUzFfQU8gKE1US19QSU5fTk8oMTI0KSB8IDcpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzEyNV9fRlVOQ19HUElPMTI1IChNVEtfUElOX05PKDEyNSkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjVfX0ZVTkNfQ01WUkVGMyAoTVRLX1BJTl9OTygxMjUp IHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI1X19GVU5DX1BDTTBfRE8gKE1US19QSU5fTk8o MTI1KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyNV9fRlVOQ19BRFNQX0pUQUdfVE1TIChN VEtfUElOX05PKDEyNSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjVfX0ZVTkNfVlBVX1VE SV9UTVMgKE1US19QSU5fTk8oMTI1KSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyNV9fRlVO Q19TUE1fSlRBR19UTVMgKE1US19QSU5fTk8oMTI1KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzEyNV9fRlVOQ19TU1BNX0pUQUdfVE1TIChNVEtfUElOX05PKDEyNSkgfCA2KQ0KKw0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMjZfX0ZVTkNfR1BJTzEyNiAoTVRLX1BJTl9OTygxMjYpIHwgMCkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTI2X19GVU5DX0NNVlJFRjQgKE1US19QSU5fTk8oMTI2KSB8IDEp DQorI2RlZmluZSBQSU5NVVhfR1BJTzEyNl9fRlVOQ19DTUZMQVNIMCAoTVRLX1BJTl9OTygxMjYp IHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI2X19GVU5DX0NPTk5fTUNVX0FJQ0VfVE1TQyAo TVRLX1BJTl9OTygxMjYpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI3X19GVU5DX0dQ SU8xMjcgKE1US19QSU5fTk8oMTI3KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyN19fRlVO Q19DTVZSRUYwIChNVEtfUElOX05PKDEyNykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjdf X0ZVTkNfQ01GTEFTSDEgKE1US19QSU5fTk8oMTI3KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzEyN19fRlVOQ19DT05OX01DVV9BSUNFX1RDS0MgKE1US19QSU5fTk8oMTI3KSB8IDYpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzEyOF9fRlVOQ19HUElPMTI4IChNVEtfUElOX05PKDEyOCkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjhfX0ZVTkNfTUQxX1NJTTFfU0lPIChNVEtfUElOX05P KDEyOCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjhfX0ZVTkNfTUQxX1NJTTJfU0lPIChN VEtfUElOX05PKDEyOCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjhfX0ZVTkNfQ0NVX0pU QUdfVFJTVCAoTVRLX1BJTl9OTygxMjgpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI4X19G VU5DX0NPTk5fRFNQX0pJTlRQIChNVEtfUElOX05PKDEyOCkgfCA0KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8xMjhfX0ZVTkNfU0NQX0pUQUdfVFJTVE4gKE1US19QSU5fTk8oMTI4KSB8IDUpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzEyOF9fRlVOQ19MVlRTX0ZPVVQgKE1US19QSU5fTk8oMTI4KSB8IDYp DQorI2RlZmluZSBQSU5NVVhfR1BJTzEyOF9fRlVOQ19EQkdfTU9OX0EzIChNVEtfUElOX05PKDEy OCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjlfX0ZVTkNfR1BJTzEyOSAoTVRLX1BJ Tl9OTygxMjkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTI5X19GVU5DX01EMV9TSU0xX1NS U1QgKE1US19QSU5fTk8oMTI5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyOV9fRlVOQ19N RDFfU0lNMl9TUlNUIChNVEtfUElOX05PKDEyOSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MjlfX0ZVTkNfQ0NVX0pUQUdfVENLIChNVEtfUElOX05PKDEyOSkgfCAzKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMjlfX0ZVTkNfQ09OTl9EU1BfSkNLIChNVEtfUElOX05PKDEyOSkgfCA0KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMjlfX0ZVTkNfU0NQX0pUQUdfVENLIChNVEtfUElOX05PKDEyOSkg fCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMjlfX0ZVTkNfTFZUU19TRE8gKE1US19QSU5fTk8o MTI5KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEyOV9fRlVOQ19EQkdfTU9OX0E0IChNVEtf UElOX05PKDEyOSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzBfX0ZVTkNfR1BJTzEz MCAoTVRLX1BJTl9OTygxMzApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMwX19GVU5DX01E MV9TSU0xX1NDTEsgKE1US19QSU5fTk8oMTMwKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEz MF9fRlVOQ19NRDFfU0lNMl9TQ0xLIChNVEtfUElOX05PKDEzMCkgfCAyKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMzBfX0ZVTkNfTFZUU18yNk0gKE1US19QSU5fTk8oMTMwKSB8IDYpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzEzMF9fRlVOQ19EQkdfTU9OX0E1IChNVEtfUElOX05PKDEzMCkgfCA3KQ0K Kw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzFfX0ZVTkNfR1BJTzEzMSAoTVRLX1BJTl9OTygxMzEp IHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMxX19GVU5DX01EMV9TSU0yX1NDTEsgKE1US19Q SU5fTk8oMTMxKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzMV9fRlVOQ19NRDFfU0lNMV9T Q0xLIChNVEtfUElOX05PKDEzMSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzFfX0ZVTkNf Q0NVX0pUQUdfVERJIChNVEtfUElOX05PKDEzMSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MzFfX0ZVTkNfQ09OTl9EU1BfSkRJIChNVEtfUElOX05PKDEzMSkgfCA0KQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMzFfX0ZVTkNfU0NQX0pUQUdfVERJIChNVEtfUElOX05PKDEzMSkgfCA1KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMzFfX0ZVTkNfTFZUU19TQ0sgKE1US19QSU5fTk8oMTMxKSB8IDYp DQorI2RlZmluZSBQSU5NVVhfR1BJTzEzMV9fRlVOQ19EQkdfTU9OX0EwIChNVEtfUElOX05PKDEz MSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzJfX0ZVTkNfR1BJTzEzMiAoTVRLX1BJ Tl9OTygxMzIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMyX19GVU5DX01EMV9TSU0yX1NS U1QgKE1US19QSU5fTk8oMTMyKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzMl9fRlVOQ19N RDFfU0lNMV9TUlNUIChNVEtfUElOX05PKDEzMikgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x MzJfX0ZVTkNfQ0NVX0pUQUdfVE1TIChNVEtfUElOX05PKDEzMikgfCAzKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMzJfX0ZVTkNfQ09OTl9EU1BfSk1TIChNVEtfUElOX05PKDEzMikgfCA0KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMzJfX0ZVTkNfU0NQX0pUQUdfVE1TIChNVEtfUElOX05PKDEzMikg fCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzJfX0ZVTkNfTFZUU19TREkgKE1US19QSU5fTk8o MTMyKSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzMl9fRlVOQ19EQkdfTU9OX0ExIChNVEtf UElOX05PKDEzMikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzNfX0ZVTkNfR1BJTzEz MyAoTVRLX1BJTl9OTygxMzMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMzX19GVU5DX01E MV9TSU0yX1NJTyAoTVRLX1BJTl9OTygxMzMpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMz X19GVU5DX01EMV9TSU0xX1NJTyAoTVRLX1BJTl9OTygxMzMpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPMTMzX19GVU5DX0NDVV9KVEFHX1RETyAoTVRLX1BJTl9OTygxMzMpIHwgMykNCisjZGVm aW5lIFBJTk1VWF9HUElPMTMzX19GVU5DX0NPTk5fRFNQX0pETyAoTVRLX1BJTl9OTygxMzMpIHwg NCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMzX19GVU5DX1NDUF9KVEFHX1RETyAoTVRLX1BJTl9O TygxMzMpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTMzX19GVU5DX0xWVFNfU0NGIChNVEtf UElOX05PKDEzMykgfCA2KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzNfX0ZVTkNfREJHX01PTl9B MiAoTVRLX1BJTl9OTygxMzMpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTM0X19GVU5D X0dQSU8xMzQgKE1US19QSU5fTk8oMTM0KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNF9f RlVOQ19NU0RDMV9DTEsgKE1US19QSU5fTk8oMTM0KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzEzNF9fRlVOQ19QQ00xX0NMSyAoTVRLX1BJTl9OTygxMzQpIHwgMikNCisjZGVmaW5lIFBJTk1V WF9HUElPMTM0X19GVU5DX1NQSTVfQl9NSSAoTVRLX1BJTl9OTygxMzQpIHwgMykNCisjZGVmaW5l IFBJTk1VWF9HUElPMTM0X19GVU5DX1VESV9UQ0sgKE1US19QSU5fTk8oMTM0KSB8IDQpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzEzNF9fRlVOQ19DT05OX0RTUF9KQ0sgKE1US19QSU5fTk8oMTM0KSB8 IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNF9fRlVOQ19JUFVfSlRBR19UQ0sgKE1US19QSU5f Tk8oMTM0KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNF9fRlVOQ19KVENLX1NFTDMgKE1U S19QSU5fTk8oMTM0KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNV9fRlVOQ19HUElP MTM1IChNVEtfUElOX05PKDEzNSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzVfX0ZVTkNf TVNEQzFfQ01EIChNVEtfUElOX05PKDEzNSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzVf X0ZVTkNfUENNMV9TWU5DIChNVEtfUElOX05PKDEzNSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xMzVfX0ZVTkNfU1BJNV9CX0NTQiAoTVRLX1BJTl9OTygxMzUpIHwgMykNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTM1X19GVU5DX1VESV9UTVMgKE1US19QSU5fTk8oMTM1KSB8IDQpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzEzNV9fRlVOQ19DT05OX0RTUF9KTVMgKE1US19QSU5fTk8oMTM1KSB8IDUp DQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNV9fRlVOQ19JUFVfSlRBR19UTVMgKE1US19QSU5fTk8o MTM1KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNV9fRlVOQ19KVE1TX1NFTDMgKE1US19Q SU5fTk8oMTM1KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNl9fRlVOQ19HUElPMTM2 IChNVEtfUElOX05PKDEzNikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzZfX0ZVTkNfTVNE QzFfREFUMyAoTVRLX1BJTl9OTygxMzYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTM2X19G VU5DX1BDTTFfREkgKE1US19QSU5fTk8oMTM2KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEz Nl9fRlVOQ19TUEk1X0JfTU8gKE1US19QSU5fTk8oMTM2KSB8IDMpDQorI2RlZmluZSBQSU5NVVhf R1BJTzEzNl9fRlVOQ19DT05OX1RDWE9FTkFfUkVRIChNVEtfUElOX05PKDEzNikgfCA0KQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xMzZfX0ZVTkNfQ09OTl9EU1BfSklOVFAgKE1US19QSU5fTk8oMTM2 KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzNl9fRlVOQ19DT05OX01DVV9BSUNFX1RNU0Mg KE1US19QSU5fTk8oMTM2KSB8IDYpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzN19fRlVOQ19H UElPMTM3IChNVEtfUElOX05PKDEzNykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzdfX0ZV TkNfTVNEQzFfREFUMCAoTVRLX1BJTl9OTygxMzcpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTM3X19GVU5DX1BDTTFfRE8wIChNVEtfUElOX05PKDEzNykgfCAyKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8xMzdfX0ZVTkNfU1BJNV9CX0NMSyAoTVRLX1BJTl9OTygxMzcpIHwgMykNCisjZGVmaW5l IFBJTk1VWF9HUElPMTM3X19GVU5DX1VESV9UREkgKE1US19QSU5fTk8oMTM3KSB8IDQpDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzEzN19fRlVOQ19DT05OX0RTUF9KREkgKE1US19QSU5fTk8oMTM3KSB8 IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzN19fRlVOQ19JUFVfSlRBR19UREkgKE1US19QSU5f Tk8oMTM3KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzN19fRlVOQ19KVERJX1NFTDMgKE1U S19QSU5fTk8oMTM3KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzOF9fRlVOQ19HUElP MTM4IChNVEtfUElOX05PKDEzOCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzhfX0ZVTkNf TVNEQzFfREFUMiAoTVRLX1BJTl9OTygxMzgpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTM4 X19GVU5DX1BDTTFfRE8yIChNVEtfUElOX05PKDEzOCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xMzhfX0ZVTkNfQU5UX1NFTDExIChNVEtfUElOX05PKDEzOCkgfCAzKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xMzhfX0ZVTkNfVURJX05UUlNUIChNVEtfUElOX05PKDEzOCkgfCA0KQ0KKyNkZWZp bmUgUElOTVVYX0dQSU8xMzhfX0ZVTkNfQ09OTl9NQ1VfQUlDRV9UQ0tDIChNVEtfUElOX05PKDEz OCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzhfX0ZVTkNfSVBVX0pUQUdfVFJTVCAoTVRL X1BJTl9OTygxMzgpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTM4X19GVU5DX0pUUlNUTl9T RUwzIChNVEtfUElOX05PKDEzOCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xMzlfX0ZV TkNfR1BJTzEzOSAoTVRLX1BJTl9OTygxMzkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTM5 X19GVU5DX01TREMxX0RBVDEgKE1US19QSU5fTk8oMTM5KSB8IDEpDQorI2RlZmluZSBQSU5NVVhf R1BJTzEzOV9fRlVOQ19QQ00xX0RPMSAoTVRLX1BJTl9OTygxMzkpIHwgMikNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTM5X19GVU5DX0FOVF9TRUwxMiAoTVRLX1BJTl9OTygxMzkpIHwgMykNCisjZGVm aW5lIFBJTk1VWF9HUElPMTM5X19GVU5DX1VESV9URE8gKE1US19QSU5fTk8oMTM5KSB8IDQpDQor I2RlZmluZSBQSU5NVVhfR1BJTzEzOV9fRlVOQ19DT05OX0RTUF9KRE8gKE1US19QSU5fTk8oMTM5 KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzOV9fRlVOQ19JUFVfSlRBR19URE8gKE1US19Q SU5fTk8oMTM5KSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzEzOV9fRlVOQ19KVERPX1NFTDMg KE1US19QSU5fTk8oMTM5KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0MF9fRlVOQ19H UElPMTQwIChNVEtfUElOX05PKDE0MCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDBfX0ZV TkNfTURfSU5UMV9DMktfVUlNMF9IT1RfUExVRyAoTVRLX1BJTl9OTygxNDApIHwgMSkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTQwX19GVU5DX01EX0lOVDJfQzJLX1VJTTFfSE9UX1BMVUcgKE1US19Q SU5fTk8oMTQwKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0MF9fRlVOQ19BRFNQX1VSWEQw IChNVEtfUElOX05PKDE0MCkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDBfX0ZVTkNfU0NM XzYzMDYgKE1US19QSU5fTk8oMTQwKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0MF9fRlVO Q19QVEFfUlhEIChNVEtfUElOX05PKDE0MCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDBf X0ZVTkNfU1NQTV9VUlhEX0FPIChNVEtfUElOX05PKDE0MCkgfCA2KQ0KKw0KKyNkZWZpbmUgUElO TVVYX0dQSU8xNDFfX0ZVTkNfR1BJTzE0MSAoTVRLX1BJTl9OTygxNDEpIHwgMCkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTQxX19GVU5DX01EX0lOVDJfQzJLX1VJTTFfSE9UX1BMVUcgKE1US19QSU5f Tk8oMTQxKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0MV9fRlVOQ19NRF9JTlQxX0MyS19V SU0wX0hPVF9QTFVHIChNVEtfUElOX05PKDE0MSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x NDFfX0ZVTkNfQURTUF9VVFhEMCAoTVRLX1BJTl9OTygxNDEpIHwgMykNCisjZGVmaW5lIFBJTk1V WF9HUElPMTQxX19GVU5DX1NEQV82MzA2IChNVEtfUElOX05PKDE0MSkgfCA0KQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xNDFfX0ZVTkNfUFRBX1RYRCAoTVRLX1BJTl9OTygxNDEpIHwgNSkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTQxX19GVU5DX1NTUE1fVVRYRF9BTyAoTVRLX1BJTl9OTygxNDEpIHwg NikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQyX19GVU5DX0dQSU8xNDIgKE1US19QSU5fTk8o MTQyKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0Ml9fRlVOQ19TQ1BfVlJFUV9WQU8gKE1U S19QSU5fTk8oMTQyKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0Ml9fRlVOQ19EVkZTUkNf RVhUX1JFUSAoTVRLX1BJTl9OTygxNDIpIHwgMikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQz X19GVU5DX0dQSU8xNDMgKE1US19QSU5fTk8oMTQzKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJ TzE0M19fRlVOQ19BVURfREFUX01PU0kyIChNVEtfUElOX05PKDE0MykgfCAxKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xNDNfX0ZVTkNfREJHX01PTl9BOSAoTVRLX1BJTl9OTygxNDMpIHwgNykNCisN CisjZGVmaW5lIFBJTk1VWF9HUElPMTQ0X19GVU5DX0dQSU8xNDQgKE1US19QSU5fTk8oMTQ0KSB8 IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0NF9fRlVOQ19BVURfTkxFX01PU0kxIChNVEtfUElO X05PKDE0NCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDRfX0ZVTkNfQVVEX0NMS19NSVNP IChNVEtfUElOX05PKDE0NCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDRfX0ZVTkNfSTJT Ml9NQ0sgKE1US19QSU5fTk8oMTQ0KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0NF9fRlVO Q19VRElfVENLIChNVEtfUElOX05PKDE0NCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDRf X0ZVTkNfVUZTX1VOSVBST19TREEgKE1US19QSU5fTk8oMTQ0KSB8IDYpDQorI2RlZmluZSBQSU5N VVhfR1BJTzE0NF9fRlVOQ19EQkdfTU9OX0ExMCAoTVRLX1BJTl9OTygxNDQpIHwgNykNCisNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTQ1X19GVU5DX0dQSU8xNDUgKE1US19QSU5fTk8oMTQ1KSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE0NV9fRlVOQ19BVURfTkxFX01PU0kwIChNVEtfUElOX05P KDE0NSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDVfX0ZVTkNfQVVEX1NZTkNfTUlTTyAo TVRLX1BJTl9OTygxNDUpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ1X19GVU5DX0kyUzJf QkNLIChNVEtfUElOX05PKDE0NSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDVfX0ZVTkNf VURJX1RNUyAoTVRLX1BJTl9OTygxNDUpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ1X19G VU5DX0RCR19NT05fQTExIChNVEtfUElOX05PKDE0NSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVY X0dQSU8xNDZfX0ZVTkNfR1BJTzE0NiAoTVRLX1BJTl9OTygxNDYpIHwgMCkNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTQ2X19GVU5DX0FVRF9EQVRfTUlTTzIgKE1US19QSU5fTk8oMTQ2KSB8IDEpDQor I2RlZmluZSBQSU5NVVhfR1BJTzE0Nl9fRlVOQ19JMlMyX0RJMiAoTVRLX1BJTl9OTygxNDYpIHwg MykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ2X19GVU5DX1VESV9URE8gKE1US19QSU5fTk8oMTQ2 KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0Nl9fRlVOQ19EQkdfTU9OX0ExNCAoTVRLX1BJ Tl9OTygxNDYpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ3X19GVU5DX0dQSU8xNDcg KE1US19QSU5fTk8oMTQ3KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0N19fRlVOQ19BTlRf U0VMMCAoTVRLX1BJTl9OTygxNDcpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ3X19GVU5D X1BXTV8zIChNVEtfUElOX05PKDE0NykgfCAyKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNDhf X0ZVTkNfR1BJTzE0OCAoTVRLX1BJTl9OTygxNDgpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTQ4X19GVU5DX0FOVF9TRUwxIChNVEtfUElOX05PKDE0OCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8xNDhfX0ZVTkNfU1BJMF9CX01JIChNVEtfUElOX05PKDE0OCkgfCAyKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xNDhfX0ZVTkNfU1NQTV9VUlhEX0FPIChNVEtfUElOX05PKDE0OCkgfCAzKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU8xNDhfX0ZVTkNfVFBfVUNUUzJfQU8gKE1US19QSU5fTk8oMTQ4 KSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0OF9fRlVOQ19DTEtNMCAoTVRLX1BJTl9OTygx NDgpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ5X19GVU5DX0dQSU8xNDkgKE1US19Q SU5fTk8oMTQ5KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0OV9fRlVOQ19BTlRfU0VMMiAo TVRLX1BJTl9OTygxNDkpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTQ5X19GVU5DX1NQSTBf Ql9DU0IgKE1US19QSU5fTk8oMTQ5KSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE0OV9fRlVO Q19TU1BNX1VUWERfQU8gKE1US19QSU5fTk8oMTQ5KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJ TzE0OV9fRlVOQ19UUF9VUlRTMl9BTyAoTVRLX1BJTl9OTygxNDkpIHwgNSkNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTQ5X19GVU5DX0NPTk5fVENYT0VOQV9SRVEgKE1US19QSU5fTk8oMTQ5KSB8IDYp DQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1MF9fRlVOQ19HUElPMTUwIChNVEtfUElOX05PKDE1 MCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTBfX0ZVTkNfQU5UX1NFTDMgKE1US19QSU5f Tk8oMTUwKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1MF9fRlVOQ19TUEkwX0JfTU8gKE1U S19QSU5fTk8oMTUwKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1MF9fRlVOQ19VQ1RTMSAo TVRLX1BJTl9OTygxNTApIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTUwX19GVU5DX1RQX1VD VFMxX0FPIChNVEtfUElOX05PKDE1MCkgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTBfX0ZV TkNfSURESUcgKE1US19QSU5fTk8oMTUwKSB8IDYpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1MF9f RlVOQ19TQ0w5IChNVEtfUElOX05PKDE1MCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x NTFfX0ZVTkNfR1BJTzE1MSAoTVRLX1BJTl9OTygxNTEpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTUxX19GVU5DX0FOVF9TRUw0IChNVEtfUElOX05PKDE1MSkgfCAxKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xNTFfX0ZVTkNfU1BJMF9CX0NMSyAoTVRLX1BJTl9OTygxNTEpIHwgMikNCisjZGVm aW5lIFBJTk1VWF9HUElPMTUxX19GVU5DX1VSVFMxIChNVEtfUElOX05PKDE1MSkgfCAzKQ0KKyNk ZWZpbmUgUElOTVVYX0dQSU8xNTFfX0ZVTkNfVFBfVVJUUzFfQU8gKE1US19QSU5fTk8oMTUxKSB8 IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1MV9fRlVOQ19VU0JfRFJWVkJVUyAoTVRLX1BJTl9O TygxNTEpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTUxX19GVU5DX1NEQTkgKE1US19QSU5f Tk8oMTUxKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1Ml9fRlVOQ19HUElPMTUyIChN VEtfUElOX05PKDE1MikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTJfX0ZVTkNfQU5UX1NF TDUgKE1US19QSU5fTk8oMTUyKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1Ml9fRlVOQ19T UEkxX0JfTUkgKE1US19QSU5fTk8oMTUyKSB8IDIpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1Ml9f RlVOQ19DTEtNMyAoTVRLX1BJTl9OTygxNTIpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTUy X19GVU5DX1RQX1VSWEQxX0FPIChNVEtfUElOX05PKDE1MikgfCA1KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8xNTJfX0ZVTkNfU0NQX1NQSTFfQl9NSSAoTVRLX1BJTl9OTygxNTIpIHwgNikNCisjZGVm aW5lIFBJTk1VWF9HUElPMTUyX19GVU5DX1NDTDggKE1US19QSU5fTk8oMTUyKSB8IDcpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzE1M19fRlVOQ19HUElPMTUzIChNVEtfUElOX05PKDE1MykgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTNfX0ZVTkNfQU5UX1NFTDYgKE1US19QSU5fTk8oMTUz KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1M19fRlVOQ19TUEkxX0JfQ1NCIChNVEtfUElO X05PKDE1MykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTNfX0ZVTkNfU1JDTEtFTkFJMCAo TVRLX1BJTl9OTygxNTMpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTUzX19GVU5DX1BXTV8w IChNVEtfUElOX05PKDE1MykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTNfX0ZVTkNfVFBf VVRYRDFfQU8gKE1US19QSU5fTk8oMTUzKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1M19f RlVOQ19TQ1BfU1BJMV9CX0NTIChNVEtfUElOX05PKDE1MykgfCA2KQ0KKyNkZWZpbmUgUElOTVVY X0dQSU8xNTNfX0ZVTkNfU0RBOCAoTVRLX1BJTl9OTygxNTMpIHwgNykNCisNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTU0X19GVU5DX0dQSU8xNTQgKE1US19QSU5fTk8oMTU0KSB8IDApDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzE1NF9fRlVOQ19BTlRfU0VMNyAoTVRLX1BJTl9OTygxNTQpIHwgMSkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTU0X19GVU5DX1NQSTFfQl9NTyAoTVRLX1BJTl9OTygxNTQpIHwg MikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTU0X19GVU5DX1NSQ0xLRU5BSTEgKE1US19QSU5fTk8o MTU0KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1NF9fRlVOQ19UUF9VUlhEMl9BTyAoTVRL X1BJTl9OTygxNTQpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTU0X19GVU5DX1NDUF9TUEkx X0JfTU8gKE1US19QSU5fTk8oMTU0KSB8IDYpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1NV9f RlVOQ19HUElPMTU1IChNVEtfUElOX05PKDE1NSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x NTVfX0ZVTkNfQU5UX1NFTDggKE1US19QSU5fTk8oMTU1KSB8IDEpDQorI2RlZmluZSBQSU5NVVhf R1BJTzE1NV9fRlVOQ19TUEkxX0JfQ0xLIChNVEtfUElOX05PKDE1NSkgfCAyKQ0KKyNkZWZpbmUg UElOTVVYX0dQSU8xNTVfX0ZVTkNfTURfSU5UMCAoTVRLX1BJTl9OTygxNTUpIHwgMykNCisjZGVm aW5lIFBJTk1VWF9HUElPMTU1X19GVU5DX1RQX1VUWEQyX0FPIChNVEtfUElOX05PKDE1NSkgfCA1 KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTVfX0ZVTkNfU0NQX1NQSTFfQl9DSyAoTVRLX1BJTl9O TygxNTUpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTU1X19GVU5DX0RCR19NT05fQTE1IChN VEtfUElOX05PKDE1NSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTZfX0ZVTkNfR1BJ TzE1NiAoTVRLX1BJTl9OTygxNTYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTU2X19GVU5D X0NPTk5fVE9QX0NMSyAoTVRLX1BJTl9OTygxNTYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTU2X19GVU5DX0FVWElGX0NMSzAgKE1US19QSU5fTk8oMTU2KSB8IDIpDQorI2RlZmluZSBQSU5N VVhfR1BJTzE1Nl9fRlVOQ19EQkdfTU9OX0ExNiAoTVRLX1BJTl9OTygxNTYpIHwgNykNCisNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTU3X19GVU5DX0dQSU8xNTcgKE1US19QSU5fTk8oMTU3KSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE1N19fRlVOQ19DT05OX1RPUF9EQVRBIChNVEtfUElOX05P KDE1NykgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTdfX0ZVTkNfQVVYSUZfU1QwIChNVEtf UElOX05PKDE1NykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNTdfX0ZVTkNfREJHX01PTl9B MTcgKE1US19QSU5fTk8oMTU3KSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE1OF9fRlVO Q19HUElPMTU4IChNVEtfUElOX05PKDE1OCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNThf X0ZVTkNfQ09OTl9IUlNUX0IgKE1US19QSU5fTk8oMTU4KSB8IDEpDQorI2RlZmluZSBQSU5NVVhf R1BJTzE1OF9fRlVOQ19EQkdfTU9OX0ExOCAoTVRLX1BJTl9OTygxNTgpIHwgNykNCisNCisjZGVm aW5lIFBJTk1VWF9HUElPMTU5X19GVU5DX0dQSU8xNTkgKE1US19QSU5fTk8oMTU5KSB8IDApDQor I2RlZmluZSBQSU5NVVhfR1BJTzE1OV9fRlVOQ19DT05OX1dCX1BUQSAoTVRLX1BJTl9OTygxNTkp IHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTU5X19GVU5DX0RCR19NT05fQTE5IChNVEtfUElO X05PKDE1OSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjBfX0ZVTkNfR1BJTzE2MCAo TVRLX1BJTl9OTygxNjApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTYwX19GVU5DX0NPTk5f QlRfQ0xLIChNVEtfUElOX05PKDE2MCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjBfX0ZV TkNfQVVYSUZfQ0xLMSAoTVRLX1BJTl9OTygxNjApIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElP MTYwX19GVU5DX0RCR19NT05fQTIwIChNVEtfUElOX05PKDE2MCkgfCA3KQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU8xNjFfX0ZVTkNfR1BJTzE2MSAoTVRLX1BJTl9OTygxNjEpIHwgMCkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTYxX19GVU5DX0NPTk5fQlRfREFUQSAoTVRLX1BJTl9OTygxNjEpIHwg MSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTYxX19GVU5DX0FVWElGX1NUMSAoTVRLX1BJTl9OTygx NjEpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTYxX19GVU5DX0RCR19NT05fQTIxIChNVEtf UElOX05PKDE2MSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjJfX0ZVTkNfR1BJTzE2 MiAoTVRLX1BJTl9OTygxNjIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTYyX19GVU5DX0NP Tk5fV0ZfQ1RSTDAgKE1US19QSU5fTk8oMTYyKSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE2 Ml9fRlVOQ19EQkdfTU9OX0EyMiAoTVRLX1BJTl9OTygxNjIpIHwgNykNCisNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTYzX19GVU5DX0dQSU8xNjMgKE1US19QSU5fTk8oMTYzKSB8IDApDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzE2M19fRlVOQ19DT05OX1dGX0NUUkwxIChNVEtfUElOX05PKDE2MykgfCAx KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjNfX0ZVTkNfVUZTX01QSFlfU0NMIChNVEtfUElOX05P KDE2MykgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjNfX0ZVTkNfREJHX01PTl9BMjMgKE1U S19QSU5fTk8oMTYzKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE2NF9fRlVOQ19HUElP MTY0IChNVEtfUElOX05PKDE2NCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjRfX0ZVTkNf Q09OTl9XRl9DVFJMMiAoTVRLX1BJTl9OTygxNjQpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTY0X19GVU5DX1VGU19NUEhZX1NEQSAoTVRLX1BJTl9OTygxNjQpIHwgMikNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTY0X19GVU5DX0RCR19NT05fQTI0IChNVEtfUElOX05PKDE2NCkgfCA3KQ0KKw0K KyNkZWZpbmUgUElOTVVYX0dQSU8xNjVfX0ZVTkNfR1BJTzE2NSAoTVRLX1BJTl9OTygxNjUpIHwg MCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTY1X19GVU5DX0NPTk5fV0ZfQ1RSTDMgKE1US19QSU5f Tk8oMTY1KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE2NV9fRlVOQ19VRlNfVU5JUFJPX1NE QSAoTVRLX1BJTl9OTygxNjUpIHwgMikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTY1X19GVU5DX0RC R19NT05fQTI1IChNVEtfUElOX05PKDE2NSkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x NjZfX0ZVTkNfR1BJTzE2NiAoTVRLX1BJTl9OTygxNjYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTY2X19GVU5DX0NPTk5fV0ZfQ1RSTDQgKE1US19QSU5fTk8oMTY2KSB8IDEpDQorI2RlZmlu ZSBQSU5NVVhfR1BJTzE2Nl9fRlVOQ19VRlNfVU5JUFJPX1NDTCAoTVRLX1BJTl9OTygxNjYpIHwg MikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTY2X19GVU5DX0RCR19NT05fQTI2IChNVEtfUElOX05P KDE2NikgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNjdfX0ZVTkNfR1BJTzE2NyAoTVRL X1BJTl9OTygxNjcpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTY3X19GVU5DX01TREMwX0NN RCAoTVRLX1BJTl9OTygxNjcpIHwgMSkNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTY4X19GVU5D X0dQSU8xNjggKE1US19QSU5fTk8oMTY4KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE2OF9f RlVOQ19NU0RDMF9EQVQwIChNVEtfUElOX05PKDE2OCkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVY X0dQSU8xNjlfX0ZVTkNfR1BJTzE2OSAoTVRLX1BJTl9OTygxNjkpIHwgMCkNCisjZGVmaW5lIFBJ Tk1VWF9HUElPMTY5X19GVU5DX01TREMwX0RBVDIgKE1US19QSU5fTk8oMTY5KSB8IDEpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzE3MF9fRlVOQ19HUElPMTcwIChNVEtfUElOX05PKDE3MCkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzBfX0ZVTkNfTVNEQzBfREFUNCAoTVRLX1BJTl9OTygx NzApIHwgMSkNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTcxX19GVU5DX0dQSU8xNzEgKE1US19Q SU5fTk8oMTcxKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE3MV9fRlVOQ19NU0RDMF9EQVQ2 IChNVEtfUElOX05PKDE3MSkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzJfX0ZVTkNf R1BJTzE3MiAoTVRLX1BJTl9OTygxNzIpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTcyX19G VU5DX01TREMwX0RBVDEgKE1US19QSU5fTk8oMTcyKSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhf R1BJTzE3M19fRlVOQ19HUElPMTczIChNVEtfUElOX05PKDE3MykgfCAwKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xNzNfX0ZVTkNfTVNEQzBfREFUNSAoTVRLX1BJTl9OTygxNzMpIHwgMSkNCisNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTc0X19GVU5DX0dQSU8xNzQgKE1US19QSU5fTk8oMTc0KSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE3NF9fRlVOQ19NU0RDMF9EQVQ3IChNVEtfUElOX05PKDE3 NCkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzVfX0ZVTkNfR1BJTzE3NSAoTVRLX1BJ Tl9OTygxNzUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTc1X19GVU5DX01TREMwX0RTTCAo TVRLX1BJTl9OTygxNzUpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTc1X19GVU5DX0FOVF9T RUw5IChNVEtfUElOX05PKDE3NSkgfCAyKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzZfX0ZV TkNfR1BJTzE3NiAoTVRLX1BJTl9OTygxNzYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTc2 X19GVU5DX01TREMwX0NMSyAoTVRLX1BJTl9OTygxNzYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTc2X19GVU5DX0FOVF9TRUwxMCAoTVRLX1BJTl9OTygxNzYpIHwgMikNCisNCisjZGVmaW5l IFBJTk1VWF9HUElPMTc3X19GVU5DX0dQSU8xNzcgKE1US19QSU5fTk8oMTc3KSB8IDApDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzE3N19fRlVOQ19NU0RDMF9EQVQzIChNVEtfUElOX05PKDE3NykgfCAx KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzhfX0ZVTkNfR1BJTzE3OCAoTVRLX1BJTl9OTygx NzgpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTc4X19GVU5DX01TREMwX1JTVEIgKE1US19Q SU5fTk8oMTc4KSB8IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE3OV9fRlVOQ19HUElPMTc5 IChNVEtfUElOX05PKDE3OSkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xNzlfX0ZVTkNfUkZJ QzBfQlNJX0VOIChNVEtfUElOX05PKDE3OSkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8x ODBfX0ZVTkNfR1BJTzE4MCAoTVRLX1BJTl9OTygxODApIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTgwX19GVU5DX1JGSUMwX0JTSV9DSyAoTVRLX1BJTl9OTygxODApIHwgMSkNCisNCisjZGVm aW5lIFBJTk1VWF9HUElPMTgxX19GVU5DX0dQSU8xODEgKE1US19QSU5fTk8oMTgxKSB8IDApDQor I2RlZmluZSBQSU5NVVhfR1BJTzE4MV9fRlVOQ19TUkNMS0VOQTAgKE1US19QSU5fTk8oMTgxKSB8 IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE4Ml9fRlVOQ19HUElPMTgyIChNVEtfUElOX05P KDE4MikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODJfX0ZVTkNfU1JDTEtFTkExIChNVEtf UElOX05PKDE4MikgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODNfX0ZVTkNfR1BJTzE4 MyAoTVRLX1BJTl9OTygxODMpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTgzX19GVU5DX1dB VENIRE9HIChNVEtfUElOX05PKDE4MykgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODRf X0ZVTkNfR1BJTzE4NCAoTVRLX1BJTl9OTygxODQpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElP MTg0X19GVU5DX1BXUkFQX1NQSTBfTUkgKE1US19QSU5fTk8oMTg0KSB8IDEpDQorI2RlZmluZSBQ SU5NVVhfR1BJTzE4NF9fRlVOQ19QV1JBUF9TUEkwX01PIChNVEtfUElOX05PKDE4NCkgfCAyKQ0K Kw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODVfX0ZVTkNfR1BJTzE4NSAoTVRLX1BJTl9OTygxODUp IHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTg1X19GVU5DX1BXUkFQX1NQSTBfQ1NOIChNVEtf UElOX05PKDE4NSkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODZfX0ZVTkNfR1BJTzE4 NiAoTVRLX1BJTl9OTygxODYpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTg2X19GVU5DX1BX UkFQX1NQSTBfTU8gKE1US19QSU5fTk8oMTg2KSB8IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE4 Nl9fRlVOQ19QV1JBUF9TUEkwX01JIChNVEtfUElOX05PKDE4NikgfCAyKQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU8xODdfX0ZVTkNfR1BJTzE4NyAoTVRLX1BJTl9OTygxODcpIHwgMCkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTg3X19GVU5DX1BXUkFQX1NQSTBfQ0sgKE1US19QSU5fTk8oMTg3KSB8 IDEpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE4OF9fRlVOQ19HUElPMTg4IChNVEtfUElOX05P KDE4OCkgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODhfX0ZVTkNfUlRDMzJLX0NLIChNVEtf UElOX05PKDE4OCkgfCAxKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xODlfX0ZVTkNfR1BJTzE4 OSAoTVRLX1BJTl9OTygxODkpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTg5X19GVU5DX0FV RF9DTEtfTU9TSSAoTVRLX1BJTl9OTygxODkpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTg5 X19GVU5DX0kyUzFfTUNLIChNVEtfUElOX05PKDE4OSkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xODlfX0ZVTkNfVUZTX1VOSVBST19TQ0wgKE1US19QSU5fTk8oMTg5KSB8IDYpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzE5MF9fRlVOQ19HUElPMTkwIChNVEtfUElOX05PKDE5MCkgfCAwKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU8xOTBfX0ZVTkNfQVVEX1NZTkNfTU9TSSAoTVRLX1BJTl9OTygx OTApIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTkwX19GVU5DX0kyUzFfQkNLIChNVEtfUElO X05PKDE5MCkgfCAzKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTBfX0ZVTkNfREJHX01PTl9BNiAo TVRLX1BJTl9OTygxOTApIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTkxX19GVU5DX0dQ SU8xOTEgKE1US19QSU5fTk8oMTkxKSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5MV9fRlVO Q19BVURfREFUX01PU0kwIChNVEtfUElOX05PKDE5MSkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xOTFfX0ZVTkNfSTJTMV9MUkNLIChNVEtfUElOX05PKDE5MSkgfCAzKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xOTFfX0ZVTkNfREJHX01PTl9BNyAoTVRLX1BJTl9OTygxOTEpIHwgNykNCisNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTkyX19GVU5DX0dQSU8xOTIgKE1US19QSU5fTk8oMTkyKSB8IDAp DQorI2RlZmluZSBQSU5NVVhfR1BJTzE5Ml9fRlVOQ19BVURfREFUX01PU0kxIChNVEtfUElOX05P KDE5MikgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTJfX0ZVTkNfSTJTMV9ETyAoTVRLX1BJ Tl9OTygxOTIpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTkyX19GVU5DX1VGU19NUEhZX1NE QSAoTVRLX1BJTl9OTygxOTIpIHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTkyX19GVU5DX0RC R19NT05fQTggKE1US19QSU5fTk8oMTkyKSB8IDcpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5 M19fRlVOQ19HUElPMTkzIChNVEtfUElOX05PKDE5MykgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQ SU8xOTNfX0ZVTkNfQVVEX0RBVF9NSVNPMCAoTVRLX1BJTl9OTygxOTMpIHwgMSkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTkzX19GVU5DX1ZPV19EQVRfTUlTTyAoTVRLX1BJTl9OTygxOTMpIHwgMikN CisjZGVmaW5lIFBJTk1VWF9HUElPMTkzX19GVU5DX0kyUzJfTFJDSyAoTVRLX1BJTl9OTygxOTMp IHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTkzX19GVU5DX1VESV9UREkgKE1US19QSU5fTk8o MTkzKSB8IDUpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5M19fRlVOQ19EQkdfTU9OX0ExMiAoTVRL X1BJTl9OTygxOTMpIHwgNykNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk0X19GVU5DX0dQSU8x OTQgKE1US19QSU5fTk8oMTk0KSB8IDApDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5NF9fRlVOQ19B VURfREFUX01JU08xIChNVEtfUElOX05PKDE5NCkgfCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8x OTRfX0ZVTkNfVk9XX0NMS19NSVNPIChNVEtfUElOX05PKDE5NCkgfCAyKQ0KKyNkZWZpbmUgUElO TVVYX0dQSU8xOTRfX0ZVTkNfSTJTMl9ESSAoTVRLX1BJTl9OTygxOTQpIHwgMykNCisjZGVmaW5l IFBJTk1VWF9HUElPMTk0X19GVU5DX1VESV9OVFJTVCAoTVRLX1BJTl9OTygxOTQpIHwgNSkNCisj ZGVmaW5lIFBJTk1VWF9HUElPMTk0X19GVU5DX1VGU19NUEhZX1NDTCAoTVRLX1BJTl9OTygxOTQp IHwgNikNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk0X19GVU5DX0RCR19NT05fQTEzIChNVEtfUElO X05PKDE5NCkgfCA3KQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTVfX0ZVTkNfR1BJTzE5NSAo TVRLX1BJTl9OTygxOTUpIHwgMCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk1X19GVU5DX0FEU1Bf SlRBR19UQ0sgKE1US19QSU5fTk8oMTk1KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5NV9f RlVOQ19WUFVfVURJX1RDSyAoTVRLX1BJTl9OTygxOTUpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTk1X19GVU5DX1NQTV9KVEFHX1RDSyAoTVRLX1BJTl9OTygxOTUpIHwgNSkNCisjZGVmaW5l IFBJTk1VWF9HUElPMTk1X19GVU5DX1NTUE1fSlRBR19UQ0sgKE1US19QSU5fTk8oMTk1KSB8IDYp DQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5Nl9fRlVOQ19HUElPMTk2IChNVEtfUElOX05PKDE5 NikgfCAwKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTZfX0ZVTkNfQ01NQ0xLNCAoTVRLX1BJTl9O TygxOTYpIHwgMSkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk2X19GVU5DX0FEU1BfSlRBR19UREkg KE1US19QSU5fTk8oMTk2KSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzE5Nl9fRlVOQ19WUFVf VURJX1RESSAoTVRLX1BJTl9OTygxOTYpIHwgNCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk2X19G VU5DX1NQTV9KVEFHX1RESSAoTVRLX1BJTl9OTygxOTYpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9H UElPMTk2X19GVU5DX1NTUE1fSlRBR19UREkgKE1US19QSU5fTk8oMTk2KSB8IDYpDQorDQorI2Rl ZmluZSBQSU5NVVhfR1BJTzE5N19fRlVOQ19HUElPMTk3IChNVEtfUElOX05PKDE5NykgfCAwKQ0K KyNkZWZpbmUgUElOTVVYX0dQSU8xOTdfX0ZVTkNfQURTUF9KVEFHX1RETyAoTVRLX1BJTl9OTygx OTcpIHwgMykNCisjZGVmaW5lIFBJTk1VWF9HUElPMTk3X19GVU5DX1ZQVV9VRElfVERPIChNVEtf UElOX05PKDE5NykgfCA0KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTdfX0ZVTkNfU1BNX0pUQUdf VERPIChNVEtfUElOX05PKDE5NykgfCA1KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8xOTdfX0ZVTkNf U1NQTV9KVEFHX1RETyAoTVRLX1BJTl9OTygxOTcpIHwgNikNCisNCisjZGVmaW5lIFBJTk1VWF9H UElPMTk4X19GVU5DX0dQSU8xOTggKE1US19QSU5fTk8oMTk4KSB8IDApDQorI2RlZmluZSBQSU5N VVhfR1BJTzE5OF9fRlVOQ19TQ0w3IChNVEtfUElOX05PKDE5OCkgfCAxKQ0KKw0KKyNkZWZpbmUg UElOTVVYX0dQSU8xOTlfX0ZVTkNfR1BJTzE5OSAoTVRLX1BJTl9OTygxOTkpIHwgMCkNCisjZGVm aW5lIFBJTk1VWF9HUElPMTk5X19GVU5DX1NEQTcgKE1US19QSU5fTk8oMTk5KSB8IDEpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzIwMF9fRlVOQ19HUElPMjAwIChNVEtfUElOX05PKDIwMCkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDBfX0ZVTkNfVVJYRDEgKE1US19QSU5fTk8oMjAwKSB8 IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMF9fRlVOQ19BRFNQX1VSWEQwIChNVEtfUElOX05P KDIwMCkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDBfX0ZVTkNfVFBfVVJYRDFfQU8gKE1U S19QSU5fTk8oMjAwKSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMF9fRlVOQ19TU1BNX1VS WERfQU8gKE1US19QSU5fTk8oMjAwKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMF9fRlVO Q19UUF9VUlhEMl9BTyAoTVRLX1BJTl9OTygyMDApIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MjAwX19GVU5DX01CSVNUUkVBREVOX1RSSUdHRVIgKE1US19QSU5fTk8oMjAwKSB8IDYpDQorDQor I2RlZmluZSBQSU5NVVhfR1BJTzIwMV9fRlVOQ19HUElPMjAxIChNVEtfUElOX05PKDIwMSkgfCAw KQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDFfX0ZVTkNfVVRYRDEgKE1US19QSU5fTk8oMjAxKSB8 IDEpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMV9fRlVOQ19BRFNQX1VUWEQwIChNVEtfUElOX05P KDIwMSkgfCAyKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDFfX0ZVTkNfVFBfVVRYRDFfQU8gKE1U S19QSU5fTk8oMjAxKSB8IDMpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMV9fRlVOQ19TU1BNX1VU WERfQU8gKE1US19QSU5fTk8oMjAxKSB8IDQpDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwMV9fRlVO Q19UUF9VVFhEMl9BTyAoTVRLX1BJTl9OTygyMDEpIHwgNSkNCisjZGVmaW5lIFBJTk1VWF9HUElP MjAxX19GVU5DX01CSVNUV1JJVEVFTl9UUklHR0VSIChNVEtfUElOX05PKDIwMSkgfCA2KQ0KKw0K KyNkZWZpbmUgUElOTVVYX0dQSU8yMDJfX0ZVTkNfR1BJTzIwMiAoTVRLX1BJTl9OTygyMDIpIHwg MCkNCisjZGVmaW5lIFBJTk1VWF9HUElPMjAyX19GVU5DX1BXTV8zIChNVEtfUElOX05PKDIwMikg fCAxKQ0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDJfX0ZVTkNfQ0xLTTMgKE1US19QSU5fTk8oMjAy KSB8IDIpDQorDQorI2RlZmluZSBQSU5NVVhfR1BJTzIwM19fRlVOQ19HUElPMjAzIChNVEtfUElO X05PKDIwMykgfCAwKQ0KKw0KKyNkZWZpbmUgUElOTVVYX0dQSU8yMDRfX0ZVTkNfR1BJTzIwNCAo TVRLX1BJTl9OTygyMDQpIHwgMCkNCisNCisjZGVmaW5lIFBJTk1VWF9HUElPMjA1X19GVU5DX0dQ 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Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 04:34:10 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 19:34:02 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Jun 2020 19:34:02 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , "Michael Turquette" , Stephen Boyd , "Sean Wang" Subject: [PATCH v6 2/7] pinctrl: mediatek: update pinmux definitions for mt6779 Date: Thu, 18 Jun 2020 19:33:33 +0800 Message-ID: <1592480018-3340-3-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 28BF5888AD7FFF42060F79C9FA90991FFD4F7B771B1152B8920DEC76B1682A922000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200618_044412_787123_F4145661 X-CRM114-Status: UNSURE ( 9.25 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , wsd_upstream@mediatek.com, Andy Teng , Mars Cheng , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, mtk01761 , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Hanks Chen Signed-off-by: Mars Cheng Signed-off-by: Andy Teng --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++++++++++++++++++++++++++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 0000000..87fdc43 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_SRCLKENAI1 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_UTXD1 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_I2S0_BCK (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_TP_URXD1_AO (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S1_LRCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_UCTS0 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_KPCOL2 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_SCL8 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_TP_UTXD1_AO (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S1_DO (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_URTS0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_KPROW2 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_SDA8 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_TP_URXD2_AO (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S1_MCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_DMIC_CLK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ANT_SEL9 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_SCL9 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_TP_UTXD2_AO (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S1_BCK (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_DMIC_DAT (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_SDA9 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_PWM_3 (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_INT0 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_PTA_RXD (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_PTA_TXD (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_MFG_EJTAG_TRSTN (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_PWM_2 (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SPI0_A_MI (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SCP_SPI0_MI (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_MFG_EJTAG_TDO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_DPI_HSYNC (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_DFD_TDO (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_JTDO_SEL1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SPI0_A_MO (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SCP_SPI0_MO (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_MFG_EJTAG_TDI (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_DPI_VSYNC (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_DFD_TDI (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_JTDI_SEL1 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SPI0_A_CSB (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SCP_SPI0_CS (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_MFG_EJTAG_TMS (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_DPI_DE (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_DFD_TMS (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_JTMS_SEL1 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SPI0_A_CLK (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SCP_SPI0_CK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_MFG_EJTAG_TCK (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_DPI_CK (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_DFD_TCK_XI (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_JTCK_SEL1 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_PWM_0 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CMFLASH0 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CMVREF2 (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CLKM0 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_ANT_SEL9 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A27 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_PWM_1 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_CMFLASH1 (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_CMVREF3 (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_CLKM1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL10 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A28 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_PWM_2 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_CMFLASH2 (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_CMVREF0 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_CLKM2 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL11 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A29 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_PWM_0 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_CMFLASH3 (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_CMVREF1 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_CLKM3 (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_ANT_SEL12 (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DBG_MON_A30 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_UCTS0 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SCL8 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_CMVREF4 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_I2S0_LRCK (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A31 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_URTS0 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SDA8 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_I2S0_DI (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_AGPS_SYNC (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A32 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_AP_GOOD (MTK_PIN_NO(27) | 1) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_SCL5 (MTK_PIN_NO(28) | 1) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_SDA5 (MTK_PIN_NO(29) | 1) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_I2S1_MCK (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_I2S3_MCK (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_I2S2_MCK (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DPI_D0 (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_SPI4_MI (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(30) | 6) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2S1_BCK (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_I2S3_BCK (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_I2S2_BCK (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DPI_D1 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_SPI4_CSB (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_CONN_MCU_TDO (MTK_PIN_NO(31) | 6) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2S1_LRCK (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I2S3_LRCK (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I2S2_LRCK (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DPI_D2 (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SPI4_MO (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 6) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_I2S2_DI (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_I2S0_DI (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_I2S5_DO (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DPI_D3 (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_SPI4_CLK (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_CONN_MCU_TMS (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I2S1_DO (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I2S3_DO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DPI_D4 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_AGPS_SYNC (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_CONN_MCU_TCK (MTK_PIN_NO(34) | 6) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_TDM_LRCK (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_I2S1_LRCK (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_I2S5_LRCK (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DPI_D5 (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_SPI5_A_MO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_IO_JTAG_TDI (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_PWM_2 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_TDM_BCK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_I2S1_BCK (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_I2S5_BCK (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_DPI_D6 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPI5_A_CSB (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_SRCLKENAI1 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_TDM_MCK (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_I2S1_MCK (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_I2S5_MCK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_DPI_D7 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPI5_A_MI (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_IO_JTAG_TCK (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_SRCLKENAI0 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_TDM_DATA0 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_I2S2_DI (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_I2S5_DO (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_DPI_D8 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPI5_A_CLK (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_IO_JTAG_TDO (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_TDM_DATA1 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_I2S1_DO (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_I2S2_DI2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_DPI_D9 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_IO_JTAG_TMS (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_IDDIG (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_TDM_DATA2 (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCL9 (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_PWM_3 (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_DPI_D10 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SRCLKENAI0 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_DAP_MD32_SWD (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_TDM_DATA3 (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SDA9 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM_1 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_DPI_D11 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_CLKM1 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(41) | 6) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_DISP_PWM (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_DSI_TE (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_LCM_RST (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SCL6 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SCL0 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SCP_SCL1 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_SCL_6306 (MTK_PIN_NO(45) | 4) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SDA6 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SDA0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SCP_SDA1 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_SDA_6306 (MTK_PIN_NO(46) | 4) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI1_A_MI (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_KPCOL2 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_MD_URXD0 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_CONN_UART0_RXD (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B32 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI1_A_CSB (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_KPROW2 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_MD_UTXD0 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_CONN_UART0_TXD (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_DBG_MON_B31 (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI1_A_MO (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_UCTS0 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_TP_URXD2_AO (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_DBG_MON_B30 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI1_A_CLK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_URTS0 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_WIFI_TXD (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_TP_UTXD2_AO (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_DBG_MON_B29 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_URXD0 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_UTXD0 (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_MD_URXD0 (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_MD_URXD1 (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_SSPM_URXD_AO (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_CONN_UART0_RXD (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_UTXD0 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_URXD0 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_MD_UTXD0 (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_MD_UTXD1 (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_WIFI_TXD (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_CONN_UART0_TXD (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SCL3 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SCP_SCL0 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_SCP_SCL1 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCL_6306 (MTK_PIN_NO(55) | 4) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SDA3 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SCP_SDA0 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_SCP_SDA1 (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_SDA_6306 (MTK_PIN_NO(56) | 4) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_KPROW1 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_PWM_1 (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_CLKM1 (MTK_PIN_NO(57) | 4) +#define PINMUX_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 5) +#define PINMUX_GPIO57__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(57) | 6) +#define PINMUX_GPIO57__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_KPROW0 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_DBG_MON_B28 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_KPCOL0 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_DBG_MON_B27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_KPCOL1 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_PWM_2 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_UCTS1 (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_CLKM2 (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_USB_DRVVBUS (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SCL1 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SCP_SCL0 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SCP_SCL1 (MTK_PIN_NO(61) | 3) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SDA1 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SCP_SDA0 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SCP_SDA1 (MTK_PIN_NO(62) | 3) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SPI2_MI (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SCP_SPI2_MI (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_KPCOL2 (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_MRG_DI (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_MD_URXD0 (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_CONN_UART0_RXD (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_B26 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SPI2_CSB (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_KPROW2 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_MD_UTXD0 (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_CONN_UART0_TXD (MTK_PIN_NO(64) | 6) +#define PINMUX_GPIO64__FUNC_DBG_MON_B25 (MTK_PIN_NO(64) | 7) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SPI2_MO (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SCP_SPI2_MO (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_SCP_SDA1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_MRG_DO (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_MD_URXD1 (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_PWM_3 (MTK_PIN_NO(65) | 6) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_SCP_SCL1 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_MRG_CLK (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_MD_UTXD1 (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_WIFI_TXD (MTK_PIN_NO(66) | 6) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_I2S3_LRCK (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_I2S1_LRCK (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_PCM0_SYNC (MTK_PIN_NO(67) | 4) +#define PINMUX_GPIO67__FUNC_I2S5_LRCK (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B10 (MTK_PIN_NO(67) | 7) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_I2S3_DO (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_PCM0_DO (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_I2S5_DO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_DBG_MON_B9 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_I2S3_MCK (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_I2S1_MCK (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_URTS1 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_AGPS_SYNC (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_I2S5_MCK (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_DBG_MON_B8 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_I2S0_DI (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_I2S2_DI (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_KPCOL2 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_PCM0_DI (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_I2S2_DI2 (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_ANT_SEL11 (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_DBG_MON_B7 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_I2S3_BCK (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_I2S1_BCK (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_KPROW2 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_PCM0_CLK (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_I2S5_BCK (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_ANT_SEL12 (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_DBG_MON_B6 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 2) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS18_PA_VM1 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_MIPI5_SCLK (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_MIPI5_SCLK (MTK_PIN_NO(73) | 3) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS17_PA_VM0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_CONN_MIPI5_SDATA (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MIPI5_SDATA (MTK_PIN_NO(74) | 3) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(75) | 3) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS7 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_DBG_MON_B24 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS6 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_DBG_MON_B23 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS8 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DBG_MON_B22 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS9 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B21 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS10 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_DBG_MON_B20 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS11 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_DBG_MON_B19 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS12 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS12 (MTK_PIN_NO(84) | 2) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_BPI_BUS13 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_BPI_BUS13 (MTK_PIN_NO(85) | 2) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_BPI_BUS14 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS14 (MTK_PIN_NO(86) | 2) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_BPI_BUS15 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS15 (MTK_PIN_NO(87) | 2) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_BPI_BUS16 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS16 (MTK_PIN_NO(88) | 2) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_BPI_BUS5 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DBG_MON_B18 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_BPI_BUS4 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_DBG_MON_B17 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_BPI_BUS3 (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_BPI_BUS2 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DBG_MON_B16 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_BPI_BUS1 (MTK_PIN_NO(93) | 1) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_BPI_BUS0 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_DBG_MON_B15 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_MIPI0_SDATA (MTK_PIN_NO(95) | 1) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_MIPI0_SCLK (MTK_PIN_NO(96) | 1) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_MIPI1_SDATA (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_MIPI1_SCLK (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_MIPI2_SCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_DBG_MON_B14 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_MIPI2_SDATA (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_MIPI3_SCLK (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DBG_MON_B12 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_MIPI3_SDATA (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DBG_MON_B11 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_MIPI4_SCLK (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_CONN_MIPI4_SCLK (MTK_PIN_NO(103) | 2) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_MIPI4_SDATA (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_CONN_MIPI4_SDATA (MTK_PIN_NO(104) | 2) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 2) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 2) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 2) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 2) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 2) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SCL4 (MTK_PIN_NO(110) | 1) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_SDA4 (MTK_PIN_NO(111) | 1) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SCL2 (MTK_PIN_NO(112) | 1) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_SDA2 (MTK_PIN_NO(113) | 1) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_CLKM0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SPI3_MI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_DBG_MON_B5 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_CLKM1 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SPI3_CSB (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_DBG_MON_B4 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_CMMCLK0 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_DBG_MON_B3 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_CMMCLK1 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_DBG_MON_B2 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_CLKM2 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_SPI3_MO (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_DBG_MON_B1 (MTK_PIN_NO(118) | 7) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_CLKM3 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_SPI3_CLK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_CMMCLK2 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_CLKM2 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_ANT_SEL12 (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_TP_UCTS2_AO (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_CMMCLK3 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_CLKM3 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_ANT_SEL11 (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_TP_URTS2_AO (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_CMVREF1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_PCM0_SYNC (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_SRCLKENAI1 (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_AGPS_SYNC (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_PWM_1 (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ANT_SEL9 (MTK_PIN_NO(122) | 6) +#define PINMUX_GPIO122__FUNC_TP_UCTS1_AO (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_PCM0_DI (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMVREF2 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_PCM0_CLK (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_MD_INT0 (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_PWM_2 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_TP_URTS1_AO (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMVREF3 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_PCM0_DO (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_VPU_UDI_TMS (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(125) | 6) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMVREF4 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(126) | 6) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_CMVREF0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(127) | 6) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_LVTS_FOUT (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_DBG_MON_A3 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_CONN_DSP_JCK (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_LVTS_SDO (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_DBG_MON_A4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_LVTS_26M (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_A5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_DSP_JDI (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_LVTS_SCK (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_A0 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_CONN_DSP_JMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_LVTS_SDI (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_DBG_MON_A1 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CONN_DSP_JDO (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_LVTS_SCF (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_A2 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_PCM1_CLK (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_SPI5_B_MI (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(134) | 6) +#define PINMUX_GPIO134__FUNC_JTCK_SEL3 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SPI5_B_CSB (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_UDI_TMS (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_CONN_DSP_JMS (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_JTMS_SEL3 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MSDC1_DAT3 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SPI5_B_MO (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(136) | 6) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_MSDC1_DAT0 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_PCM1_DO0 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_SPI5_B_CLK (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_UDI_TDI (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_CONN_DSP_JDI (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_JTDI_SEL3 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_PCM1_DO2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_ANT_SEL11 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_MSDC1_DAT1 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_ANT_SEL12 (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_UDI_TDO (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_CONN_DSP_JDO (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_JTDO_SEL3 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_ADSP_URXD0 (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCL_6306 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_PTA_RXD (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_SSPM_URXD_AO (MTK_PIN_NO(140) | 6) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_ADSP_UTXD0 (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SDA_6306 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_PTA_TXD (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(141) | 6) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(142) | 2) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_DBG_MON_A9 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_AUD_CLK_MISO (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_I2S2_MCK (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_UDI_TCK (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(144) | 6) +#define PINMUX_GPIO144__FUNC_DBG_MON_A10 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_I2S2_BCK (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_UDI_TMS (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_A11 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_I2S2_DI2 (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_UDI_TDO (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_A14 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_ANT_SEL0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_PWM_3 (MTK_PIN_NO(147) | 2) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_ANT_SEL1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_SPI0_B_MI (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_SSPM_URXD_AO (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_UCTS2_AO (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 6) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_ANT_SEL2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_SPI0_B_CSB (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_URTS2_AO (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(149) | 6) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_SPI0_B_MO (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_UCTS1 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_UCTS1_AO (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_IDDIG (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_SCL9 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_SPI0_B_CLK (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_URTS1 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_URTS1_AO (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_USB_DRVVBUS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_SDA9 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SPI1_B_MI (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_URXD1_AO (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_SCL8 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_SPI1_B_CSB (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_SRCLKENAI0 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_PWM_0 (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_TP_UTXD1_AO (MTK_PIN_NO(153) | 5) +#define PINMUX_GPIO153__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_SDA8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_ANT_SEL7 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_SPI1_B_MO (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_SRCLKENAI1 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_URXD2_AO (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(154) | 6) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_ANT_SEL8 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_SPI1_B_CLK (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_MD_INT0 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_TP_UTXD2_AO (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_A15 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_CONN_TOP_CLK (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_AUXIF_CLK0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DBG_MON_A16 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_CONN_TOP_DATA (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_AUXIF_ST0 (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_DBG_MON_A17 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_CONN_HRST_B (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_DBG_MON_A18 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_CONN_WB_PTA (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_DBG_MON_A19 (MTK_PIN_NO(159) | 7) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_CONN_BT_CLK (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_AUXIF_CLK1 (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_DBG_MON_A20 (MTK_PIN_NO(160) | 7) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_CONN_BT_DATA (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_AUXIF_ST1 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_DBG_MON_A21 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A22 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_DBG_MON_A23 (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_DBG_MON_A24 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_DBG_MON_A25 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_DBG_MON_A26 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MSDC0_CMD (MTK_PIN_NO(167) | 1) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MSDC0_DAT0 (MTK_PIN_NO(168) | 1) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MSDC0_DAT2 (MTK_PIN_NO(169) | 1) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC0_DAT4 (MTK_PIN_NO(170) | 1) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC0_DAT6 (MTK_PIN_NO(171) | 1) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC0_DAT1 (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC0_DAT5 (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC0_DAT7 (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC0_DSL (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_ANT_SEL9 (MTK_PIN_NO(175) | 2) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_MSDC0_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_ANT_SEL10 (MTK_PIN_NO(176) | 2) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_MSDC0_DAT3 (MTK_PIN_NO(177) | 1) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_MSDC0_RSTB (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SRCLKENA0 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_SRCLKENA1 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_WATCHDOG (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(184) | 2) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(186) | 2) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_RTC32K_CK (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_I2S1_MCK (MTK_PIN_NO(189) | 3) +#define PINMUX_GPIO189__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(189) | 6) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_I2S1_BCK (MTK_PIN_NO(190) | 3) +#define PINMUX_GPIO190__FUNC_DBG_MON_A6 (MTK_PIN_NO(190) | 7) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_I2S1_LRCK (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_DBG_MON_A7 (MTK_PIN_NO(191) | 7) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_I2S1_DO (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(192) | 6) +#define PINMUX_GPIO192__FUNC_DBG_MON_A8 (MTK_PIN_NO(192) | 7) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_VOW_DAT_MISO (MTK_PIN_NO(193) | 2) +#define PINMUX_GPIO193__FUNC_I2S2_LRCK (MTK_PIN_NO(193) | 3) +#define PINMUX_GPIO193__FUNC_UDI_TDI (MTK_PIN_NO(193) | 5) +#define PINMUX_GPIO193__FUNC_DBG_MON_A12 (MTK_PIN_NO(193) | 7) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_VOW_CLK_MISO (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_I2S2_DI (MTK_PIN_NO(194) | 3) +#define PINMUX_GPIO194__FUNC_UDI_NTRST (MTK_PIN_NO(194) | 5) +#define PINMUX_GPIO194__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(194) | 6) +#define PINMUX_GPIO194__FUNC_DBG_MON_A13 (MTK_PIN_NO(194) | 7) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_VPU_UDI_TCK (MTK_PIN_NO(195) | 4) +#define PINMUX_GPIO195__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(195) | 5) +#define PINMUX_GPIO195__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(195) | 6) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_CMMCLK4 (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(196) | 3) +#define PINMUX_GPIO196__FUNC_VPU_UDI_TDI (MTK_PIN_NO(196) | 4) +#define PINMUX_GPIO196__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(196) | 5) +#define PINMUX_GPIO196__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(196) | 6) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_VPU_UDI_TDO (MTK_PIN_NO(197) | 4) +#define PINMUX_GPIO197__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(197) | 5) +#define PINMUX_GPIO197__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(197) | 6) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_SCL7 (MTK_PIN_NO(198) | 1) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_SDA7 (MTK_PIN_NO(199) | 1) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_URXD1 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_ADSP_URXD0 (MTK_PIN_NO(200) | 2) +#define PINMUX_GPIO200__FUNC_TP_URXD1_AO (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_SSPM_URXD_AO (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_TP_URXD2_AO (MTK_PIN_NO(200) | 5) +#define PINMUX_GPIO200__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(200) | 6) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_UTXD1 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_ADSP_UTXD0 (MTK_PIN_NO(201) | 2) +#define PINMUX_GPIO201__FUNC_TP_UTXD1_AO (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_TP_UTXD2_AO (MTK_PIN_NO(201) | 5) +#define PINMUX_GPIO201__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(201) | 6) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_PWM_3 (MTK_PIN_NO(202) | 1) +#define PINMUX_GPIO202__FUNC_CLKM3 (MTK_PIN_NO(202) | 2) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) + +#endif /* __MT6779-PINFUNC_H */ -- 1.7.9.5 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org 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Walleij , Rob Herring , Matthias Brugger , "Michael Turquette" , Stephen Boyd , "Sean Wang" Subject: [PATCH v6 2/7] pinctrl: mediatek: update pinmux definitions for mt6779 Date: Thu, 18 Jun 2020 19:33:33 +0800 Message-ID: <1592480018-3340-3-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 28BF5888AD7FFF42060F79C9FA90991FFD4F7B771B1152B8920DEC76B1682A922000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200618_044412_787123_F4145661 X-CRM114-Status: UNSURE ( 9.25 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , wsd_upstream@mediatek.com, Andy Teng , Mars Cheng , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, mtk01761 , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add devicetree bindings for Mediatek mt6779 SoC Pin Controller. Acked-by: Sean Wang Signed-off-by: Hanks Chen Signed-off-by: Mars Cheng Signed-off-by: Andy Teng --- include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++++++++++++++++++++++++++ 1 file changed, 1242 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6779-pinfunc.h b/include/dt-bindings/pinctrl/mt6779-pinfunc.h new file mode 100644 index 0000000..87fdc43 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6779-pinfunc.h @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __MT6779_PINFUNC_H +#define __MT6779_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_MI (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_LRCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_PCM1_SYNC (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCL_6306 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_PTA_RXD (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_DO (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_PCM1_DO0 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SDA_6306 (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_PTA_TXD (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_BCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_TDM_BCK_2ND (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_PCM1_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_CLK (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_MCK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TDM_MCK_2ND (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_MI (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_PCM1_DO1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_SCL8 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_PCM1_DO2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_SDA8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_PCM1_DI (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_SCL9 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_CLK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_SRCLKENAI1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_SDA9 (MTK_PIN_NO(7) | 7) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_PWM_0 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SRCLKENAI0 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_URXD1 (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_I2S0_MCK (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IDDIG (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_PWM_3 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_MD_INT0 (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_SRCLKENAI1 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_UTXD1 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_I2S0_BCK (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_USB_DRVVBUS (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MSDC1_CLK_A (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_TP_URXD1_AO (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S1_LRCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_UCTS0 (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_DMIC1_CLK (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_KPCOL2 (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_SCL8 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MSDC1_CMD_A (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_TP_UTXD1_AO (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S1_DO (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_URTS0 (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_DMIC1_DAT (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_KPROW2 (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_SDA8 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_MSDC1_DAT3_A (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_TP_URXD2_AO (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S1_MCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_DMIC_CLK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ANT_SEL9 (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_SCL9 (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MSDC1_DAT0_A (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_TP_UTXD2_AO (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S1_BCK (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_DMIC_DAT (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_SDA9 (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MSDC1_DAT2_A (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_PWM_3 (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_INT0 (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_PTA_RXD (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MSDC1_DAT1_A (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_PTA_TXD (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_MFG_EJTAG_TRSTN (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_PWM_2 (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SPI0_A_MI (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_SCP_SPI0_MI (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_MFG_EJTAG_TDO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_DPI_HSYNC (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_DFD_TDO (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_JTDO_SEL1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SPI0_A_MO (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SCP_SPI0_MO (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_MFG_EJTAG_TDI (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_DPI_VSYNC (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_DFD_TDI (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_JTDI_SEL1 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SPI0_A_CSB (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SCP_SPI0_CS (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_MFG_EJTAG_TMS (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_DPI_DE (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_DFD_TMS (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_JTMS_SEL1 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SPI0_A_CLK (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SCP_SPI0_CK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_MFG_EJTAG_TCK (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_DPI_CK (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_DFD_TCK_XI (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_JTCK_SEL1 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_PWM_0 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CMFLASH0 (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CMVREF2 (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_CLKM0 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_ANT_SEL9 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A27 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_PWM_1 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_CMFLASH1 (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_CMVREF3 (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_CLKM1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL10 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A28 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_PWM_2 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_CMFLASH2 (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_CMVREF0 (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_CLKM2 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL11 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A29 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_PWM_0 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_CMFLASH3 (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_CMVREF1 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_CLKM3 (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_ANT_SEL12 (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DBG_MON_A30 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_UCTS0 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SCL8 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_CMVREF4 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_I2S0_LRCK (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A31 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_URTS0 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SDA8 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_I2S0_DI (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_AGPS_SYNC (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A32 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_AP_GOOD (MTK_PIN_NO(27) | 1) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_SCL5 (MTK_PIN_NO(28) | 1) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_SDA5 (MTK_PIN_NO(29) | 1) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_I2S1_MCK (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_I2S3_MCK (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_I2S2_MCK (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DPI_D0 (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_SPI4_MI (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(30) | 6) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2S1_BCK (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_I2S3_BCK (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_I2S2_BCK (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DPI_D1 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_SPI4_CSB (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_CONN_MCU_TDO (MTK_PIN_NO(31) | 6) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2S1_LRCK (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I2S3_LRCK (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I2S2_LRCK (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DPI_D2 (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SPI4_MO (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 6) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_I2S2_DI (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_I2S0_DI (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_I2S5_DO (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DPI_D3 (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_SPI4_CLK (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_CONN_MCU_TMS (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I2S1_DO (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I2S3_DO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DPI_D4 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_AGPS_SYNC (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_CONN_MCU_TCK (MTK_PIN_NO(34) | 6) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_TDM_LRCK (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_I2S1_LRCK (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_I2S5_LRCK (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DPI_D5 (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_SPI5_A_MO (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_IO_JTAG_TDI (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_PWM_2 (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_TDM_BCK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_I2S1_BCK (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_I2S5_BCK (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_DPI_D6 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPI5_A_CSB (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_SRCLKENAI1 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_TDM_MCK (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_I2S1_MCK (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_I2S5_MCK (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_DPI_D7 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPI5_A_MI (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_IO_JTAG_TCK (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_SRCLKENAI0 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_TDM_DATA0 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_I2S2_DI (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_I2S5_DO (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_DPI_D8 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPI5_A_CLK (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_IO_JTAG_TDO (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_TDM_DATA1 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_I2S1_DO (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_I2S2_DI2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_DPI_D9 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_IO_JTAG_TMS (MTK_PIN_NO(39) | 6) +#define PINMUX_GPIO39__FUNC_IDDIG (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_TDM_DATA2 (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCL9 (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_PWM_3 (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_DPI_D10 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SRCLKENAI0 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_DAP_MD32_SWD (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_TDM_DATA3 (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SDA9 (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM_1 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_DPI_D11 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_CLKM1 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(41) | 6) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_DISP_PWM (MTK_PIN_NO(42) | 1) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_DSI_TE (MTK_PIN_NO(43) | 1) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_LCM_RST (MTK_PIN_NO(44) | 1) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SCL6 (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SCL0 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SCP_SCL1 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_SCL_6306 (MTK_PIN_NO(45) | 4) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SDA6 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SDA0 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SCP_SDA1 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_SDA_6306 (MTK_PIN_NO(46) | 4) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI1_A_MI (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_KPCOL2 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_MD_URXD0 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_CONN_UART0_RXD (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B32 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI1_A_CSB (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_KPROW2 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_MD_UTXD0 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_CONN_UART0_TXD (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_DBG_MON_B31 (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI1_A_MO (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_UCTS0 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_PWM_1 (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_TP_URXD2_AO (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_DBG_MON_B30 (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI1_A_CLK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_URTS0 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_WIFI_TXD (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_TP_UTXD2_AO (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_DBG_MON_B29 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 1) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 1) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_URXD0 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_UTXD0 (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_MD_URXD0 (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_MD_URXD1 (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_SSPM_URXD_AO (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_CONN_UART0_RXD (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_UTXD0 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_URXD0 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_MD_UTXD0 (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_MD_UTXD1 (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_WIFI_TXD (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_CONN_UART0_TXD (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SCL3 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SCP_SCL0 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_SCP_SCL1 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCL_6306 (MTK_PIN_NO(55) | 4) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SDA3 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SCP_SDA0 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_SCP_SDA1 (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_SDA_6306 (MTK_PIN_NO(56) | 4) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_KPROW1 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_PWM_1 (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(57) | 3) +#define PINMUX_GPIO57__FUNC_CLKM1 (MTK_PIN_NO(57) | 4) +#define PINMUX_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 5) +#define PINMUX_GPIO57__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(57) | 6) +#define PINMUX_GPIO57__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_KPROW0 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_DBG_MON_B28 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_KPCOL0 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_DBG_MON_B27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_KPCOL1 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_PWM_2 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_UCTS1 (MTK_PIN_NO(60) | 3) +#define PINMUX_GPIO60__FUNC_CLKM2 (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_USB_DRVVBUS (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SCL1 (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SCP_SCL0 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SCP_SCL1 (MTK_PIN_NO(61) | 3) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SDA1 (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SCP_SDA0 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SCP_SDA1 (MTK_PIN_NO(62) | 3) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SPI2_MI (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SCP_SPI2_MI (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_KPCOL2 (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_MRG_DI (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_MD_URXD0 (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_CONN_UART0_RXD (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_B26 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SPI2_CSB (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SCP_SPI2_CS (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_KPROW2 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_MD_UTXD0 (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_CONN_UART0_TXD (MTK_PIN_NO(64) | 6) +#define PINMUX_GPIO64__FUNC_DBG_MON_B25 (MTK_PIN_NO(64) | 7) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SPI2_MO (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SCP_SPI2_MO (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_SCP_SDA1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_MRG_DO (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_MD_URXD1 (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_PWM_3 (MTK_PIN_NO(65) | 6) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_SCP_SCL1 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_MRG_CLK (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_MD_UTXD1 (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_WIFI_TXD (MTK_PIN_NO(66) | 6) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_I2S3_LRCK (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_I2S1_LRCK (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_PCM0_SYNC (MTK_PIN_NO(67) | 4) +#define PINMUX_GPIO67__FUNC_I2S5_LRCK (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_ANT_SEL9 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B10 (MTK_PIN_NO(67) | 7) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_I2S3_DO (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_PCM0_DO (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_I2S5_DO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_ANT_SEL10 (MTK_PIN_NO(68) | 6) +#define PINMUX_GPIO68__FUNC_DBG_MON_B9 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_I2S3_MCK (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_I2S1_MCK (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_URTS1 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_AGPS_SYNC (MTK_PIN_NO(69) | 4) +#define PINMUX_GPIO69__FUNC_I2S5_MCK (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 6) +#define PINMUX_GPIO69__FUNC_DBG_MON_B8 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_I2S0_DI (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_I2S2_DI (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_KPCOL2 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_PCM0_DI (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_I2S2_DI2 (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_ANT_SEL11 (MTK_PIN_NO(70) | 6) +#define PINMUX_GPIO70__FUNC_DBG_MON_B7 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_I2S3_BCK (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_I2S1_BCK (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_KPROW2 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_PCM0_CLK (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_I2S5_BCK (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_ANT_SEL12 (MTK_PIN_NO(71) | 6) +#define PINMUX_GPIO71__FUNC_DBG_MON_B6 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS19_OLAT0 (MTK_PIN_NO(72) | 2) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS18_PA_VM1 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_MIPI5_SCLK (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_MIPI5_SCLK (MTK_PIN_NO(73) | 3) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS17_PA_VM0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_CONN_MIPI5_SDATA (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MIPI5_SDATA (MTK_PIN_NO(74) | 3) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS20_OLAT1 (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(75) | 3) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS7 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_DBG_MON_B24 (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS6 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_DBG_MON_B23 (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS8 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DBG_MON_B22 (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS9 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B21 (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS10 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_DBG_MON_B20 (MTK_PIN_NO(82) | 7) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS11 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_DBG_MON_B19 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS12 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS12 (MTK_PIN_NO(84) | 2) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_BPI_BUS13 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_BPI_BUS13 (MTK_PIN_NO(85) | 2) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_BPI_BUS14 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_BPI_BUS14 (MTK_PIN_NO(86) | 2) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_BPI_BUS15 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_BPI_BUS15 (MTK_PIN_NO(87) | 2) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_BPI_BUS16 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_BPI_BUS16 (MTK_PIN_NO(88) | 2) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_BPI_BUS5 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DBG_MON_B18 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_BPI_BUS4 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_DBG_MON_B17 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_BPI_BUS3 (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_BPI_BUS2 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DBG_MON_B16 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_BPI_BUS1 (MTK_PIN_NO(93) | 1) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_BPI_BUS0 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_DBG_MON_B15 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_MIPI0_SDATA (MTK_PIN_NO(95) | 1) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_MIPI0_SCLK (MTK_PIN_NO(96) | 1) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_MIPI1_SDATA (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_MIPI1_SCLK (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_MIPI2_SCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_DBG_MON_B14 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_MIPI2_SDATA (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_DBG_MON_B13 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_MIPI3_SCLK (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DBG_MON_B12 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_MIPI3_SDATA (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DBG_MON_B11 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_MIPI4_SCLK (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_CONN_MIPI4_SCLK (MTK_PIN_NO(103) | 2) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_MIPI4_SDATA (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_CONN_MIPI4_SDATA (MTK_PIN_NO(104) | 2) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS22_OLAT3 (MTK_PIN_NO(105) | 2) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS21_OLAT2 (MTK_PIN_NO(106) | 2) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS24_ANT1 (MTK_PIN_NO(107) | 2) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS25_ANT2 (MTK_PIN_NO(108) | 2) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS23_ANT0 (MTK_PIN_NO(109) | 2) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SCL4 (MTK_PIN_NO(110) | 1) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_SDA4 (MTK_PIN_NO(111) | 1) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SCL2 (MTK_PIN_NO(112) | 1) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_SDA2 (MTK_PIN_NO(113) | 1) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_CLKM0 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SPI3_MI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_DBG_MON_B5 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_CLKM1 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SPI3_CSB (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_DBG_MON_B4 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_CMMCLK0 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_DBG_MON_B3 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_CMMCLK1 (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_DBG_MON_B2 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_CLKM2 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_SPI3_MO (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_DBG_MON_B1 (MTK_PIN_NO(118) | 7) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_CLKM3 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_SPI3_CLK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DBG_MON_B0 (MTK_PIN_NO(119) | 7) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_CMMCLK2 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_CLKM2 (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_ANT_SEL12 (MTK_PIN_NO(120) | 6) +#define PINMUX_GPIO120__FUNC_TP_UCTS2_AO (MTK_PIN_NO(120) | 7) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_CMMCLK3 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_CLKM3 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_ANT_SEL11 (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_TP_URTS2_AO (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_CMVREF1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_PCM0_SYNC (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_SRCLKENAI1 (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_AGPS_SYNC (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_PWM_1 (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ANT_SEL9 (MTK_PIN_NO(122) | 6) +#define PINMUX_GPIO122__FUNC_TP_UCTS1_AO (MTK_PIN_NO(122) | 7) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_PCM0_DI (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 3) +#define PINMUX_GPIO123__FUNC_VPU_UDI_NTRST (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMVREF2 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_PCM0_CLK (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_MD_INT0 (MTK_PIN_NO(124) | 3) +#define PINMUX_GPIO124__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(124) | 4) +#define PINMUX_GPIO124__FUNC_PWM_2 (MTK_PIN_NO(124) | 5) +#define PINMUX_GPIO124__FUNC_ANT_SEL10 (MTK_PIN_NO(124) | 6) +#define PINMUX_GPIO124__FUNC_TP_URTS1_AO (MTK_PIN_NO(124) | 7) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMVREF3 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_PCM0_DO (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_VPU_UDI_TMS (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(125) | 6) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMVREF4 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(126) | 6) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_CMVREF0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(127) | 6) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_LVTS_FOUT (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_DBG_MON_A3 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_CONN_DSP_JCK (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_LVTS_SDO (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_DBG_MON_A4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_LVTS_26M (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_A5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_DSP_JDI (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_LVTS_SCK (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_A0 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_CONN_DSP_JMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_LVTS_SDI (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_DBG_MON_A1 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CONN_DSP_JDO (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_LVTS_SCF (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_A2 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_PCM1_CLK (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_SPI5_B_MI (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_UDI_TCK (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(134) | 6) +#define PINMUX_GPIO134__FUNC_JTCK_SEL3 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MSDC1_CMD (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SPI5_B_CSB (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_UDI_TMS (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_CONN_DSP_JMS (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_JTMS_SEL3 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MSDC1_DAT3 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SPI5_B_MO (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(136) | 6) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_MSDC1_DAT0 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_PCM1_DO0 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_SPI5_B_CLK (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_UDI_TDI (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_CONN_DSP_JDI (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_JTDI_SEL3 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_MSDC1_DAT2 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_PCM1_DO2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_ANT_SEL11 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_UDI_NTRST (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_MSDC1_DAT1 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_ANT_SEL12 (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_UDI_TDO (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_CONN_DSP_JDO (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_JTDO_SEL3 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_ADSP_URXD0 (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCL_6306 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_PTA_RXD (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_SSPM_URXD_AO (MTK_PIN_NO(140) | 6) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_ADSP_UTXD0 (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SDA_6306 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_PTA_TXD (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(141) | 6) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(142) | 2) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_DBG_MON_A9 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_AUD_CLK_MISO (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_I2S2_MCK (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_UDI_TCK (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(144) | 6) +#define PINMUX_GPIO144__FUNC_DBG_MON_A10 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_I2S2_BCK (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_UDI_TMS (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_A11 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_I2S2_DI2 (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_UDI_TDO (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_A14 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_ANT_SEL0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_PWM_3 (MTK_PIN_NO(147) | 2) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_ANT_SEL1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_SPI0_B_MI (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_SSPM_URXD_AO (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_UCTS2_AO (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 6) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_ANT_SEL2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_SPI0_B_CSB (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_URTS2_AO (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(149) | 6) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_ANT_SEL3 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_SPI0_B_MO (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_UCTS1 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_UCTS1_AO (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_IDDIG (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_SCL9 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_ANT_SEL4 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_SPI0_B_CLK (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_URTS1 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_URTS1_AO (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_USB_DRVVBUS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_SDA9 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_ANT_SEL5 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SPI1_B_MI (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_URXD1_AO (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_SCL8 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_ANT_SEL6 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_SPI1_B_CSB (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_SRCLKENAI0 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_PWM_0 (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_TP_UTXD1_AO (MTK_PIN_NO(153) | 5) +#define PINMUX_GPIO153__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_SDA8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_ANT_SEL7 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_SPI1_B_MO (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_SRCLKENAI1 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_URXD2_AO (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(154) | 6) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_ANT_SEL8 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_SPI1_B_CLK (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_MD_INT0 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_TP_UTXD2_AO (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_A15 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_CONN_TOP_CLK (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_AUXIF_CLK0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DBG_MON_A16 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_CONN_TOP_DATA (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_AUXIF_ST0 (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_DBG_MON_A17 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_CONN_HRST_B (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_DBG_MON_A18 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_CONN_WB_PTA (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_DBG_MON_A19 (MTK_PIN_NO(159) | 7) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_CONN_BT_CLK (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_AUXIF_CLK1 (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_DBG_MON_A20 (MTK_PIN_NO(160) | 7) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_CONN_BT_DATA (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_AUXIF_ST1 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_DBG_MON_A21 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A22 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_DBG_MON_A23 (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_DBG_MON_A24 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_DBG_MON_A25 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_DBG_MON_A26 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MSDC0_CMD (MTK_PIN_NO(167) | 1) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MSDC0_DAT0 (MTK_PIN_NO(168) | 1) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MSDC0_DAT2 (MTK_PIN_NO(169) | 1) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MSDC0_DAT4 (MTK_PIN_NO(170) | 1) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MSDC0_DAT6 (MTK_PIN_NO(171) | 1) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MSDC0_DAT1 (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_MSDC0_DAT5 (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_MSDC0_DAT7 (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_MSDC0_DSL (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_ANT_SEL9 (MTK_PIN_NO(175) | 2) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_MSDC0_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_ANT_SEL10 (MTK_PIN_NO(176) | 2) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_MSDC0_DAT3 (MTK_PIN_NO(177) | 1) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_MSDC0_RSTB (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SRCLKENA0 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_SRCLKENA1 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_WATCHDOG (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(184) | 2) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(186) | 2) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_RTC32K_CK (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_I2S1_MCK (MTK_PIN_NO(189) | 3) +#define PINMUX_GPIO189__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(189) | 6) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_I2S1_BCK (MTK_PIN_NO(190) | 3) +#define PINMUX_GPIO190__FUNC_DBG_MON_A6 (MTK_PIN_NO(190) | 7) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_I2S1_LRCK (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_DBG_MON_A7 (MTK_PIN_NO(191) | 7) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_I2S1_DO (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(192) | 6) +#define PINMUX_GPIO192__FUNC_DBG_MON_A8 (MTK_PIN_NO(192) | 7) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_VOW_DAT_MISO (MTK_PIN_NO(193) | 2) +#define PINMUX_GPIO193__FUNC_I2S2_LRCK (MTK_PIN_NO(193) | 3) +#define PINMUX_GPIO193__FUNC_UDI_TDI (MTK_PIN_NO(193) | 5) +#define PINMUX_GPIO193__FUNC_DBG_MON_A12 (MTK_PIN_NO(193) | 7) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_VOW_CLK_MISO (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_I2S2_DI (MTK_PIN_NO(194) | 3) +#define PINMUX_GPIO194__FUNC_UDI_NTRST (MTK_PIN_NO(194) | 5) +#define PINMUX_GPIO194__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(194) | 6) +#define PINMUX_GPIO194__FUNC_DBG_MON_A13 (MTK_PIN_NO(194) | 7) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_VPU_UDI_TCK (MTK_PIN_NO(195) | 4) +#define PINMUX_GPIO195__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(195) | 5) +#define PINMUX_GPIO195__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(195) | 6) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_CMMCLK4 (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(196) | 3) +#define PINMUX_GPIO196__FUNC_VPU_UDI_TDI (MTK_PIN_NO(196) | 4) +#define PINMUX_GPIO196__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(196) | 5) +#define PINMUX_GPIO196__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(196) | 6) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_VPU_UDI_TDO (MTK_PIN_NO(197) | 4) +#define PINMUX_GPIO197__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(197) | 5) +#define PINMUX_GPIO197__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(197) | 6) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_SCL7 (MTK_PIN_NO(198) | 1) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_SDA7 (MTK_PIN_NO(199) | 1) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_URXD1 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_ADSP_URXD0 (MTK_PIN_NO(200) | 2) +#define PINMUX_GPIO200__FUNC_TP_URXD1_AO (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_SSPM_URXD_AO (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_TP_URXD2_AO (MTK_PIN_NO(200) | 5) +#define PINMUX_GPIO200__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(200) | 6) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_UTXD1 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_ADSP_UTXD0 (MTK_PIN_NO(201) | 2) +#define PINMUX_GPIO201__FUNC_TP_UTXD1_AO (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_TP_UTXD2_AO (MTK_PIN_NO(201) | 5) +#define PINMUX_GPIO201__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(201) | 6) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_PWM_3 (MTK_PIN_NO(202) | 1) +#define PINMUX_GPIO202__FUNC_CLKM3 (MTK_PIN_NO(202) | 2) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) + +#endif /* __MT6779-PINFUNC_H */ -- 1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel