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dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 620126E976; Tue, 23 Jun 2020 07:49:03 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by gabe.freedesktop.org (Postfix) with ESMTP id 45D726E858 for ; Mon, 22 Jun 2020 16:12:56 +0000 (UTC) X-UUID: c557e0dc835144f1b10ce311e1b0fd89-20200623 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=+hGMYQ5BeneB1BgmJmHHunz9V/JO0f6iK6J28OXcnV8=; b=jCcqeqWWx+R7jfddcukPXPBphvdK4ExueFOlsghv0JWpo56cBDxBtaiX+LpTx92qV3xgoSVBWKRvHGIJ2kZiJVNEJa2qIjOPYy3FlOXkazKU66TZjLJpUeyE51uYrqcWha43mdg+l1IOoQkPfgW4rmx1XY3SiXI8SQs7f69Oh8I=; X-UUID: c557e0dc835144f1b10ce311e1b0fd89-20200623 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 202892470; Tue, 23 Jun 2020 00:12:53 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Jun 2020 00:12:48 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Jun 2020 00:12:48 +0800 Message-ID: <1592842372.3619.8.camel@mtkswgap22> Subject: Re: [PATCH v1 03/11] soc: mediatek: cmdq: add write_s function From: Dennis-YC Hsieh To: Matthias Brugger Date: Tue, 23 Jun 2020 00:12:52 +0800 In-Reply-To: <8bdfff5f-9fa8-7a13-79d3-dcb63d587629@gmail.com> References: <1592749115-24158-1-git-send-email-dennis-yc.hsieh@mediatek.com> <1592749115-24158-4-git-send-email-dennis-yc.hsieh@mediatek.com> <1592840183.1307.12.camel@mtkswgap22> <8bdfff5f-9fa8-7a13-79d3-dcb63d587629@gmail.com> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Tue, 23 Jun 2020 07:48:47 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wsd_upstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, Houlong Wei , HS Liao , linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Matthias, On Mon, 2020-06-22 at 17:54 +0200, Matthias Brugger wrote: > > On 22/06/2020 17:36, Dennis-YC Hsieh wrote: > > Hi Matthias, > > > > thanks for your comment. > > > > On Mon, 2020-06-22 at 13:07 +0200, Matthias Brugger wrote: > >> > >> On 21/06/2020 16:18, Dennis YC Hsieh wrote: > >>> add write_s function in cmdq helper functions which > >>> writes value contains in internal register to address > >>> with large dma access support. > >>> > >>> Signed-off-by: Dennis YC Hsieh > >>> --- > >>> drivers/soc/mediatek/mtk-cmdq-helper.c | 19 +++++++++++++++++++ > >>> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + > >>> include/linux/soc/mediatek/mtk-cmdq.h | 19 +++++++++++++++++++ > >>> 3 files changed, 39 insertions(+) > >>> > >>> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c > >>> index bf32e3b2ca6c..817a5a97dbe5 100644 > >>> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c > >>> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c > >>> @@ -18,6 +18,10 @@ struct cmdq_instruction { > >>> union { > >>> u32 value; > >>> u32 mask; > >>> + struct { > >>> + u16 arg_c; > >>> + u16 src_reg; > >>> + }; > >>> }; > >>> union { > >>> u16 offset; > >>> @@ -222,6 +226,21 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, > >>> } > >>> EXPORT_SYMBOL(cmdq_pkt_write_mask); > >>> > >>> +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, > >>> + u16 addr_low, u16 src_reg_idx) > >>> +{ > >> > >> Do I understand correctly that we use CMDQ_ADDR_HIGH(addr) and > >> CMDQ_ADDR_LOW(addr) to calculate in the client high_addr_reg_idx and addr_low > >> respectively? > >> > >> In that case I think a better interface would be to pass the address and do the > >> high/low calculation in the cmdq_pkt_write_s > > > > Not exactly. The high_addr_reg_idx parameter is index of internal > > register (which store address bit[47:16]), not result of > > CMDQ_ADDR_HIGH(addr). > > > > The CMDQ_ADDR_HIGH macro use in patch 02/11 cmdq_pkt_assign() api. This > > api helps assign address bit[47:16] into one of internal register by > > index. And same index could be use in cmdq_pkt_write_s(). The gce > > combine bit[47:16] in internal register and bit[15:0] in addr_low > > parameter to final address. So it is better to keep interface in this > > way. > > > > Got it, but then why don't we call cmdq_pkt_assign() in cmdq_pkt_write_s()? This > way we would get a clean API for what we want to do. > Do we expect other users of cmdq_pkt_assign()? Otherwise we could keep it > private the this file and don't export it. Considering this case: write 2 register 0xaabb00c0 0xaabb00d0. If we call assign inside write_s api it will be: assign aabb to internal reg 0 write reg 0 + 0x00c0 assign aabb to internal reg 0 write reg 0 + 0x00d0 But if we let client decide timing to call assign, it will be like: assign aabb to internal reg 0 write reg 0 + 0x00c0 write reg 0 + 0x00d0 The first way uses 4 command and second one uses only 3 command. Thus it is better to let client call assign explicitly. > > By the way, why do you postfix the _s, I understand that it reflects the large > DMA access but I wonder why you choose '_s'. > The name of this command is "write_s" which is hardware spec. I'm just following it since it is a common language between gce sw/hw designers. Regards, Dennis > Regards, > Matthias > > > > > Regards, > > Dennis > > > >> > >> Regards, > >> Matthias > >> > >>> + struct cmdq_instruction inst = {}; > >>> + > >>> + inst.op = CMDQ_CODE_WRITE_S; > >>> + inst.src_t = CMDQ_REG_TYPE; > >>> + inst.sop = high_addr_reg_idx; > >>> + inst.offset = addr_low; > >>> + inst.src_reg = src_reg_idx; > >>> + > >>> + return cmdq_pkt_append_command(pkt, inst); > >>> +} > >>> +EXPORT_SYMBOL(cmdq_pkt_write_s); > >>> + > >>> int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event) > >>> { > >>> struct cmdq_instruction inst = { {0} }; > >>> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h > >>> index 121c3bb6d3de..ee67dd3b86f5 100644 > >>> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h > >>> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h > >>> @@ -59,6 +59,7 @@ enum cmdq_code { > >>> CMDQ_CODE_JUMP = 0x10, > >>> CMDQ_CODE_WFE = 0x20, > >>> CMDQ_CODE_EOC = 0x40, > >>> + CMDQ_CODE_WRITE_S = 0x90, > >>> CMDQ_CODE_LOGIC = 0xa0, > >>> }; > >>> > >>> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h > >>> index 83340211e1d3..e1c5a7549b4f 100644 > >>> --- a/include/linux/soc/mediatek/mtk-cmdq.h > >>> +++ b/include/linux/soc/mediatek/mtk-cmdq.h > >>> @@ -12,6 +12,8 @@ > >>> #include > >>> > >>> #define CMDQ_NO_TIMEOUT 0xffffffffu > >>> +#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) > >>> +#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) > >>> > >>> struct cmdq_pkt; > >>> > >>> @@ -103,6 +105,23 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, > >>> u16 offset, u32 value, u32 mask); > >>> > >>> /** > >>> + * cmdq_pkt_write_s() - append write_s command to the CMDQ packet > >>> + * @pkt: the CMDQ packet > >>> + * @high_addr_reg_idx: internal register ID which contains high address of pa > >>> + * @addr_low: low address of pa > >>> + * @src_reg_idx: the CMDQ internal register ID which cache source value > >>> + * > >>> + * Return: 0 for success; else the error code is returned > >>> + * > >>> + * Support write value to physical address without subsys. Use CMDQ_ADDR_HIGH() > >>> + * to get high address and call cmdq_pkt_assign() to assign value into internal > >>> + * reg. Also use CMDQ_ADDR_LOW() to get low address for addr_low parameter when > >>> + * call to this function. > >>> + */ > >>> +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, > >>> + u16 addr_low, u16 src_reg_idx); > >>> + > >>> +/** > >>> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet > >>> * @pkt: the CMDQ packet > >>> * @event: the desired event type to "wait and CLEAR" > >>> > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 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<1592842372.3619.8.camel@mtkswgap22> Subject: Re: [PATCH v1 03/11] soc: mediatek: cmdq: add write_s function From: Dennis-YC Hsieh To: Matthias Brugger CC: Philipp Zabel , David Airlie , Daniel Vetter , CK Hu , Bibby Hsieh , Houlong Wei , , , , , , HS Liao Date: Tue, 23 Jun 2020 00:12:52 +0800 In-Reply-To: <8bdfff5f-9fa8-7a13-79d3-dcb63d587629@gmail.com> References: <1592749115-24158-1-git-send-email-dennis-yc.hsieh@mediatek.com> <1592749115-24158-4-git-send-email-dennis-yc.hsieh@mediatek.com> <1592840183.1307.12.camel@mtkswgap22> <8bdfff5f-9fa8-7a13-79d3-dcb63d587629@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGkgTWF0dGhpYXMsDQoNCk9uIE1vbiwgMjAyMC0wNi0yMiBhdCAxNzo1NCArMDIwMCwgTWF0dGhp YXMgQnJ1Z2dlciB3cm90ZToNCj4gDQo+IE9uIDIyLzA2LzIwMjAgMTc6MzYsIERlbm5pcy1ZQyBI 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