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X-UUID: aafbf51206634258a2df94bc1f5ba20b-20200624 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1189343506; Wed, 24 Jun 2020 14:36:47 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 24 Jun 2020 14:36:41 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 24 Jun 2020 14:36:41 +0800 Message-ID: <1592980561.24677.1.camel@mbjsdccf07> Subject: Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 From: chao hao To: Matthias Brugger Date: Wed, 24 Jun 2020 14:36:01 +0800 In-Reply-To: References: <20200617030029.4082-1-chao.hao@mediatek.com> <20200617030029.4082-7-chao.hao@mediatek.com> <9e2c52d6-a887-1977-8877-fbcd30cb4261@gmail.com> <1592564184.5692.6.camel@mbjsdccf07> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Sun, 2020-06-21 at 13:01 +0200, Matthias Brugger wrote: > > On 19/06/2020 12:56, chao hao wrote: > > On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN > >>> to improve performance. > >>> This patch add this register definition. > >> > >> Please be more specific what this register is about. > >> > > OK. thanks. > > We can use "has_wr_len" flag to control whether we need to set the > > register. If the register uses default value, iommu will send command to > > EMI without restriction, when the number of commands become more and > > more, it will drop the EMI performance. So when more than > > ten_commands(default value) don't be handled for EMI, IOMMU will stop > > send command to EMI for keeping EMI's performace by enabling write > > throttling mechanism(bit[5][21]=0) in MMU_WR_LEN_CTRL register. > > > > I will write description above to commit message in next version > > > >>> > >>> Signed-off-by: Chao Hao > >>> --- > >>> drivers/iommu/mtk_iommu.c | 10 ++++++++++ > >>> drivers/iommu/mtk_iommu.h | 2 ++ > >>> 2 files changed, 12 insertions(+) > >>> > >>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > >>> index a687e8db0e51..c706bca6487e 100644 > >>> --- a/drivers/iommu/mtk_iommu.c > >>> +++ b/drivers/iommu/mtk_iommu.c > >>> @@ -46,6 +46,8 @@ > >>> #define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > >>> > >>> #define REG_MMU_DCM_DIS 0x050 > >>> +#define REG_MMU_WR_LEN 0x054 > >>> +#define F_MMU_WR_THROT_DIS_BIT (BIT(5) | BIT(21)) > >>> > >>> #define REG_MMU_CTRL_REG 0x110 > >>> #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) > >>> @@ -581,6 +583,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > >>> writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); > >>> } > >>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > >>> + if (data->plat_data->has_wr_len) { > >>> + /* write command throttling mode */ > >>> + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); > >>> + regval &= ~F_MMU_WR_THROT_DIS_BIT; > >>> + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); > >>> + } > >>> > >>> if (data->plat_data->reset_axi) { > >>> /* The register is called STANDARD_AXI_MODE in this case */ > >>> @@ -737,6 +745,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) > >>> struct mtk_iommu_suspend_reg *reg = &data->reg; > >>> void __iomem *base = data->base; > >>> > >>> + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); > >> > >> Can we read/write the register without any side effect although hardware has not > >> implemented it (!has_wr_len)? > > > > It doesn't have side effect. Becasue all the MTK platform have the > > register for iommu HW. If we need to have requirement for performance, > > we can set it by has_wr_len. > > But I'm Sorry, the name of flag(has_wr_len) is not exact, I will rename > > it in next version, ex: "wr_throt_en" > > > >> > >> > >>> reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); > >>> reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); > >>> reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); > >>> @@ -761,6 +770,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > >>> dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); > >>> return ret; > >>> } > >>> + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); > >>> writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); > >>> writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); > >>> writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); > >>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > >>> index d51ff99c2c71..9971cedd72ea 100644 > >>> --- a/drivers/iommu/mtk_iommu.h > >>> +++ b/drivers/iommu/mtk_iommu.h > >>> @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { > >>> u32 int_main_control; > >>> u32 ivrp_paddr; > >>> u32 vld_pa_rng; > >>> + u32 wr_len; > >>> }; > >>> > >>> enum mtk_iommu_plat { > >>> @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { > >>> bool has_misc_ctrl; > >>> bool has_sub_comm; > >>> bool has_vld_pa_rng; > >>> + bool has_wr_len; > >> > >> Given the fact that we are adding more and more plat_data bool values, I think > >> it would make sense to use a u32 flags register and add the appropriate macro > >> definitions to set and check for a flag present. > > > > Thanks for your advice. > > do you mean like this: > > struct plat_flag { > > > > #define HAS_4GB_MODE BIT(0) > > #define HAS_BCLK BIT(1) > > #define REST_AXI BIT(2) > > ... ... > > > > u32 flag; > > }; > > > > struct mtk_iommu_plat_data { > > ...... > > struct plat_flag flag; > > ...... > > }; > > > > Nearly, I mean something like this: > > #define HAS_4GB_MODE BIT(0) > #define HAS_BCLK BIT(1) > #define REST_AXI BIT(2) > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > > struct mtk_iommu_plat_data { > ... > u32 flags; > ... > } > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK) > ... > Ok, got it, thanks > Regards, > Matthias > > > > >> Regards, > >> Matthias > >> > >>> bool reset_axi; > >>> u32 inv_sel_reg; > >>> unsigned char larbid_remap[8][4]; > >>> > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D59DEC433DF for ; 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Wed, 24 Jun 2020 14:36:41 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 24 Jun 2020 14:36:41 +0800 Message-ID: <1592980561.24677.1.camel@mbjsdccf07> Subject: Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 From: chao hao To: Matthias Brugger Date: Wed, 24 Jun 2020 14:36:01 +0800 In-Reply-To: References: <20200617030029.4082-1-chao.hao@mediatek.com> <20200617030029.4082-7-chao.hao@mediatek.com> <9e2c52d6-a887-1977-8877-fbcd30cb4261@gmail.com> <1592564184.5692.6.camel@mbjsdccf07> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Sun, 2020-06-21 at 13:01 +0200, Matthias Brugger wrote: > > On 19/06/2020 12:56, chao hao wrote: > > On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN > >>> to improve performance. > >>> This patch add this register definition. > >> > >> Please be more specific what this register is about. > >> > > OK. thanks. > > We can use "has_wr_len" flag to control whether we need to set the > > register. If the register uses default value, iommu will send command to > > EMI without restriction, when the number of commands become more and > > more, it will drop the EMI performance. So when more than > > ten_commands(default value) don't be handled for EMI, IOMMU will stop > > send command to EMI for keeping EMI's performace by enabling write > > throttling mechanism(bit[5][21]=0) in MMU_WR_LEN_CTRL register. > > > > I will write description above to commit message in next version > > > >>> > >>> Signed-off-by: Chao Hao > >>> --- > >>> drivers/iommu/mtk_iommu.c | 10 ++++++++++ > >>> drivers/iommu/mtk_iommu.h | 2 ++ > >>> 2 files changed, 12 insertions(+) > >>> > >>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > >>> index a687e8db0e51..c706bca6487e 100644 > >>> --- a/drivers/iommu/mtk_iommu.c > >>> +++ b/drivers/iommu/mtk_iommu.c > >>> @@ -46,6 +46,8 @@ > >>> #define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > >>> > >>> #define REG_MMU_DCM_DIS 0x050 > >>> +#define REG_MMU_WR_LEN 0x054 > >>> +#define F_MMU_WR_THROT_DIS_BIT (BIT(5) | BIT(21)) > >>> > >>> #define REG_MMU_CTRL_REG 0x110 > >>> #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) > >>> @@ -581,6 +583,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > >>> writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); > >>> } > >>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > >>> + if (data->plat_data->has_wr_len) { > >>> + /* write command throttling mode */ > >>> + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); > >>> + regval &= ~F_MMU_WR_THROT_DIS_BIT; > >>> + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); > >>> + } > >>> > >>> if (data->plat_data->reset_axi) { > >>> /* The register is called STANDARD_AXI_MODE in this case */ > >>> @@ -737,6 +745,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) > >>> struct mtk_iommu_suspend_reg *reg = &data->reg; > >>> void __iomem *base = data->base; > >>> > >>> + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); > >> > >> Can we read/write the register without any side effect although hardware has not > >> implemented it (!has_wr_len)? > > > > It doesn't have side effect. Becasue all the MTK platform have the > > register for iommu HW. If we need to have requirement for performance, > > we can set it by has_wr_len. > > But I'm Sorry, the name of flag(has_wr_len) is not exact, I will rename > > it in next version, ex: "wr_throt_en" > > > >> > >> > >>> reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); > >>> reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); > >>> reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); > >>> @@ -761,6 +770,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > >>> dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); > >>> return ret; > >>> } > >>> + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); > >>> writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); > >>> writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); > >>> writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); > >>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > >>> index d51ff99c2c71..9971cedd72ea 100644 > >>> --- a/drivers/iommu/mtk_iommu.h > >>> +++ b/drivers/iommu/mtk_iommu.h > >>> @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { > >>> u32 int_main_control; > >>> u32 ivrp_paddr; > >>> u32 vld_pa_rng; > >>> + u32 wr_len; > >>> }; > >>> > >>> enum mtk_iommu_plat { > >>> @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { > >>> bool has_misc_ctrl; > >>> bool has_sub_comm; > >>> bool has_vld_pa_rng; > >>> + bool has_wr_len; > >> > >> Given the fact that we are adding more and more plat_data bool values, I think > >> it would make sense to use a u32 flags register and add the appropriate macro > >> definitions to set and check for a flag present. > > > > Thanks for your advice. > > do you mean like this: > > struct plat_flag { > > > > #define HAS_4GB_MODE BIT(0) > > #define HAS_BCLK BIT(1) > > #define REST_AXI BIT(2) > > ... ... > > > > u32 flag; > > }; > > > > struct mtk_iommu_plat_data { > > ...... > > struct plat_flag flag; > > ...... > > }; > > > > Nearly, I mean something like this: > > #define HAS_4GB_MODE BIT(0) > #define HAS_BCLK BIT(1) > #define REST_AXI BIT(2) > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > > struct mtk_iommu_plat_data { > ... > u32 flags; > ... > } > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK) > ... > Ok, got it, thanks > Regards, > Matthias > > > > >> Regards, > >> Matthias > >> > >>> bool reset_axi; > >>> u32 inv_sel_reg; > >>> unsigned char larbid_remap[8][4]; > >>> > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FC1DC433DF for ; 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Wed, 24 Jun 2020 06:46:51 +0000 X-UUID: a1bbb95176284ebda69ac4757d3970b2-20200623 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=dyrzMGwsnsiMhIacftJo7XUszB6l2wtiz1xwMW8R/c0=; b=Am65U8lnm61YapKhelbvFNf2q1U1T6Vwon0jPy5pKhqj47mzQWEyR3AsvvbAnKTJrOYw8BfpvHeyIHsZNE2ESjCc8gODTA0UC9fTXF4vqmq4PiEFYF18TSc7wkAVOEv7eFT2KaT5GwKnz3Ko0YSeJyKcXa1Ov03hSSMeRyr2CTE=; X-UUID: a1bbb95176284ebda69ac4757d3970b2-20200623 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1126202237; Tue, 23 Jun 2020 22:46:27 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Jun 2020 23:36:43 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 24 Jun 2020 14:36:41 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 24 Jun 2020 14:36:41 +0800 Message-ID: <1592980561.24677.1.camel@mbjsdccf07> Subject: Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 From: chao hao To: Matthias Brugger Date: Wed, 24 Jun 2020 14:36:01 +0800 In-Reply-To: References: <20200617030029.4082-1-chao.hao@mediatek.com> <20200617030029.4082-7-chao.hao@mediatek.com> <9e2c52d6-a887-1977-8877-fbcd30cb4261@gmail.com> <1592564184.5692.6.camel@mbjsdccf07> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Yong Wu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, 2020-06-21 at 13:01 +0200, Matthias Brugger wrote: > > On 19/06/2020 12:56, chao hao wrote: > > On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN > >>> to improve performance. > >>> This patch add this register definition. > >> > >> Please be more specific what this register is about. > >> > > OK. thanks. > > We can use "has_wr_len" flag to control whether we need to set the > > register. If the register uses default value, iommu will send command to > > EMI without restriction, when the number of commands become more and > > more, it will drop the EMI performance. So when more than > > ten_commands(default value) don't be handled for EMI, IOMMU will stop > > send command to EMI for keeping EMI's performace by enabling write > > throttling mechanism(bit[5][21]=0) in MMU_WR_LEN_CTRL register. > > > > I will write description above to commit message in next version > > > >>> > >>> Signed-off-by: Chao Hao > >>> --- > >>> drivers/iommu/mtk_iommu.c | 10 ++++++++++ > >>> drivers/iommu/mtk_iommu.h | 2 ++ > >>> 2 files changed, 12 insertions(+) > >>> > >>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > >>> index a687e8db0e51..c706bca6487e 100644 > >>> --- a/drivers/iommu/mtk_iommu.c > >>> +++ b/drivers/iommu/mtk_iommu.c > >>> @@ -46,6 +46,8 @@ > >>> #define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > >>> > >>> #define REG_MMU_DCM_DIS 0x050 > >>> +#define REG_MMU_WR_LEN 0x054 > >>> +#define F_MMU_WR_THROT_DIS_BIT (BIT(5) | BIT(21)) > >>> > >>> #define REG_MMU_CTRL_REG 0x110 > >>> #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) > >>> @@ -581,6 +583,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > >>> writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); > >>> } > >>> writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > >>> + if (data->plat_data->has_wr_len) { > >>> + /* write command throttling mode */ > >>> + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); > >>> + regval &= ~F_MMU_WR_THROT_DIS_BIT; > >>> + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); > >>> + } > >>> > >>> if (data->plat_data->reset_axi) { > >>> /* The register is called STANDARD_AXI_MODE in this case */ > >>> @@ -737,6 +745,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) > >>> struct mtk_iommu_suspend_reg *reg = &data->reg; > >>> void __iomem *base = data->base; > >>> > >>> + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); > >> > >> Can we read/write the register without any side effect although hardware has not > >> implemented it (!has_wr_len)? > > > > It doesn't have side effect. Becasue all the MTK platform have the > > register for iommu HW. If we need to have requirement for performance, > > we can set it by has_wr_len. > > But I'm Sorry, the name of flag(has_wr_len) is not exact, I will rename > > it in next version, ex: "wr_throt_en" > > > >> > >> > >>> reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); > >>> reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); > >>> reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); > >>> @@ -761,6 +770,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > >>> dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); > >>> return ret; > >>> } > >>> + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); > >>> writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); > >>> writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); > >>> writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); > >>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > >>> index d51ff99c2c71..9971cedd72ea 100644 > >>> --- a/drivers/iommu/mtk_iommu.h > >>> +++ b/drivers/iommu/mtk_iommu.h > >>> @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { > >>> u32 int_main_control; > >>> u32 ivrp_paddr; > >>> u32 vld_pa_rng; > >>> + u32 wr_len; > >>> }; > >>> > >>> enum mtk_iommu_plat { > >>> @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { > >>> bool has_misc_ctrl; > >>> bool has_sub_comm; > >>> bool has_vld_pa_rng; > >>> + bool has_wr_len; > >> > >> Given the fact that we are adding more and more plat_data bool values, I think > >> it would make sense to use a u32 flags register and add the appropriate macro > >> definitions to set and check for a flag present. > > > > Thanks for your advice. > > do you mean like this: > > struct plat_flag { > > > > #define HAS_4GB_MODE BIT(0) > > #define HAS_BCLK BIT(1) > > #define REST_AXI BIT(2) > > ... ... > > > > u32 flag; > > }; > > > > struct mtk_iommu_plat_data { > > ...... > > struct plat_flag flag; > > ...... > > }; > > > > Nearly, I mean something like this: > > #define HAS_4GB_MODE BIT(0) > #define HAS_BCLK BIT(1) > #define REST_AXI BIT(2) > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > ((((pdata)->flags) & (_x)) == (_x)) > > struct mtk_iommu_plat_data { > ... > u32 flags; > ... > } > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK) > ... > Ok, got it, thanks > Regards, > Matthias > > > > >> Regards, > >> Matthias > >> > >>> bool reset_axi; > >>> u32 inv_sel_reg; > >>> unsigned char larbid_remap[8][4]; > >>> > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 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<1592980561.24677.1.camel@mbjsdccf07> Subject: Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779 From: chao hao To: Matthias Brugger CC: Joerg Roedel , Rob Herring , , , , , , , Yong Wu , FY Yang , Chao Hao Date: Wed, 24 Jun 2020 14:36:01 +0800 In-Reply-To: References: <20200617030029.4082-1-chao.hao@mediatek.com> <20200617030029.4082-7-chao.hao@mediatek.com> <9e2c52d6-a887-1977-8877-fbcd30cb4261@gmail.com> <1592564184.5692.6.camel@mbjsdccf07> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gU3VuLCAyMDIwLTA2LTIxIGF0IDEzOjAxICswMjAwLCBNYXR0aGlhcyBCcnVnZ2VyIHdyb3Rl Og0KPiANCj4gT24gMTkvMDYvMjAyMCAxMjo1NiwgY2hhbyBoYW8gd3JvdGU6DQo+ID4gT24gV2Vk LCAyMDIwLTA2LTE3IGF0IDExOjIyICswMjAwLCBNYXR0aGlhcyBCcnVnZ2VyIHdyb3RlOg0KPiA+ Pg0KPiA+PiBPbiAxNy8wNi8yMDIwIDA1OjAwLCBDaGFvIEhhbyB3cm90ZToNCj4gPj4+IFNvbWUg cGxhdGZvcm1zKGV4OiBtdDY3NzkpIGhhdmUgYSBuZXcgcmVnaXN0ZXIgY2FsbGVkIGJ5IFJFR19N TVVfV1JfTEVODQo+ID4+PiB0byBpbXByb3ZlIHBlcmZvcm1hbmNlLg0KPiA+Pj4gVGhpcyBwYXRj aCBhZGQgdGhpcyByZWdpc3RlciBkZWZpbml0aW9uLg0KPiA+Pg0KPiA+PiBQbGVhc2UgYmUgbW9y ZSBzcGVjaWZpYyB3aGF0IHRoaXMgcmVnaXN0ZXIgaXMgYWJvdXQuDQo+ID4+DQo+ID4gT0suIHRo YW5rcy4NCj4gPiBXZSBjYW4gdXNlICJoYXNfd3JfbGVuIiBmbGFnIHRvIGNvbnRyb2wgd2hldGhl ciB3ZSBuZWVkIHRvIHNldCB0aGUNCj4gPiByZWdpc3Rlci4gSWYgdGhlIHJlZ2lzdGVyIHVzZXMg ZGVmYXVsdCB2YWx1ZSwgaW9tbXUgd2lsbCBzZW5kIGNvbW1hbmQgdG8NCj4gPiBFTUkgd2l0aG91 dCByZXN0cmljdGlvbiwgd2hlbiB0aGUgbnVtYmVyIG9mIGNvbW1hbmRzIGJlY29tZSBtb3JlIGFu ZA0KPiA+IG1vcmUsIGl0IHdpbGwgZHJvcCB0aGUgRU1JIHBlcmZvcm1hbmNlLiBTbyB3aGVuIG1v cmUgdGhhbg0KPiA+IHRlbl9jb21tYW5kcyhkZWZhdWx0IHZhbHVlKSBkb24ndCBiZSBoYW5kbGVk IGZvciBFTUksIElPTU1VIHdpbGwgc3RvcA0KPiA+IHNlbmQgY29tbWFuZCB0byBFTUkgZm9yIGtl ZXBpbmcgRU1JJ3MgcGVyZm9ybWFjZSBieSBlbmFibGluZyB3cml0ZQ0KPiA+IHRocm90dGxpbmcg bWVjaGFuaXNtKGJpdFs1XVsyMV09MCkgaW4gTU1VX1dSX0xFTl9DVFJMIHJlZ2lzdGVyLg0KPiA+ IA0KPiA+IEkgd2lsbCB3cml0ZSBkZXNjcmlwdGlvbiBhYm92ZSB0byBjb21taXQgbWVzc2FnZSBp biBuZXh0IHZlcnNpb24NCj4gPiANCj4gPj4+DQo+ID4+PiBTaWduZWQtb2ZmLWJ5OiBDaGFvIEhh byA8Y2hhby5oYW9AbWVkaWF0ZWsuY29tPg0KPiA+Pj4gLS0tDQo+ID4+PiAgZHJpdmVycy9pb21t dS9tdGtfaW9tbXUuYyB8IDEwICsrKysrKysrKysNCj4gPj4+ICBkcml2ZXJzL2lvbW11L210a19p b21tdS5oIHwgIDIgKysNCj4gPj4+ICAyIGZpbGVzIGNoYW5nZWQsIDEyIGluc2VydGlvbnMoKykN Cj4gPj4+DQo+ID4+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9pb21tdS9tdGtfaW9tbXUuYyBiL2Ry aXZlcnMvaW9tbXUvbXRrX2lvbW11LmMNCj4gPj4+IGluZGV4IGE2ODdlOGRiMGU1MS4uYzcwNmJj YTY0ODdlIDEwMDY0NA0KPiA+Pj4gLS0tIGEvZHJpdmVycy9pb21tdS9tdGtfaW9tbXUuYw0KPiA+ Pj4gKysrIGIvZHJpdmVycy9pb21tdS9tdGtfaW9tbXUuYw0KPiA+Pj4gQEAgLTQ2LDYgKzQ2LDgg QEANCj4gPj4+ICAjZGVmaW5lIEZfTU1VX1NUQU5EQVJEX0FYSV9NT0RFX0JJVAkJKEJJVCgzKSB8 IEJJVCgxOSkpDQo+ID4+PiAgDQo+ID4+PiAgI2RlZmluZSBSRUdfTU1VX0RDTV9ESVMJCQkJMHgw NTANCj4gPj4+ICsjZGVmaW5lIFJFR19NTVVfV1JfTEVOCQkJCTB4MDU0DQo+ID4+PiArI2RlZmlu ZSBGX01NVV9XUl9USFJPVF9ESVNfQklUCQkJKEJJVCg1KSB8ICBCSVQoMjEpKQ0KPiA+Pj4gIA0K PiA+Pj4gICNkZWZpbmUgUkVHX01NVV9DVFJMX1JFRwkJCTB4MTEwDQo+ID4+PiAgI2RlZmluZSBG X01NVV9URl9QUk9UX1RPX1BST0dSQU1fQUREUgkJKDIgPDwgNCkNCj4gPj4+IEBAIC01ODEsNiAr NTgzLDEyIEBAIHN0YXRpYyBpbnQgbXRrX2lvbW11X2h3X2luaXQoY29uc3Qgc3RydWN0IG10a19p b21tdV9kYXRhICpkYXRhKQ0KPiA+Pj4gIAkJd3JpdGVsX3JlbGF4ZWQocmVndmFsLCBkYXRhLT5i YXNlICsgUkVHX01NVV9WTERfUEFfUk5HKTsNCj4gPj4+ICAJfQ0KPiA+Pj4gIAl3cml0ZWxfcmVs YXhlZCgwLCBkYXRhLT5iYXNlICsgUkVHX01NVV9EQ01fRElTKTsNCj4gPj4+ICsJaWYgKGRhdGEt PnBsYXRfZGF0YS0+aGFzX3dyX2xlbikgew0KPiA+Pj4gKwkJLyogd3JpdGUgY29tbWFuZCB0aHJv dHRsaW5nIG1vZGUgKi8NCj4gPj4+ICsJCXJlZ3ZhbCA9IHJlYWRsX3JlbGF4ZWQoZGF0YS0+YmFz ZSArIFJFR19NTVVfV1JfTEVOKTsNCj4gPj4+ICsJCXJlZ3ZhbCAmPSB+Rl9NTVVfV1JfVEhST1Rf RElTX0JJVDsNCj4gPj4+ICsJCXdyaXRlbF9yZWxheGVkKHJlZ3ZhbCwgZGF0YS0+YmFzZSArIFJF R19NTVVfV1JfTEVOKTsNCj4gPj4+ICsJfQ0KPiA+Pj4gIA0KPiA+Pj4gIAlpZiAoZGF0YS0+cGxh dF9kYXRhLT5yZXNldF9heGkpIHsNCj4gPj4+ICAJCS8qIFRoZSByZWdpc3RlciBpcyBjYWxsZWQg U1RBTkRBUkRfQVhJX01PREUgaW4gdGhpcyBjYXNlICovDQo+ID4+PiBAQCAtNzM3LDYgKzc0NSw3 IEBAIHN0YXRpYyBpbnQgX19tYXliZV91bnVzZWQgbXRrX2lvbW11X3N1c3BlbmQoc3RydWN0IGRl dmljZSAqZGV2KQ0KPiA+Pj4gIAlzdHJ1Y3QgbXRrX2lvbW11X3N1c3BlbmRfcmVnICpyZWcgPSAm ZGF0YS0+cmVnOw0KPiA+Pj4gIAl2b2lkIF9faW9tZW0gKmJhc2UgPSBkYXRhLT5iYXNlOw0KPiA+ Pj4gIA0KPiA+Pj4gKwlyZWctPndyX2xlbiA9IHJlYWRsX3JlbGF4ZWQoYmFzZSArIFJFR19NTVVf V1JfTEVOKTsNCj4gPj4NCj4gPj4gQ2FuIHdlIHJlYWQvd3JpdGUgdGhlIHJlZ2lzdGVyIHdpdGhv dXQgYW55IHNpZGUgZWZmZWN0IGFsdGhvdWdoIGhhcmR3YXJlIGhhcyBub3QNCj4gPj4gaW1wbGVt ZW50ZWQgaXQgKCFoYXNfd3JfbGVuKT8NCj4gPiANCj4gPiBJdCBkb2Vzbid0IGhhdmUgc2lkZSBl ZmZlY3QuIEJlY2FzdWUgYWxsIHRoZSBNVEsgcGxhdGZvcm0gaGF2ZSB0aGUNCj4gPiByZWdpc3Rl ciBmb3IgaW9tbXUgSFcuIElmIHdlIG5lZWQgdG8gaGF2ZSByZXF1aXJlbWVudCBmb3IgcGVyZm9y bWFuY2UsDQo+ID4gd2UgY2FuIHNldCBpdCBieSBoYXNfd3JfbGVuLg0KPiA+IEJ1dCBJJ20gU29y cnksIHRoZSBuYW1lIG9mIGZsYWcoaGFzX3dyX2xlbikgaXMgbm90IGV4YWN0LCBJIHdpbGwgcmVu YW1lDQo+ID4gaXQgaW4gbmV4dCB2ZXJzaW9uLCBleDogIndyX3Rocm90X2VuIg0KPiA+IA0KPiA+ Pg0KPiA+Pg0KPiA+Pj4gIAlyZWctPm1pc2NfY3RybCA9IHJlYWRsX3JlbGF4ZWQoYmFzZSArIFJF R19NTVVfTUlTQ19DVFJMKTsNCj4gPj4+ICAJcmVnLT5kY21fZGlzID0gcmVhZGxfcmVsYXhlZChi YXNlICsgUkVHX01NVV9EQ01fRElTKTsNCj4gPj4+ICAJcmVnLT5jdHJsX3JlZyA9IHJlYWRsX3Jl bGF4ZWQoYmFzZSArIFJFR19NTVVfQ1RSTF9SRUcpOw0KPiA+Pj4gQEAgLTc2MSw2ICs3NzAsNyBA QCBzdGF0aWMgaW50IF9fbWF5YmVfdW51c2VkIG10a19pb21tdV9yZXN1bWUoc3RydWN0IGRldmlj ZSAqZGV2KQ0KPiA+Pj4gIAkJZGV2X2VycihkYXRhLT5kZXYsICJGYWlsZWQgdG8gZW5hYmxlIGNs ayglZCkgaW4gcmVzdW1lXG4iLCByZXQpOw0KPiA+Pj4gIAkJcmV0dXJuIHJldDsNCj4gPj4+ICAJ fQ0KPiA+Pj4gKwl3cml0ZWxfcmVsYXhlZChyZWctPndyX2xlbiwgYmFzZSArIFJFR19NTVVfV1Jf TEVOKTsNCj4gPj4+ICAJd3JpdGVsX3JlbGF4ZWQocmVnLT5taXNjX2N0cmwsIGJhc2UgKyBSRUdf TU1VX01JU0NfQ1RSTCk7DQo+ID4+PiAgCXdyaXRlbF9yZWxheGVkKHJlZy0+ZGNtX2RpcywgYmFz ZSArIFJFR19NTVVfRENNX0RJUyk7DQo+ID4+PiAgCXdyaXRlbF9yZWxheGVkKHJlZy0+Y3RybF9y ZWcsIGJhc2UgKyBSRUdfTU1VX0NUUkxfUkVHKTsNCj4gPj4+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2lvbW11L210a19pb21tdS5oIGIvZHJpdmVycy9pb21tdS9tdGtfaW9tbXUuaA0KPiA+Pj4gaW5k ZXggZDUxZmY5OWMyYzcxLi45OTcxY2VkZDcyZWEgMTAwNjQ0DQo+ID4+PiAtLS0gYS9kcml2ZXJz L2lvbW11L210a19pb21tdS5oDQo+ID4+PiArKysgYi9kcml2ZXJzL2lvbW11L210a19pb21tdS5o DQo+ID4+PiBAQCAtMjUsNiArMjUsNyBAQCBzdHJ1Y3QgbXRrX2lvbW11X3N1c3BlbmRfcmVnIHsN Cj4gPj4+ICAJdTMyCQkJCWludF9tYWluX2NvbnRyb2w7DQo+ID4+PiAgCXUzMgkJCQlpdnJwX3Bh ZGRyOw0KPiA+Pj4gIAl1MzIJCQkJdmxkX3BhX3JuZzsNCj4gPj4+ICsJdTMyCQkJCXdyX2xlbjsN Cj4gPj4+ICB9Ow0KPiA+Pj4gIA0KPiA+Pj4gIGVudW0gbXRrX2lvbW11X3BsYXQgew0KPiA+Pj4g QEAgLTQzLDYgKzQ0LDcgQEAgc3RydWN0IG10a19pb21tdV9wbGF0X2RhdGEgew0KPiA+Pj4gIAli b29sCQkgICAgaGFzX21pc2NfY3RybDsNCj4gPj4+ICAJYm9vbAkJICAgIGhhc19zdWJfY29tbTsN Cj4gPj4+ICAJYm9vbCAgICAgICAgICAgICAgICBoYXNfdmxkX3BhX3JuZzsNCj4gPj4+ICsJYm9v bCAgICAgICAgICAgICAgICBoYXNfd3JfbGVuOw0KPiA+Pg0KPiA+PiBHaXZlbiB0aGUgZmFjdCB0 aGF0IHdlIGFyZSBhZGRpbmcgbW9yZSBhbmQgbW9yZSBwbGF0X2RhdGEgYm9vbCB2YWx1ZXMsIEkg dGhpbmsNCj4gPj4gaXQgd291bGQgbWFrZSBzZW5zZSB0byB1c2UgYSB1MzIgZmxhZ3MgcmVnaXN0 ZXIgYW5kIGFkZCB0aGUgYXBwcm9wcmlhdGUgbWFjcm8NCj4gPj4gZGVmaW5pdGlvbnMgdG8gc2V0 IGFuZCBjaGVjayBmb3IgYSBmbGFnIHByZXNlbnQuDQo+ID4gDQo+ID4gVGhhbmtzIGZvciB5b3Vy IGFkdmljZS4NCj4gPiBkbyB5b3UgbWVhbiBsaWtlIHRoaXM6DQo+ID4gc3RydWN0IHBsYXRfZmxh ZyB7DQo+ID4gDQo+ID4gICAgICAgICAjZGVmaW5lICBIQVNfNEdCX01PREUgICBCSVQoMCkNCj4g PiAgICAgICAgICNkZWZpbmUgIEhBU19CQ0xLICAgICAgIEJJVCgxKQ0KPiA+ICAgICAgICAgI2Rl ZmluZSAgUkVTVF9BWEkgICAgICAgQklUKDIpDQo+ID4gICAgICAgICAuLi4gLi4uDQo+ID4gDQo+ ID4gICAgICAgICB1MzIgZmxhZzsNCj4gPiB9Ow0KPiA+IA0KPiA+IHN0cnVjdCBtdGtfaW9tbXVf cGxhdF9kYXRhIHsNCj4gPiAgICAgICAgIC4uLi4uLg0KPiA+ICAgICAgICAgc3RydWN0IHBsYXRf ZmxhZyBmbGFnOw0KPiA+ICAgICAgICAgLi4uLi4uDQo+ID4gfTsNCj4gPiANCj4gDQo+IE5lYXJs eSwgSSBtZWFuIHNvbWV0aGluZyBsaWtlIHRoaXM6DQo+IA0KPiAjZGVmaW5lICBIQVNfNEdCX01P REUgICBCSVQoMCkNCj4gI2RlZmluZSAgSEFTX0JDTEsgICAgICAgQklUKDEpDQo+ICNkZWZpbmUg IFJFU1RfQVhJICAgICAgIEJJVCgyKQ0KPiANCj4gI2RlZmluZSBNVEtfSU9NTVVfSEFTX0ZMQUco cGRhdGEsIF94KQlcDQo+IAkJKCgoKHBkYXRhKS0+ZmxhZ3MpICYgKF94KSkgPT0gKF94KSkNCj4g DQo+IHN0cnVjdCBtdGtfaW9tbXVfcGxhdF9kYXRhIHsNCj4gCS4uLg0KPiAJdTMyIGZsYWdzOw0K PiAJLi4uDQo+IH0NCj4gDQo+IGlmIChNVEtfSU9NTVVfSEFTX0ZMQUcoZGF0YS0+cGxhdF9kYXRh LCBIQVNfQkNMSykNCj4gLi4uDQo+IA0KDQpPaywgZ290IGl0LCB0aGFua3MNCg0KDQo+IFJlZ2Fy ZHMsDQo+IE1hdHRoaWFzDQo+IA0KPiA+IA0KPiA+PiBSZWdhcmRzLA0KPiA+PiBNYXR0aGlhcw0K PiA+Pg0KPiA+Pj4gIAlib29sICAgICAgICAgICAgICAgIHJlc2V0X2F4aTsNCj4gPj4+ICAJdTMy ICAgICAgICAgICAgICAgICBpbnZfc2VsX3JlZzsNCj4gPj4+ICAJdW5zaWduZWQgY2hhciAgICAg ICBsYXJiaWRfcmVtYXBbOF1bNF07DQo+ID4+Pg0KPiA+IA0KDQo=