From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D8F3C433E2 for ; Tue, 30 Jun 2020 10:54:38 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45AAD2073E for ; Tue, 30 Jun 2020 10:54:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="W9mu+44/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45AAD2073E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id D6DA086D6E; Tue, 30 Jun 2020 10:54:37 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oTO-P4-r1zh2; Tue, 30 Jun 2020 10:54:36 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by fraxinus.osuosl.org (Postfix) with ESMTP id 0E949868AF; Tue, 30 Jun 2020 10:54:36 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id CCF27C088F; Tue, 30 Jun 2020 10:54:35 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by lists.linuxfoundation.org (Postfix) with ESMTP id 0A068C016E for ; Tue, 30 Jun 2020 10:54:34 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id F18EB8787F for ; Tue, 30 Jun 2020 10:54:33 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id enGaCYEUDx0K for ; Tue, 30 Jun 2020 10:54:33 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by whitealder.osuosl.org (Postfix) with ESMTP id 9F6F287C0A for ; Tue, 30 Jun 2020 10:54:32 +0000 (UTC) X-UUID: 8652aa4974ec431eb1bd83e81af4e9d5-20200630 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=1frGonLY1z6bSq/H3kT64qvgesRuR+pzmBbHCLpti1k=; b=W9mu+44/QT8bk5uDWHK6tphZBC7tG5n/0s/UHdqvnnuKhI1DUkiq1zr7VrTU5GWDCtxRXEZ5P3t4KKC2zyWsIq60TBWONiIppfF5N/XfBLSIsurpv3akPiUZqApzNdtvxxGtN16GT9BoKim+JBIs4LrJsFcFLUV2QhHakTqB7Gs=; X-UUID: 8652aa4974ec431eb1bd83e81af4e9d5-20200630 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 704726967; Tue, 30 Jun 2020 18:54:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 18:54:17 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Jun 2020 18:54:16 +0800 Message-ID: <1593514398.2581.7.camel@mbjsdccf07> Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register From: chao hao To: Matthias Brugger Date: Tue, 30 Jun 2020 18:53:18 +0800 In-Reply-To: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BAF6CEB1E06926B691EB2968E120FA304DAE48B58E1A3A76D8C81A49D6E53EB22000:8 X-MTK: N Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > > standard AXI protocol), iommu will send urgent read command firstly > > compare with normal read command to improve performance. > > Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > Does this mean that you will send a 'urgent read command' which is not described > in the specifications instead of a normal read command? ok. iommu sends read command to next bus_node normally(we can name it to cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read command is needed to be sent(we can name it to cmd2), iommu will send cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and cmd2 will be handled secondly. But for standard AXI protocol, it will ignore the priority of read command and only be handled in order. So cmd2 is handled by next bus_node after cmd1 is done. > > > F_MMU_IN_ORDER_WR_EN: > > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > > will re-order write command and send more higher priority write command > > instead of sending write command in order. The feature be controlled > > by OUT_ORDER_EN macro definition. > > > > Cc: Matthias Brugger > > Suggested-by: Yong Wu > > Signed-off-by: Chao Hao > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 8f81df6cbe51..67b46b5d83d9 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? ok, you are right. 1'b1: follow standard axi protocol > > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > We only need to read regval in the else branch. ok, I got it. thanks > > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > > /* The register is called STANDARD_AXI_MODE in this case */ > > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > + regval = 0; > > + } else { > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > } > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 7cc39f729263..4b780b651ef4 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -22,6 +22,7 @@ > > #define HAS_BCLK BIT(1) > > #define HAS_VLD_PA_RNG BIT(2) > > #define RESET_AXI BIT(3) > > +#define OUT_ORDER_EN BIT(4) > > Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > write path. > ok, thanks for your advice. > > > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > ((((pdata)->flags) & (_x)) == (_x)) > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B34DC433E0 for ; Tue, 30 Jun 2020 10:55:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 425652073E for ; Tue, 30 Jun 2020 10:55:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="XuNCiecD"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="W9mu+44/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 425652073E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cDKxVmu5DmOCGjs0+y9/tLB6GD7Q9GpwEGPsq+bZWxE=; b=XuNCiecDAXsB/ycTIp9h8ryoJ 1YChKjNzmmaiTPOoRYKt3+k7kVt+b6W09OQV1Naow6aniCInQWI8v05W2RHEDDWccr7eEHMwvc4r1 dDy+xi57Q7Q1F/49uTigtzG4522f/tuQzf8PwtdugWBVt7eN3wuWsHm7aWOIU9XCFhy8lIMEG1tc3 AGbVWUZzbvNjwsJ0hOpW6sET8uZYxB5lHWxjBKRFrocc3FKFSVhvhNLG6GABpGvhH+cFjltBGWsFH nX4K8C1gxONPjf8JMpEGAaI+VklRaKqd519mGdHOnQ5okQ8XRaMd0mA17N52sDhs6EhLVzH9zy3Ms wuJIXztHA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqDuc-0001sA-Ee; Tue, 30 Jun 2020 10:54:50 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqDuZ-0001rc-Em; Tue, 30 Jun 2020 10:54:49 +0000 X-UUID: 7b2a77604d90457ba3cba94629b0d8e7-20200630 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=1frGonLY1z6bSq/H3kT64qvgesRuR+pzmBbHCLpti1k=; b=W9mu+44/QT8bk5uDWHK6tphZBC7tG5n/0s/UHdqvnnuKhI1DUkiq1zr7VrTU5GWDCtxRXEZ5P3t4KKC2zyWsIq60TBWONiIppfF5N/XfBLSIsurpv3akPiUZqApzNdtvxxGtN16GT9BoKim+JBIs4LrJsFcFLUV2QhHakTqB7Gs=; X-UUID: 7b2a77604d90457ba3cba94629b0d8e7-20200630 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 42055014; Tue, 30 Jun 2020 02:54:29 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 03:54:31 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 18:54:17 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Jun 2020 18:54:16 +0800 Message-ID: <1593514398.2581.7.camel@mbjsdccf07> Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register From: chao hao To: Matthias Brugger Date: Tue, 30 Jun 2020 18:53:18 +0800 In-Reply-To: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BAF6CEB1E06926B691EB2968E120FA304DAE48B58E1A3A76D8C81A49D6E53EB22000:8 X-MTK: N X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Yong Wu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > > standard AXI protocol), iommu will send urgent read command firstly > > compare with normal read command to improve performance. > > Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > Does this mean that you will send a 'urgent read command' which is not described > in the specifications instead of a normal read command? ok. iommu sends read command to next bus_node normally(we can name it to cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read command is needed to be sent(we can name it to cmd2), iommu will send cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and cmd2 will be handled secondly. But for standard AXI protocol, it will ignore the priority of read command and only be handled in order. So cmd2 is handled by next bus_node after cmd1 is done. > > > F_MMU_IN_ORDER_WR_EN: > > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > > will re-order write command and send more higher priority write command > > instead of sending write command in order. The feature be controlled > > by OUT_ORDER_EN macro definition. > > > > Cc: Matthias Brugger > > Suggested-by: Yong Wu > > Signed-off-by: Chao Hao > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 8f81df6cbe51..67b46b5d83d9 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? ok, you are right. 1'b1: follow standard axi protocol > > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > We only need to read regval in the else branch. ok, I got it. thanks > > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > > /* The register is called STANDARD_AXI_MODE in this case */ > > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > + regval = 0; > > + } else { > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > } > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 7cc39f729263..4b780b651ef4 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -22,6 +22,7 @@ > > #define HAS_BCLK BIT(1) > > #define HAS_VLD_PA_RNG BIT(2) > > #define RESET_AXI BIT(3) > > +#define OUT_ORDER_EN BIT(4) > > Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > write path. > ok, thanks for your advice. > > > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > ((((pdata)->flags) & (_x)) == (_x)) > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80925C433DF for ; Tue, 30 Jun 2020 10:56:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C41C2067D for ; Tue, 30 Jun 2020 10:56:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="0GZcBZDB"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="W9mu+44/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C41C2067D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KoDJgYaj7BD/d+1Rc2g3Q8n4LKszElDk2smm0Z8X3+c=; b=0GZcBZDBKlPDEEhPZDdUEt9n6 69LTRVxH9rjj8Da5Pv5diULXXnWN7zNGFPcE9805SWFLo1tSzRXmEkRucYQO2QCHpXRNSav1pps6f DpwkoBpY7shwTtslNlvXVfGTTDkQgwArnpOBve+Jupq8h4zYwW0hIF438mv2rshXaqlV16RN4O3wv RIn0H9n9ZXMG7trYCuAHyOk7qaLtj9lrO4MzgNfngJnphB2qXBPYrLIY2V7FUxHUeCL/GLnFhFvBa HDfSVmLg4lYc0nT5NUcjAK1KsHmfGehkIc4SVGqwVPQHr0joqTDM68HdH6MjF14F+lZeS1agZQL+I /74GgqyIQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqDud-0001sH-60; Tue, 30 Jun 2020 10:54:51 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqDuZ-0001rc-Em; Tue, 30 Jun 2020 10:54:49 +0000 X-UUID: 7b2a77604d90457ba3cba94629b0d8e7-20200630 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=1frGonLY1z6bSq/H3kT64qvgesRuR+pzmBbHCLpti1k=; b=W9mu+44/QT8bk5uDWHK6tphZBC7tG5n/0s/UHdqvnnuKhI1DUkiq1zr7VrTU5GWDCtxRXEZ5P3t4KKC2zyWsIq60TBWONiIppfF5N/XfBLSIsurpv3akPiUZqApzNdtvxxGtN16GT9BoKim+JBIs4LrJsFcFLUV2QhHakTqB7Gs=; X-UUID: 7b2a77604d90457ba3cba94629b0d8e7-20200630 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 42055014; Tue, 30 Jun 2020 02:54:29 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 03:54:31 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 18:54:17 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Jun 2020 18:54:16 +0800 Message-ID: <1593514398.2581.7.camel@mbjsdccf07> Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register From: chao hao To: Matthias Brugger Date: Tue, 30 Jun 2020 18:53:18 +0800 In-Reply-To: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BAF6CEB1E06926B691EB2968E120FA304DAE48B58E1A3A76D8C81A49D6E53EB22000:8 X-MTK: N X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , Chao Hao , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Yong Wu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow > > standard AXI protocol), iommu will send urgent read command firstly > > compare with normal read command to improve performance. > > Can you please help me to understand the phrase. Sorry I'm not a AXI specialist. > Does this mean that you will send a 'urgent read command' which is not described > in the specifications instead of a normal read command? ok. iommu sends read command to next bus_node normally(we can name it to cmd1), when cmd1 isn't handled by next bus_node, iommu has a urgent read command is needed to be sent(we can name it to cmd2), iommu will send cmd2 and replace cmd1. So cmd2 is handled by next bus_node firstly and cmd2 will be handled secondly. But for standard AXI protocol, it will ignore the priority of read command and only be handled in order. So cmd2 is handled by next bus_node after cmd1 is done. > > > F_MMU_IN_ORDER_WR_EN: > > If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu > > will re-order write command and send more higher priority write command > > instead of sending write command in order. The feature be controlled > > by OUT_ORDER_EN macro definition. > > > > Cc: Matthias Brugger > > Suggested-by: Yong Wu > > Signed-off-by: Chao Hao > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++++++++- > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 8f81df6cbe51..67b46b5d83d9 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > Wouldn't it make more sense to name it F_MMU_STANDARD_AXI_MODE_EN? ok, you are right. 1'b1: follow standard axi protocol > > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > } > > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > We only need to read regval in the else branch. ok, I got it. thanks > > > if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > > /* The register is called STANDARD_AXI_MODE in this case */ > > - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > + regval = 0; > > + } else { > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > } > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 7cc39f729263..4b780b651ef4 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -22,6 +22,7 @@ > > #define HAS_BCLK BIT(1) > > #define HAS_VLD_PA_RNG BIT(2) > > #define RESET_AXI BIT(3) > > +#define OUT_ORDER_EN BIT(4) > > Maybe something like OUT_ORDER_WR_EN, to make clear that it's about the the > write path. > ok, thanks for your advice. > > > > #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > ((((pdata)->flags) & (_x)) == (_x)) > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB8DFC433DF for ; Tue, 30 Jun 2020 10:54:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ACA7E20780 for ; Tue, 30 Jun 2020 10:54:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="W9mu+44/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732659AbgF3Kyd (ORCPT ); Tue, 30 Jun 2020 06:54:33 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:10632 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729377AbgF3Kyd (ORCPT ); Tue, 30 Jun 2020 06:54:33 -0400 X-UUID: 8652aa4974ec431eb1bd83e81af4e9d5-20200630 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=1frGonLY1z6bSq/H3kT64qvgesRuR+pzmBbHCLpti1k=; b=W9mu+44/QT8bk5uDWHK6tphZBC7tG5n/0s/UHdqvnnuKhI1DUkiq1zr7VrTU5GWDCtxRXEZ5P3t4KKC2zyWsIq60TBWONiIppfF5N/XfBLSIsurpv3akPiUZqApzNdtvxxGtN16GT9BoKim+JBIs4LrJsFcFLUV2QhHakTqB7Gs=; X-UUID: 8652aa4974ec431eb1bd83e81af4e9d5-20200630 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 704726967; Tue, 30 Jun 2020 18:54:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Jun 2020 18:54:17 +0800 Received: from [10.15.20.246] (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Jun 2020 18:54:16 +0800 Message-ID: <1593514398.2581.7.camel@mbjsdccf07> Subject: Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register From: chao hao To: Matthias Brugger CC: Joerg Roedel , Rob Herring , "Yong Wu" , Evan Green , , , , , , , FY Yang , Chao Hao Date: Tue, 30 Jun 2020 18:53:18 +0800 In-Reply-To: <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> <20200629071310.1557-5-chao.hao@mediatek.com> <0e9ceba8-0cc4-44a1-148c-1c9a6b3844ce@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: BAF6CEB1E06926B691EB2968E120FA304DAE48B58E1A3A76D8C81A49D6E53EB22000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gTW9uLCAyMDIwLTA2LTI5IGF0IDExOjI4ICswMjAwLCBNYXR0aGlhcyBCcnVnZ2VyIHdyb3Rl Og0KPiANCj4gT24gMjkvMDYvMjAyMCAwOToxMywgQ2hhbyBIYW8gd3JvdGU6DQo+ID4gQWRkIEZf TU1VX0lOX09SREVSX1dSX0VOIGFuZCBGX01NVV9TVEFOREFSRF9BWElfTU9ERV9CSVQgZGVmaW5p dGlvbg0KPiA+IGluIE1JU0NfQ1RSTCByZWdpc3Rlci4NCj4gPiBGX01NVV9TVEFOREFSRF9BWElf TU9ERV9CSVQ6DQo+ID4gICBJZiB3ZSBzZXQgRl9NTVVfU1RBTkRBUkRfQVhJX01PREVfQklUKGJp dFszXVsxOV0gPSAwLCBub3QgZm9sbG93DQo+ID4gc3RhbmRhcmQgQVhJIHByb3RvY29sKSwgaW9t bXUgd2lsbCBzZW5kIHVyZ2VudCByZWFkIGNvbW1hbmQgZmlyc3RseQ0KPiA+IGNvbXBhcmUgd2l0 aCBub3JtYWwgcmVhZCBjb21tYW5kIHRvIGltcHJvdmUgcGVyZm9ybWFuY2UuDQo+IA0KPiBDYW4g eW91IHBsZWFzZSBoZWxwIG1lIHRvIHVuZGVyc3RhbmQgdGhlIHBocmFzZS4gU29ycnkgSSdtIG5v dCBhIEFYSSBzcGVjaWFsaXN0Lg0KPiBEb2VzIHRoaXMgbWVhbiB0aGF0IHlvdSB3aWxsIHNlbmQg YSAndXJnZW50IHJlYWQgY29tbWFuZCcgd2hpY2ggaXMgbm90IGRlc2NyaWJlZA0KPiBpbiB0aGUg c3BlY2lmaWNhdGlvbnMgaW5zdGVhZCBvZiBhIG5vcm1hbCByZWFkIGNvbW1hbmQ/DQoNCm9rLg0K aW9tbXUgc2VuZHMgcmVhZCBjb21tYW5kIHRvIG5leHQgYnVzX25vZGUgbm9ybWFsbHkod2UgY2Fu IG5hbWUgaXQgdG8NCmNtZDEpLCB3aGVuIGNtZDEgaXNuJ3QgaGFuZGxlZCBieSBuZXh0IGJ1c19u b2RlLCBpb21tdSBoYXMgYSB1cmdlbnQgcmVhZA0KY29tbWFuZCBpcyBuZWVkZWQgdG8gYmUgc2Vu dCh3ZSBjYW4gbmFtZSBpdCB0byBjbWQyKSwgaW9tbXUgd2lsbCBzZW5kDQpjbWQyIGFuZCByZXBs YWNlIGNtZDEuIFNvIGNtZDIgaXMgaGFuZGxlZCBieSBuZXh0IGJ1c19ub2RlIGZpcnN0bHkgYW5k DQpjbWQyIHdpbGwgYmUgaGFuZGxlZCBzZWNvbmRseS4NCkJ1dCBmb3Igc3RhbmRhcmQgQVhJIHBy b3RvY29sLCBpdCB3aWxsIGlnbm9yZSB0aGUgcHJpb3JpdHkgb2YgcmVhZA0KY29tbWFuZCBhbmQg b25seSBiZSBoYW5kbGVkIGluIG9yZGVyLiBTbyBjbWQyIGlzIGhhbmRsZWQgYnkgbmV4dA0KYnVz X25vZGUgYWZ0ZXIgY21kMSBpcyBkb25lLg0KDQo+IA0KPiA+IEZfTU1VX0lOX09SREVSX1dSX0VO Og0KPiA+ICAgSWYgd2Ugc2V0IEZfTU1VX0lOX09SREVSX1dSX0VOKGJpdFsxXVsxN10gPSAwLCBv dXQtb2Ytb3JkZXIgd3JpdGUpLCBpb21tdQ0KPiA+IHdpbGwgcmUtb3JkZXIgd3JpdGUgY29tbWFu ZCBhbmQgc2VuZCBtb3JlIGhpZ2hlciBwcmlvcml0eSB3cml0ZSBjb21tYW5kDQo+ID4gaW5zdGVh ZCBvZiBzZW5kaW5nIHdyaXRlIGNvbW1hbmQgaW4gb3JkZXIuIFRoZSBmZWF0dXJlIGJlIGNvbnRy b2xsZWQNCj4gPiBieSBPVVRfT1JERVJfRU4gbWFjcm8gZGVmaW5pdGlvbi4NCj4gPiANCj4gPiBD YzogTWF0dGhpYXMgQnJ1Z2dlciA8bWF0dGhpYXMuYmdnQGdtYWlsLmNvbT4NCj4gPiBTdWdnZXN0 ZWQtYnk6IFlvbmcgV3UgPHlvbmcud3VAbWVkaWF0ZWsuY29tPg0KPiA+IFNpZ25lZC1vZmYtYnk6 IENoYW8gSGFvIDxjaGFvLmhhb0BtZWRpYXRlay5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMv aW9tbXUvbXRrX2lvbW11LmMgfCAxMiArKysrKysrKysrKy0NCj4gPiAgZHJpdmVycy9pb21tdS9t dGtfaW9tbXUuaCB8ICAxICsNCj4gPiAgMiBmaWxlcyBjaGFuZ2VkLCAxMiBpbnNlcnRpb25zKCsp LCAxIGRlbGV0aW9uKC0pDQo+ID4gDQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaW9tbXUvbXRr X2lvbW11LmMgYi9kcml2ZXJzL2lvbW11L210a19pb21tdS5jDQo+ID4gaW5kZXggOGY4MWRmNmNi ZTUxLi42N2I0NmI1ZDgzZDkgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9pb21tdS9tdGtfaW9t bXUuYw0KPiA+ICsrKyBiL2RyaXZlcnMvaW9tbXUvbXRrX2lvbW11LmMNCj4gPiBAQCAtNDIsNiAr NDIsOSBAQA0KPiA+ICAjZGVmaW5lIEZfSU5WTERfRU4xCQkJCUJJVCgxKQ0KPiA+ICANCj4gPiAg I2RlZmluZSBSRUdfTU1VX01JU0NfQ1RSTAkJCTB4MDQ4DQo+ID4gKyNkZWZpbmUgRl9NTVVfSU5f T1JERVJfV1JfRU4JCQkoQklUKDEpIHwgQklUKDE3KSkNCj4gPiArI2RlZmluZSBGX01NVV9TVEFO REFSRF9BWElfTU9ERV9CSVQJCShCSVQoMykgfCBCSVQoMTkpKQ0KPiANCj4gV291bGRuJ3QgaXQg bWFrZSBtb3JlIHNlbnNlIHRvIG5hbWUgaXQgRl9NTVVfU1RBTkRBUkRfQVhJX01PREVfRU4/DQpv aywgeW91IGFyZSByaWdodC4NCjEnYjE6IGZvbGxvdyBzdGFuZGFyZCBheGkgcHJvdG9jb2wNCg0K PiANCj4gPiArDQo+ID4gICNkZWZpbmUgUkVHX01NVV9EQ01fRElTCQkJCTB4MDUwDQo+ID4gIA0K PiA+ICAjZGVmaW5lIFJFR19NTVVfQ1RSTF9SRUcJCQkweDExMA0KPiA+IEBAIC01NzQsMTAgKzU3 NywxNyBAQCBzdGF0aWMgaW50IG10a19pb21tdV9od19pbml0KGNvbnN0IHN0cnVjdCBtdGtfaW9t bXVfZGF0YSAqZGF0YSkNCj4gPiAgCX0NCj4gPiAgCXdyaXRlbF9yZWxheGVkKDAsIGRhdGEtPmJh c2UgKyBSRUdfTU1VX0RDTV9ESVMpOw0KPiA+ICANCj4gPiArCXJlZ3ZhbCA9IHJlYWRsX3JlbGF4 ZWQoZGF0YS0+YmFzZSArIFJFR19NTVVfTUlTQ19DVFJMKTsNCj4gDQo+IFdlIG9ubHkgbmVlZCB0 byByZWFkIHJlZ3ZhbCBpbiB0aGUgZWxzZSBicmFuY2guDQoNCm9rLCBJIGdvdCBpdC4gdGhhbmtz DQoNCj4gDQo+ID4gIAlpZiAoTVRLX0lPTU1VX0hBU19GTEFHKGRhdGEtPnBsYXRfZGF0YSwgUkVT RVRfQVhJKSkgew0KPiA+ICAJCS8qIFRoZSByZWdpc3RlciBpcyBjYWxsZWQgU1RBTkRBUkRfQVhJ X01PREUgaW4gdGhpcyBjYXNlICovDQo+ID4gLQkJd3JpdGVsX3JlbGF4ZWQoMCwgZGF0YS0+YmFz ZSArIFJFR19NTVVfTUlTQ19DVFJMKTsNCj4gPiArCQlyZWd2YWwgPSAwOw0KPiA+ICsJfSBlbHNl IHsNCj4gPiArCQkvKiBGb3IgbW1faW9tbXUsIGl0IGNhbiBpbXByb3ZlIHBlcmZvcm1hbmNlIGJ5 IHRoZSBzZXR0aW5nICovDQo+ID4gKwkJcmVndmFsICY9IH5GX01NVV9TVEFOREFSRF9BWElfTU9E RV9CSVQ7DQo+ID4gKwkJaWYgKE1US19JT01NVV9IQVNfRkxBRyhkYXRhLT5wbGF0X2RhdGEsIE9V VF9PUkRFUl9FTikpDQo+ID4gKwkJCXJlZ3ZhbCAmPSB+Rl9NTVVfSU5fT1JERVJfV1JfRU47DQo+ ID4gIAl9DQo+ID4gKwl3cml0ZWxfcmVsYXhlZChyZWd2YWwsIGRhdGEtPmJhc2UgKyBSRUdfTU1V X01JU0NfQ1RSTCk7DQo+ID4gIA0KPiA+ICAJaWYgKGRldm1fcmVxdWVzdF9pcnEoZGF0YS0+ZGV2 LCBkYXRhLT5pcnEsIG10a19pb21tdV9pc3IsIDAsDQo+ID4gIAkJCSAgICAgZGV2X25hbWUoZGF0 YS0+ZGV2KSwgKHZvaWQgKilkYXRhKSkgew0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2lvbW11 L210a19pb21tdS5oIGIvZHJpdmVycy9pb21tdS9tdGtfaW9tbXUuaA0KPiA+IGluZGV4IDdjYzM5 ZjcyOTI2My4uNGI3ODBiNjUxZWY0IDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvaW9tbXUvbXRr X2lvbW11LmgNCj4gPiArKysgYi9kcml2ZXJzL2lvbW11L210a19pb21tdS5oDQo+ID4gQEAgLTIy LDYgKzIyLDcgQEANCj4gPiAgI2RlZmluZSBIQVNfQkNMSwkJCUJJVCgxKQ0KPiA+ICAjZGVmaW5l IEhBU19WTERfUEFfUk5HCQkJQklUKDIpDQo+ID4gICNkZWZpbmUgUkVTRVRfQVhJCQkJQklUKDMp DQo+ID4gKyNkZWZpbmUgT1VUX09SREVSX0VOCQkJQklUKDQpDQo+IA0KPiBNYXliZSBzb21ldGhp bmcgbGlrZSBPVVRfT1JERVJfV1JfRU4sIHRvIG1ha2UgY2xlYXIgdGhhdCBpdCdzIGFib3V0IHRo ZSB0aGUNCj4gd3JpdGUgcGF0aC4NCj4gDQpvaywgdGhhbmtzIGZvciB5b3VyIGFkdmljZS4NCg0K PiA+ICANCj4gPiAgI2RlZmluZSBNVEtfSU9NTVVfSEFTX0ZMQUcocGRhdGEsIF94KSBcDQo+ID4g IAkJKCgoKHBkYXRhKS0+ZmxhZ3MpICYgKF94KSkgPT0gKF94KSkNCj4gPiANCg0K