From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
bhelgaas@google.com, robh+dt@kernel.org, kishon@ti.com,
vkoul@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
svarbanov@mm-sol.com, lorenzo.pieralisi@arm.com,
p.zabel@pengutronix.de, sivaprak@codeaurora.org,
mgautam@codeaurora.org, smuthayy@codeaurora.org,
varada@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Subject: [PATCH 9/9] arm64: dts: ipq8074: Fixup pcie dts nodes
Date: Sun, 5 Jul 2020 14:48:00 +0530 [thread overview]
Message-ID: <1593940680-2363-10-git-send-email-sivaprak@codeaurora.org> (raw)
In-Reply-To: <1593940680-2363-1-git-send-email-sivaprak@codeaurora.org>
ipq8074 pcie nodes missing several properties which is needed to make
them work add these properties.
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +--
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 ++++++++++++++++++++----------
2 files changed, 78 insertions(+), 39 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6754cb0638f4..dfb8ad73f134 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -52,19 +52,19 @@
&pcie0 {
status = "ok";
- perst-gpio = <&tlmm 61 0x1>;
+ perst-gpio = <&tlmm 58 0x1>;
};
&pcie1 {
status = "ok";
- perst-gpio = <&tlmm 58 0x1>;
+ perst-gpio = <&tlmm 61 0x1>;
};
-&pcie_phy0 {
+&qmp_pcie_phy0 {
status = "ok";
};
-&pcie_phy1 {
+&qmp_pcie_phy1 {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821300b4..5bb58b70199e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -82,34 +82,66 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pcie_phy0: phy@86000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x00086000 0x1000>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy0_pipe_clk";
+ qmp_pcie_phy0: phy@84000 {
+ compatible = "qcom,ipq8074-qmp-pcie-gen3-phy";
+ reg = <0x00084000 0x1bc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy0: lane@84200 {
+ reg = <0x84200 0x16c>, /* Serdes Tx */
+ <0x84400 0x200>, /* Serdes Rx */
+ <0x84800 0x4f4>; /* PCS: Lane0, COM, PCIE */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ clock-output-rate = <250000000>;
+ #clock-cells = <0>;
+ };
};
- pcie_phy1: phy@8e000 {
+ qmp_pcie_phy1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1000>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy1_pipe_clk";
+ reg = <0x8e000 0x1c4>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = <&gcc GCC_PCIE1_PHY_BCR>,
- <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy1: lane@8e200 {
+ reg = <0x8e200 0x130>, /* Serdes Tx */
+ <0x8e400 0x200>, /* Serdes Rx */
+ <0x8e800 0x1f8>; /* PCS */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie1_pipe_clk_src";
+ clock-output-rate = <125000000>;
+ #clock-cells = <0>;
+ };
};
tlmm: pinctrl@1000000 {
@@ -370,10 +402,10 @@
pcie1: pci@10000000 {
compatible = "qcom,pcie-ipq8074";
- reg = <0x10000000 0xf1d
- 0x10000f20 0xa8
- 0x00088000 0x2000
- 0x10100000 0x1000>;
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x00088000 0x2000>,
+ <0x10100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
@@ -386,9 +418,9 @@
phy-names = "pciephy";
ranges = <0x81000000 0 0x10200000 0x10200000
- 0 0x100000 /* downstream I/O */
- 0x82000000 0 0x10300000 0x10300000
- 0 0xd00000>; /* non-prefetchable memory */
+ 0 0x100000>, /* downstream I/O */
+ <0x82000000 0 0x10220000 0x10220000
+ 0 0xfde0000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -431,12 +463,13 @@
};
pcie0: pci@20000000 {
- compatible = "qcom,pcie-ipq8074";
- reg = <0x20000000 0xf1d
- 0x20000f20 0xa8
- 0x00080000 0x2000
- 0x20100000 0x1000>;
- reg-names = "dbi", "elbi", "parf", "config";
+ compatible = "qcom,pcie-ipq8074-gen3";
+ reg = <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00080000 0x4000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
@@ -448,9 +481,9 @@
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0x20200000
- 0 0x100000 /* downstream I/O */
- 0x82000000 0 0x20300000 0x20300000
- 0 0xd00000>; /* non-prefetchable memory */
+ 0 0x100000>, /* downstream I/O */
+ <0x82000000 0 0x20220000 0x20220000
+ 0 0xfde0000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -469,27 +502,33 @@
<&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
- <&gcc GCC_PCIE0_AUX_CLK>;
+ <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE0_RCHNG_CLK>;
clock-names = "iface",
"axi_m",
"axi_s",
"ahb",
- "aux";
+ "aux",
+ "axi_bridge",
+ "rchng";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
- "axi_m_sticky";
+ "axi_m_sticky",
+ "axi_s_sticky";
status = "disabled";
};
};
--
2.7.4
next prev parent reply other threads:[~2020-07-05 9:18 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-05 9:17 [PATCH 0/9] Add PCIe support for IPQ8074 Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 1/9] dt-bindings: pci: Add ipq8074 gen3 pci compatible Sivaprakash Murugesan
2020-07-15 21:50 ` Rob Herring
2020-07-05 9:17 ` [PATCH 2/9] dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy Sivaprakash Murugesan
2020-07-15 21:50 ` Rob Herring
2020-07-05 9:17 ` [PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie Sivaprakash Murugesan
2020-07-11 16:12 ` Stephen Boyd
2020-07-05 9:17 ` [PATCH 4/9] clk: qcom: ipq8074: Add missing clocks " Sivaprakash Murugesan
2020-07-11 16:10 ` Stephen Boyd
2020-07-11 16:12 ` Stephen Boyd
2020-07-05 9:17 ` [PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init Sivaprakash Murugesan
2020-07-10 14:02 ` Sasha Levin
2020-07-13 5:55 ` Vinod Koul
2020-07-29 6:45 ` Sivaprakash Murugesan
2020-08-03 11:03 ` Vinod Koul
2020-07-05 9:17 ` [PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy Sivaprakash Murugesan
2020-07-13 6:04 ` Vinod Koul
2020-07-29 7:46 ` Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 7/9] pci: dwc: qcom: do phy power on before pcie init Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 8/9] pci: qcom: Add support for ipq8074 pci controller Sivaprakash Murugesan
2020-07-05 9:18 ` Sivaprakash Murugesan [this message]
2020-07-06 23:49 ` [PATCH 0/9] Add PCIe support for IPQ8074 Bjorn Helgaas
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