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X-UUID: 1f5ee34c1b514bc68d959a307bc0f959-20200717 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1625753150; Fri, 17 Jul 2020 16:18:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Jul 2020 16:18:24 +0800 Received: from [172.21.77.33] (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Jul 2020 16:18:24 +0800 Message-ID: <1594973906.12796.20.camel@mtkswgap22> Subject: Re: [PATCH 1/4] dt-bindings: mediatek: add mediatek,infracfg phandle From: Miles Chen To: Rob Herring Date: Fri, 17 Jul 2020 16:18:26 +0800 In-Reply-To: <20200715205120.GA778876@bogus> References: <20200702093721.6063-1-miles.chen@mediatek.com> <20200715205120.GA778876@bogus> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 5CB742BDEFA856503BBD69CE4475BAA8884078200B5E49D595D6209E416DC56D2000:8 X-MTK: N Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Chao Hao , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, 2020-07-15 at 14:51 -0600, Rob Herring wrote: > On Thu, Jul 02, 2020 at 05:37:17PM +0800, Miles Chen wrote: > > Add a description for mediatek,infracfg. We can check if 4GB mode > > is enable by reading it instead of checking the unexported > > symbol "max_pfn". > > > > This is a step towards building mtk_iommu as a kernel module. > > You determined this before without DT, so it is an OS problem and > shouldn't need a DT update. Thanks for your comment. The old way (using max_pfn) do determine this is risky because the max_pfn may lower than (GB if reserved memory regions occupy memory higher than 4GB. So, the better way to do this is by reading register from H/W. > > I'd assume there's only one instance of the node mediatek,infracfg > points to, so just search for it if you want to get the info from DT. > I can do syscon_regmap_lookup_by_compatible() to search for it. However, the compatibles are different in mt2712e.dtsi and mt8173.dtsi. so I have to search "mediatek,mt2712-infracfg" and "mediatek,mt8173-infracfg" respectively. Using mediatek,infracfg phandle can make the code easier to read. Is it possible to reconsider the phandle approach, please? arch/arm64/boot/dts/mediatek/mt2712e.dtsi:253: infracfg: syscon@10001000 { compatible = "mediatek,mt2712-infracfg", "syscon"; arch/arm64/boot/dts/mediatek/mt8173.dtsi:363: infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; > > > > > Cc: Yong Wu > > Signed-off-by: Miles Chen > > --- > > Documentation/devicetree/bindings/iommu/mediatek,iommu.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..a7881deabcca 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -74,6 +74,8 @@ Required properties: > > - mediatek,larbs : List of phandle to the local arbiters in the current Socs. > > Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > > according to the local arbiter index, like larb0, larb1, larb2... > > +- mediatek,infracfg: a phandle to infracfg. It is used to confirm if 4GB mode is set. > > + It is an optional property, add it when the SoC have 4g mode. > > - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > -- > > 2.18.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19F1C433EA for ; Fri, 17 Jul 2020 08:18:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C163A2074B for ; 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bh=jFgiHvr1fVVgOZ8IpoZq8KSqHUKORJrsDZDgN40XiAY=; b=h8WRNFGZ7w4shM3mbMkE2zKSbK1FnBwTqhMP4RtCVTBwu0UAbxwEL4/4SXr27m5Aq9Jo+yPsG0iSov9pqX5V+Rx4rWKLOAF0aftWk2hmfA5kNk+55XbYjbUl3ueCcMZ/xuJeHxiG+9qM0+1GAbIxL0ey+TiVl6K/ycl06VgQJdQ=; X-UUID: 55b3d26eec694496a2aa2e52602b6805-20200717 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1184320695; Fri, 17 Jul 2020 00:18:41 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Jul 2020 01:18:28 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Jul 2020 16:18:24 +0800 Received: from [172.21.77.33] (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Jul 2020 16:18:24 +0800 Message-ID: <1594973906.12796.20.camel@mtkswgap22> Subject: Re: [PATCH 1/4] dt-bindings: mediatek: add mediatek,infracfg phandle From: Miles Chen To: Rob Herring Date: Fri, 17 Jul 2020 16:18:26 +0800 In-Reply-To: <20200715205120.GA778876@bogus> References: <20200702093721.6063-1-miles.chen@mediatek.com> <20200715205120.GA778876@bogus> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 5CB742BDEFA856503BBD69CE4475BAA8884078200B5E49D595D6209E416DC56D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_041841_335166_D6EC07C1 X-CRM114-Status: GOOD ( 24.33 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, wsd_upstream@mediatek.com, Joerg Roedel , linux-kernel@vger.kernel.org, Chao Hao , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Yong Wu , Matthias Brugger , Yingjoe Chen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-07-15 at 14:51 -0600, Rob Herring wrote: > On Thu, Jul 02, 2020 at 05:37:17PM +0800, Miles Chen wrote: > > Add a description for mediatek,infracfg. We can check if 4GB mode > > is enable by reading it instead of checking the unexported > > symbol "max_pfn". > > > > This is a step towards building mtk_iommu as a kernel module. > > You determined this before without DT, so it is an OS problem and > shouldn't need a DT update. Thanks for your comment. The old way (using max_pfn) do determine this is risky because the max_pfn may lower than (GB if reserved memory regions occupy memory higher than 4GB. So, the better way to do this is by reading register from H/W. > > I'd assume there's only one instance of the node mediatek,infracfg > points to, so just search for it if you want to get the info from DT. > I can do syscon_regmap_lookup_by_compatible() to search for it. However, the compatibles are different in mt2712e.dtsi and mt8173.dtsi. so I have to search "mediatek,mt2712-infracfg" and "mediatek,mt8173-infracfg" respectively. Using mediatek,infracfg phandle can make the code easier to read. Is it possible to reconsider the phandle approach, please? arch/arm64/boot/dts/mediatek/mt2712e.dtsi:253: infracfg: syscon@10001000 { compatible = "mediatek,mt2712-infracfg", "syscon"; arch/arm64/boot/dts/mediatek/mt8173.dtsi:363: infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; > > > > > Cc: Yong Wu > > Signed-off-by: Miles Chen > > --- > > Documentation/devicetree/bindings/iommu/mediatek,iommu.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..a7881deabcca 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -74,6 +74,8 @@ Required properties: > > - mediatek,larbs : List of phandle to the local arbiters in the current Socs. > > Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > > according to the local arbiter index, like larb0, larb1, larb2... > > +- mediatek,infracfg: a phandle to infracfg. It is used to confirm if 4GB mode is set. > > + It is an optional property, add it when the SoC have 4g mode. > > - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > -- > > 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32164C433E4 for ; Fri, 17 Jul 2020 08:20:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EDE342074B for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-07-15 at 14:51 -0600, Rob Herring wrote: > On Thu, Jul 02, 2020 at 05:37:17PM +0800, Miles Chen wrote: > > Add a description for mediatek,infracfg. We can check if 4GB mode > > is enable by reading it instead of checking the unexported > > symbol "max_pfn". > > > > This is a step towards building mtk_iommu as a kernel module. > > You determined this before without DT, so it is an OS problem and > shouldn't need a DT update. Thanks for your comment. The old way (using max_pfn) do determine this is risky because the max_pfn may lower than (GB if reserved memory regions occupy memory higher than 4GB. So, the better way to do this is by reading register from H/W. > > I'd assume there's only one instance of the node mediatek,infracfg > points to, so just search for it if you want to get the info from DT. > I can do syscon_regmap_lookup_by_compatible() to search for it. However, the compatibles are different in mt2712e.dtsi and mt8173.dtsi. so I have to search "mediatek,mt2712-infracfg" and "mediatek,mt8173-infracfg" respectively. Using mediatek,infracfg phandle can make the code easier to read. Is it possible to reconsider the phandle approach, please? arch/arm64/boot/dts/mediatek/mt2712e.dtsi:253: infracfg: syscon@10001000 { compatible = "mediatek,mt2712-infracfg", "syscon"; arch/arm64/boot/dts/mediatek/mt8173.dtsi:363: infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; > > > > > Cc: Yong Wu > > Signed-off-by: Miles Chen > > --- > > Documentation/devicetree/bindings/iommu/mediatek,iommu.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > index ce59a505f5a4..a7881deabcca 100644 > > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > @@ -74,6 +74,8 @@ Required properties: > > - mediatek,larbs : List of phandle to the local arbiters in the current Socs. > > Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > > according to the local arbiter index, like larb0, larb1, larb2... > > +- mediatek,infracfg: a phandle to infracfg. It is used to confirm if 4GB mode is set. > > + It is an optional property, add it when the SoC have 4g mode. > > - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > > Specifies the mtk_m4u_id as defined in > > dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > > -- > > 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8072C433E1 for ; Fri, 17 Jul 2020 08:18:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B35120768 for ; Fri, 17 Jul 2020 08:18:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="h8WRNFGZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726426AbgGQISe (ORCPT ); Fri, 17 Jul 2020 04:18:34 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:50129 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726240AbgGQISd (ORCPT ); Fri, 17 Jul 2020 04:18:33 -0400 X-UUID: 1f5ee34c1b514bc68d959a307bc0f959-20200717 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=jFgiHvr1fVVgOZ8IpoZq8KSqHUKORJrsDZDgN40XiAY=; b=h8WRNFGZ7w4shM3mbMkE2zKSbK1FnBwTqhMP4RtCVTBwu0UAbxwEL4/4SXr27m5Aq9Jo+yPsG0iSov9pqX5V+Rx4rWKLOAF0aftWk2hmfA5kNk+55XbYjbUl3ueCcMZ/xuJeHxiG+9qM0+1GAbIxL0ey+TiVl6K/ycl06VgQJdQ=; X-UUID: 1f5ee34c1b514bc68d959a307bc0f959-20200717 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1625753150; Fri, 17 Jul 2020 16:18:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Jul 2020 16:18:24 +0800 Received: from [172.21.77.33] (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Jul 2020 16:18:24 +0800 Message-ID: <1594973906.12796.20.camel@mtkswgap22> Subject: Re: [PATCH 1/4] dt-bindings: mediatek: add mediatek,infracfg phandle From: Miles Chen To: Rob Herring CC: Joerg Roedel , Matthias Brugger , , , , , , , Yong Wu , Chao Hao , Yingjoe Chen Date: Fri, 17 Jul 2020 16:18:26 +0800 In-Reply-To: <20200715205120.GA778876@bogus> References: <20200702093721.6063-1-miles.chen@mediatek.com> <20200715205120.GA778876@bogus> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-TM-SNTS-SMTP: 5CB742BDEFA856503BBD69CE4475BAA8884078200B5E49D595D6209E416DC56D2000:8 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gV2VkLCAyMDIwLTA3LTE1IGF0IDE0OjUxIC0wNjAwLCBSb2IgSGVycmluZyB3cm90ZToNCj4g T24gVGh1LCBKdWwgMDIsIDIwMjAgYXQgMDU6Mzc6MTdQTSArMDgwMCwgTWlsZXMgQ2hlbiB3cm90 ZToNCj4gPiBBZGQgYSBkZXNjcmlwdGlvbiBmb3IgbWVkaWF0ZWssaW5mcmFjZmcuIFdlIGNhbiBj aGVjayBpZiA0R0IgbW9kZQ0KPiA+IGlzIGVuYWJsZSBieSByZWFkaW5nIGl0IGluc3RlYWQgb2Yg Y2hlY2tpbmcgdGhlIHVuZXhwb3J0ZWQNCj4gPiBzeW1ib2wgIm1heF9wZm4iLg0KPiA+IA0KPiA+ IFRoaXMgaXMgYSBzdGVwIHRvd2FyZHMgYnVpbGRpbmcgbXRrX2lvbW11IGFzIGEga2VybmVsIG1v ZHVsZS4NCj4gDQo+IFlvdSBkZXRlcm1pbmVkIHRoaXMgYmVmb3JlIHdpdGhvdXQgRFQsIHNvIGl0 IGlzIGFuIE9TIHByb2JsZW0gYW5kIA0KPiBzaG91bGRuJ3QgbmVlZCBhIERUIHVwZGF0ZS4NCg0K VGhhbmtzIGZvciB5b3VyIGNvbW1lbnQuDQoNClRoZSBvbGQgd2F5ICh1c2luZyBtYXhfcGZuKSBk byBkZXRlcm1pbmUgdGhpcyBpcyByaXNreSBiZWNhdXNlIHRoZQ0KbWF4X3BmbiBtYXkgbG93ZXIg dGhhbiAoR0IgaWYgcmVzZXJ2ZWQgbWVtb3J5IHJlZ2lvbnMgb2NjdXB5IG1lbW9yeQ0KaGlnaGVy IHRoYW4gNEdCLg0KDQpTbywgdGhlIGJldHRlciB3YXkgdG8gZG8gdGhpcyBpcyBieSByZWFkaW5n IHJlZ2lzdGVyIGZyb20gSC9XLg0KPiANCj4gSSdkIGFzc3VtZSB0aGVyZSdzIG9ubHkgb25lIGlu c3RhbmNlIG9mIHRoZSBub2RlIG1lZGlhdGVrLGluZnJhY2ZnIA0KPiBwb2ludHMgdG8sIHNvIGp1 c3Qgc2VhcmNoIGZvciBpdCBpZiB5b3Ugd2FudCB0byBnZXQgdGhlIGluZm8gZnJvbSBEVC4NCj4g DQpJIGNhbiBkbyBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9jb21wYXRpYmxlKCkgdG8gc2VhcmNo IGZvciBpdC4gSG93ZXZlciwNCnRoZSBjb21wYXRpYmxlcyBhcmUgZGlmZmVyZW50IGluIG10Mjcx MmUuZHRzaSBhbmQgbXQ4MTczLmR0c2kuIHNvIEkgaGF2ZQ0KdG8gc2VhcmNoICJtZWRpYXRlayxt dDI3MTItaW5mcmFjZmciIGFuZCAibWVkaWF0ZWssbXQ4MTczLWluZnJhY2ZnIg0KcmVzcGVjdGl2 ZWx5Lg0KDQpVc2luZyBtZWRpYXRlayxpbmZyYWNmZyBwaGFuZGxlIGNhbiBtYWtlIHRoZSBjb2Rl IGVhc2llciB0byByZWFkLg0KSXMgaXQgcG9zc2libGUgdG8gcmVjb25zaWRlciB0aGUgcGhhbmRs ZSBhcHByb2FjaCwgcGxlYXNlPw0KDQoNCmFyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQy NzEyZS5kdHNpOjI1MzoNCmluZnJhY2ZnOiBzeXNjb25AMTAwMDEwMDAgew0KY29tcGF0aWJsZSA9 ICJtZWRpYXRlayxtdDI3MTItaW5mcmFjZmciLCAic3lzY29uIjsNCmFyY2gvYXJtNjQvYm9vdC9k dHMvbWVkaWF0ZWsvbXQ4MTczLmR0c2k6MzYzOiAgICAgICAgICAgICAgICAgICANCmluZnJhY2Zn OiBwb3dlci1jb250cm9sbGVyQDEwMDAxMDAwIHsNCmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4 MTczLWluZnJhY2ZnIiwgInN5c2NvbiI7DQoNCg0KDQo+IA0KPiA+IA0KPiA+IENjOiBZb25nIFd1 IDx5b25nLnd1QG1lZGlhdGVrLmNvbT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBNaWxlcyBDaGVuIDxt aWxlcy5jaGVuQG1lZGlhdGVrLmNvbT4NCj4gPiAtLS0NCj4gPiAgRG9jdW1lbnRhdGlvbi9kZXZp Y2V0cmVlL2JpbmRpbmdzL2lvbW11L21lZGlhdGVrLGlvbW11LnR4dCB8IDIgKysNCj4gPiAgMSBm aWxlIGNoYW5nZWQsIDIgaW5zZXJ0aW9ucygrKQ0KPiA+IA0KPiA+IGRpZmYgLS1naXQgYS9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvbWVkaWF0ZWssaW9tbXUudHh0IGIv RG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2lvbW11L21lZGlhdGVrLGlvbW11LnR4 dA0KPiA+IGluZGV4IGNlNTlhNTA1ZjVhNC4uYTc4ODFkZWFiY2NhIDEwMDY0NA0KPiA+IC0tLSBh L0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9pb21tdS9tZWRpYXRlayxpb21tdS50 eHQNCj4gPiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvbWVk aWF0ZWssaW9tbXUudHh0DQo+ID4gQEAgLTc0LDYgKzc0LDggQEAgUmVxdWlyZWQgcHJvcGVydGll czoNCj4gPiAgLSBtZWRpYXRlayxsYXJicyA6IExpc3Qgb2YgcGhhbmRsZSB0byB0aGUgbG9jYWwg YXJiaXRlcnMgaW4gdGhlIGN1cnJlbnQgU29jcy4NCj4gPiAgCVJlZmVyIHRvIGJpbmRpbmdzL21l bW9yeS1jb250cm9sbGVycy9tZWRpYXRlayxzbWktbGFyYi50eHQuIEl0IG11c3Qgc29ydA0KPiA+ ICAJYWNjb3JkaW5nIHRvIHRoZSBsb2NhbCBhcmJpdGVyIGluZGV4LCBsaWtlIGxhcmIwLCBsYXJi MSwgbGFyYjIuLi4NCj4gPiArLSBtZWRpYXRlayxpbmZyYWNmZzogYSBwaGFuZGxlIHRvIGluZnJh Y2ZnLiBJdCBpcyB1c2VkIHRvIGNvbmZpcm0gaWYgNEdCIG1vZGUgaXMgc2V0Lg0KPiA+ICsJSXQg aXMgYW4gb3B0aW9uYWwgcHJvcGVydHksIGFkZCBpdCB3aGVuIHRoZSBTb0MgaGF2ZSA0ZyBtb2Rl Lg0KPiA+ICAtIGlvbW11LWNlbGxzIDogbXVzdCBiZSAxLiBUaGlzIGlzIHRoZSBtdGtfbTR1X2lk IGFjY29yZGluZyB0byB0aGUgSFcuDQo+ID4gIAlTcGVjaWZpZXMgdGhlIG10a19tNHVfaWQgYXMg ZGVmaW5lZCBpbg0KPiA+ICAJZHQtYmluZGluZy9tZW1vcnkvbXQyNzAxLWxhcmItcG9ydC5oIGZv ciBtdDI3MDEsIG10NzYyMw0KPiA+IC0tIA0KPiA+IDIuMTguMA0KDQo=