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Thu, 23 Jul 2020 02:05:14 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jul 2020 03:05:13 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jul 2020 18:05:11 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jul 2020 18:05:12 +0800 Message-ID: <1595498644.13250.2.camel@mhfsdcap03> Subject: Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h From: Yongqiang Niu To: Enric Balletbo Serra Date: Thu, 23 Jul 2020 18:04:04 +0800 In-Reply-To: References: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com> <1595469798-3824-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_060521_372356_7AEC181A X-CRM114-Status: GOOD ( 19.20 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , "devicetree@vger.kernel.org" , Philipp Zabel , David Airlie , linux-kernel , dri-devel , Matthias Brugger , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include > > +#include > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include > > +#include > > #include > > #include > > #include > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D46CC433DF for ; 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Thu, 23 Jul 2020 18:05:11 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jul 2020 18:05:12 +0800 Message-ID: <1595498644.13250.2.camel@mhfsdcap03> Subject: Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h From: Yongqiang Niu To: Enric Balletbo Serra Date: Thu, 23 Jul 2020 18:04:04 +0800 In-Reply-To: References: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com> <1595469798-3824-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_060521_372356_7AEC181A X-CRM114-Status: GOOD ( 19.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , "devicetree@vger.kernel.org" , Philipp Zabel , David Airlie , linux-kernel , dri-devel , Matthias Brugger , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , CK Hu , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include > > +#include > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include > > +#include > > #include > > #include > > #include > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC803C433DF for ; Thu, 23 Jul 2020 10:05:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2FA02065E for ; Thu, 23 Jul 2020 10:05:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NU0SiGyA" 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Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1215864354; Thu, 23 Jul 2020 18:05:13 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jul 2020 18:05:11 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jul 2020 18:05:12 +0800 Message-ID: <1595498644.13250.2.camel@mhfsdcap03> Subject: Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h From: Yongqiang Niu Reply-To: Yongqiang Niu To: Enric Balletbo Serra CC: CK Hu , Philipp Zabel , "Rob Herring" , Matthias Brugger , David Airlie , Daniel Vetter , "Mark Rutland" , dri-devel , "devicetree@vger.kernel.org" , linux-kernel , Linux ARM , "moderated list:ARM/Mediatek SoC support" Date: Thu, 23 Jul 2020 18:04:04 +0800 In-Reply-To: References: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com> <1595469798-3824-2-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gVGh1LCAyMDIwLTA3LTIzIGF0IDExOjM0ICswMjAwLCBFbnJpYyBCYWxsZXRibyBTZXJyYSB3 cm90ZToNCj4gSGkgWW9uZ3FpYW4gTml1LA0KPiANCj4gVGhhbmsgeW91IGZvciB5b3VyIHBhdGNo DQo+IA0KPiBNaXNzYXRnZSBkZSBZb25ncWlhbmcgTml1IDx5b25ncWlhbmcubml1QG1lZGlhdGVr LmNvbT4gZGVsIGRpYSBkai4sIDIzDQo+IGRlIGp1bC4gMjAyMCBhIGxlcyA0OjA1Og0KPiA+DQo+ ID4gbW92ZSBkZHAgY29tcG9uZW50IGRlZmludCBpbnRvIG10a19tbXN5cy5oDQo+ID4NCj4gDQo+ IFRoZXJlIGlzIGEgdHlwbywgc2hvdWxkIGJlICJkZWZpbmVzIi4gQnV0IHdoeSB5b3Ugc2hvdWxk IG1vdmUgdGhlc2UNCj4gZGVmaW5lcyB0byBtdGstbW1zeXM/DQo+IA0KDQpjayBkbyBub3QgbGlr ZSB0aGlzIDoNCj4gLSNpbmNsdWRlICIuLi8uLi9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRw LmgiDQo+IC0jaW5jbHVkZSAiLi4vLi4vZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21w LmgiDQoNCmFmdGVyIHJlbW92ZSB0aGlzLCB3ZSBuZWVkIG1vdmUgdGhlIGRkcCBjb21wb25lbnQg ZGVmaW5lDQoNCnR5cGUgZXJyb3Igd2lsbCBmaXhlZCBpbiBuZXh0IHZlcnNpb24uDQoNCg0KPiAN Cj4gDQo+ID4gU2lnbmVkLW9mZi1ieTogWW9uZ3FpYW5nIE5pdSA8eW9uZ3FpYW5nLm5pdUBtZWRp YXRlay5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJt X2RkcF9jb21wLmggfCAzNCArLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQ0KPiA+ICBkcml2 ZXJzL3NvYy9tZWRpYXRlay9tdGstbW1zeXMuYyAgICAgICAgICAgIHwgIDQgKy0tLQ0KPiA+ICBp bmNsdWRlL2xpbnV4L3NvYy9tZWRpYXRlay9tdGstbW1zeXMuaCAgICAgIHwgMzMgKysrKysrKysr KysrKysrKysrKysrKysrKysrKw0KPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDM1IGluc2VydGlvbnMo KyksIDM2IGRlbGV0aW9ucygtKQ0KPiA+DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kZHBfY29tcC5oDQo+ID4gaW5kZXggZGViZTM2My4uMTYxMjAxZiAxMDA2NDQNCj4g PiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5oDQo+ID4g KysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaA0KPiA+IEBA IC03LDYgKzcsNyBAQA0KPiA+ICAjZGVmaW5lIE1US19EUk1fRERQX0NPTVBfSA0KPiA+DQo+ID4g ICNpbmNsdWRlIDxsaW51eC9pby5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvc29jL21lZGlhdGVr L210ay1tbXN5cy5oPg0KPiA+DQo+ID4gIHN0cnVjdCBkZXZpY2U7DQo+ID4gIHN0cnVjdCBkZXZp Y2Vfbm9kZTsNCj4gPiBAQCAtMzUsMzkgKzM2LDYgQEAgZW51bSBtdGtfZGRwX2NvbXBfdHlwZSB7 DQo+ID4gICAgICAgICBNVEtfRERQX0NPTVBfVFlQRV9NQVgsDQo+ID4gIH07DQo+ID4NCj4gPiAt ZW51bSBtdGtfZGRwX2NvbXBfaWQgew0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9BQUwwLA0K PiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9BQUwxLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVO VF9CTFMsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX0NDT1JSLA0KPiA+IC0gICAgICAgRERQ X0NPTVBPTkVOVF9DT0xPUjAsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX0NPTE9SMSwNCj4g PiAtICAgICAgIEREUF9DT01QT05FTlRfRElUSEVSLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVO VF9EUEkwLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9EUEkxLA0KPiA+IC0gICAgICAgRERQ X0NPTVBPTkVOVF9EU0kwLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9EU0kxLA0KPiA+IC0g ICAgICAgRERQX0NPTVBPTkVOVF9EU0kyLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9EU0kz LA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9HQU1NQSwNCj4gPiAtICAgICAgIEREUF9DT01Q T05FTlRfT0QwLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9PRDEsDQo+ID4gLSAgICAgICBE RFBfQ09NUE9ORU5UX09WTDAsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX09WTF8yTDAsDQo+ ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX09WTF8yTDEsDQo+ID4gLSAgICAgICBERFBfQ09NUE9O RU5UX09WTDEsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX1BXTTAsDQo+ID4gLSAgICAgICBE RFBfQ09NUE9ORU5UX1BXTTEsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX1BXTTIsDQo+ID4g LSAgICAgICBERFBfQ09NUE9ORU5UX1JETUEwLA0KPiA+IC0gICAgICAgRERQX0NPTVBPTkVOVF9S RE1BMSwNCj4gPiAtICAgICAgIEREUF9DT01QT05FTlRfUkRNQTIsDQo+ID4gLSAgICAgICBERFBf Q09NUE9ORU5UX1VGT0UsDQo+ID4gLSAgICAgICBERFBfQ09NUE9ORU5UX1dETUEwLA0KPiA+IC0g ICAgICAgRERQX0NPTVBPTkVOVF9XRE1BMSwNCj4gPiAtICAgICAgIEREUF9DT01QT05FTlRfSURf TUFYLA0KPiA+IC19Ow0KPiA+IC0NCj4gPiAgc3RydWN0IG10a19kZHBfY29tcDsNCj4gPiAgc3Ry dWN0IGNtZHFfcGt0Ow0KPiA+ICBzdHJ1Y3QgbXRrX2RkcF9jb21wX2Z1bmNzIHsNCj4gPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmMgYi9kcml2ZXJzL3NvYy9t ZWRpYXRlay9tdGstbW1zeXMuYw0KPiA+IGluZGV4IGE1NWYyNTUuLjM2YWQ2NmIgMTAwNjQ0DQo+ ID4gLS0tIGEvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmMNCj4gPiArKysgYi9kcml2 ZXJzL3NvYy9tZWRpYXRlay9tdGstbW1zeXMuYw0KPiA+IEBAIC01LDEzICs1LDExIEBADQo+ID4g ICAqLw0KPiA+DQo+ID4gICNpbmNsdWRlIDxsaW51eC9kZXZpY2UuaD4NCj4gPiArI2luY2x1ZGUg PGxpbnV4L2lvLmg+DQo+ID4gICNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4NCj4gPiAgI2lu Y2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgvc29j L21lZGlhdGVrL210ay1tbXN5cy5oPg0KPiA+DQo+ID4gLSNpbmNsdWRlICIuLi8uLi9ncHUvZHJt L21lZGlhdGVrL210a19kcm1fZGRwLmgiDQo+ID4gLSNpbmNsdWRlICIuLi8uLi9ncHUvZHJtL21l ZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaCINCj4gPiAtDQo+ID4gICNkZWZpbmUgRElTUF9SRUdf Q09ORklHX0RJU1BfT1ZMMF9NT1VUX0VOICAgICAgMHgwNDANCj4gPiAgI2RlZmluZSBESVNQX1JF R19DT05GSUdfRElTUF9PVkwxX01PVVRfRU4gICAgICAweDA0NA0KPiA+ICAjZGVmaW5lIERJU1Bf UkVHX0NPTkZJR19ESVNQX09EX01PVVRfRU4gICAgICAgICAgICAgICAgMHgwNDgNCj4gPiBkaWZm IC0tZ2l0IGEvaW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lzLmggYi9pbmNsdWRl L2xpbnV4L3NvYy9tZWRpYXRlay9tdGstbW1zeXMuaA0KPiA+IGluZGV4IDdiYWI1ZDkuLjIyMjhi ZjYgMTAwNjQ0DQo+ID4gLS0tIGEvaW5jbHVkZS9saW51eC9zb2MvbWVkaWF0ZWsvbXRrLW1tc3lz LmgNCj4gPiArKysgYi9pbmNsdWRlL2xpbnV4L3NvYy9tZWRpYXRlay9tdGstbW1zeXMuaA0KPiA+ IEBAIC05LDYgKzksMzkgQEANCj4gPiAgZW51bSBtdGtfZGRwX2NvbXBfaWQ7DQo+ID4gIHN0cnVj dCBkZXZpY2U7DQo+ID4NCj4gPiArZW51bSBtdGtfZGRwX2NvbXBfaWQgew0KPiA+ICsgICAgICAg RERQX0NPTVBPTkVOVF9BQUwwLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9BQUwxLA0KPiA+ ICsgICAgICAgRERQX0NPTVBPTkVOVF9CTFMsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX0ND T1JSLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9DT0xPUjAsDQo+ID4gKyAgICAgICBERFBf Q09NUE9ORU5UX0NPTE9SMSwNCj4gPiArICAgICAgIEREUF9DT01QT05FTlRfRElUSEVSLA0KPiA+ ICsgICAgICAgRERQX0NPTVBPTkVOVF9EUEkwLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9E UEkxLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9EU0kwLA0KPiA+ICsgICAgICAgRERQX0NP TVBPTkVOVF9EU0kxLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9EU0kyLA0KPiA+ICsgICAg ICAgRERQX0NPTVBPTkVOVF9EU0kzLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9HQU1NQSwN Cj4gPiArICAgICAgIEREUF9DT01QT05FTlRfT0QwLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVO VF9PRDEsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX09WTDAsDQo+ID4gKyAgICAgICBERFBf Q09NUE9ORU5UX09WTF8yTDAsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX09WTF8yTDEsDQo+ ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX09WTDEsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5U X1BXTTAsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX1BXTTEsDQo+ID4gKyAgICAgICBERFBf Q09NUE9ORU5UX1BXTTIsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX1JETUEwLA0KPiA+ICsg ICAgICAgRERQX0NPTVBPTkVOVF9SRE1BMSwNCj4gPiArICAgICAgIEREUF9DT01QT05FTlRfUkRN QTIsDQo+ID4gKyAgICAgICBERFBfQ09NUE9ORU5UX1VGT0UsDQo+ID4gKyAgICAgICBERFBfQ09N UE9ORU5UX1dETUEwLA0KPiA+ICsgICAgICAgRERQX0NPTVBPTkVOVF9XRE1BMSwNCj4gPiArICAg ICAgIEREUF9DT01QT05FTlRfSURfTUFYLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAgdm9pZCBtdGtf bW1zeXNfZGRwX2Nvbm5lY3Qoc3RydWN0IGRldmljZSAqZGV2LA0KPiA+ICAgICAgICAgICAgICAg ICAgICAgICAgICAgIGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwNCj4gPiAgICAgICAgICAgICAg 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<1595498644.13250.2.camel@mhfsdcap03> Subject: Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h From: Yongqiang Niu To: Enric Balletbo Serra Date: Thu, 23 Jul 2020 18:04:04 +0800 In-Reply-To: References: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com> <1595469798-3824-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Fri, 24 Jul 2020 07:21:47 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , "devicetree@vger.kernel.org" , David Airlie , linux-kernel , dri-devel , Matthias Brugger , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include > > +#include > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include > > +#include > > #include > > #include > > #include > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel