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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add ti_syscon_reset() to integrate assert and deassert together, and change return value of the reset assert and deassert interface from regmap_update_bits to regmap_write_bits. when clear bit is already 1, regmap_update_bits can not write 1 to it again. Some IC has the feature that, when set bit is 1, the clear bit change to 1 together. It will truly clear bit to 0 by write 1 to the clear bit Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index a2635c2..5a8ec8f 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /** @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + ti_syscon_reset_assert(rcdev, id); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, .status = ti_syscon_reset_status, + .reset = ti_syscon_reset, }; static int ti_syscon_reset_probe(struct platform_device *pdev) -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 748E6C433E0 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ti_syscon_reset() to integrate assert and deassert together, and change return value of the reset assert and deassert interface from regmap_update_bits to regmap_write_bits. when clear bit is already 1, regmap_update_bits can not write 1 to it again. Some IC has the feature that, when set bit is 1, the clear bit change to 1 together. It will truly clear bit to 0 by write 1 to the clear bit Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index a2635c2..5a8ec8f 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /** @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + ti_syscon_reset_assert(rcdev, id); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, .status = ti_syscon_reset_status, + .reset = ti_syscon_reset, }; static int ti_syscon_reset_probe(struct platform_device *pdev) -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D768BC433E1 for ; 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X-UUID: b124722788254b7490b25b97e4daac44-20200729 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 543757748; Wed, 29 Jul 2020 15:39:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 15:39:44 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 15:39:45 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface Date: Wed, 29 Jul 2020 15:39:16 +0800 Message-ID: <1596008357-11213-2-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> References: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org QWRkIHRpX3N5c2Nvbl9yZXNldCgpIHRvIGludGVncmF0ZSBhc3NlcnQgYW5kIGRlYXNzZXJ0IHRv Z2V0aGVyLA0KYW5kIGNoYW5nZSByZXR1cm4gdmFsdWUgb2YgdGhlIHJlc2V0IGFzc2VydCBhbmQg ZGVhc3NlcnQgaW50ZXJmYWNlDQpmcm9tIHJlZ21hcF91cGRhdGVfYml0cyB0byByZWdtYXBfd3Jp dGVfYml0cy4NCg0Kd2hlbiBjbGVhciBiaXQgaXMgYWxyZWFkeSAxLCByZWdtYXBfdXBkYXRlX2Jp dHMgY2FuIG5vdCB3cml0ZSAxIHRvIGl0IGFnYWluLg0KU29tZSBJQyBoYXMgdGhlIGZlYXR1cmUg dGhhdCwgd2hlbiBzZXQgYml0IGlzIDEsIHRoZSBjbGVhciBiaXQgY2hhbmdlDQp0byAxIHRvZ2V0 aGVyLiBJdCB3aWxsIHRydWx5IGNsZWFyIGJpdCB0byAwIGJ5IHdyaXRlIDEgdG8gdGhlIGNsZWFy IGJpdA0KDQpTaWduZWQtb2ZmLWJ5OiBDcnlzdGFsIEd1byA8Y3J5c3RhbC5ndW9AbWVkaWF0ZWsu Y29tPg0KLS0tDQogZHJpdmVycy9yZXNldC9yZXNldC10aS1zeXNjb24uYyB8IDEzICsrKysrKysr KysrLS0NCiAxIGZpbGUgY2hhbmdlZCwgMTEgaW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkN Cg0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvcmVzZXQvcmVzZXQtdGktc3lzY29uLmMgYi9kcml2ZXJz L3Jlc2V0L3Jlc2V0LXRpLXN5c2Nvbi5jDQppbmRleCBhMjYzNWMyLi41YThlYzhmIDEwMDY0NA0K LS0tIGEvZHJpdmVycy9yZXNldC9yZXNldC10aS1zeXNjb24uYw0KKysrIGIvZHJpdmVycy9yZXNl dC9yZXNldC10aS1zeXNjb24uYw0KQEAgLTg5LDcgKzg5LDcgQEAgc3RhdGljIGludCB0aV9zeXNj b25fcmVzZXRfYXNzZXJ0KHN0cnVjdCByZXNldF9jb250cm9sbGVyX2RldiAqcmNkZXYsDQogCW1h c2sgPSBCSVQoY29udHJvbC0+YXNzZXJ0X2JpdCk7DQogCXZhbHVlID0gKGNvbnRyb2wtPmZsYWdz ICYgQVNTRVJUX1NFVCkgPyBtYXNrIDogMHgwOw0KIA0KLQlyZXR1cm4gcmVnbWFwX3VwZGF0ZV9i aXRzKGRhdGEtPnJlZ21hcCwgY29udHJvbC0+YXNzZXJ0X29mZnNldCwgbWFzaywgdmFsdWUpOw0K KwlyZXR1cm4gcmVnbWFwX3dyaXRlX2JpdHMoZGF0YS0+cmVnbWFwLCBjb250cm9sLT5hc3NlcnRf b2Zmc2V0LCBtYXNrLCB2YWx1ZSk7DQogfQ0KIA0KIC8qKg0KQEAgLTEyMCw3ICsxMjAsNyBAQCBz dGF0aWMgaW50IHRpX3N5c2Nvbl9yZXNldF9kZWFzc2VydChzdHJ1Y3QgcmVzZXRfY29udHJvbGxl cl9kZXYgKnJjZGV2LA0KIAltYXNrID0gQklUKGNvbnRyb2wtPmRlYXNzZXJ0X2JpdCk7DQogCXZh bHVlID0gKGNvbnRyb2wtPmZsYWdzICYgREVBU1NFUlRfU0VUKSA/IG1hc2sgOiAweDA7DQogDQot CXJldHVybiByZWdtYXBfdXBkYXRlX2JpdHMoZGF0YS0+cmVnbWFwLCBjb250cm9sLT5kZWFzc2Vy dF9vZmZzZXQsIG1hc2ssIHZhbHVlKTsNCisJcmV0dXJuIHJlZ21hcF93cml0ZV9iaXRzKGRhdGEt PnJlZ21hcCwgY29udHJvbC0+ZGVhc3NlcnRfb2Zmc2V0LCBtYXNrLCB2YWx1ZSk7DQogfQ0KIA0K IC8qKg0KQEAgLTE1OCwxMCArMTU4LDE5IEBAIHN0YXRpYyBpbnQgdGlfc3lzY29uX3Jlc2V0X3N0 YXR1cyhzdHJ1Y3QgcmVzZXRfY29udHJvbGxlcl9kZXYgKnJjZGV2LA0KIAkJIShjb250cm9sLT5m bGFncyAmIFNUQVRVU19TRVQpOw0KIH0NCiANCitzdGF0aWMgaW50IHRpX3N5c2Nvbl9yZXNldChz dHJ1Y3QgcmVzZXRfY29udHJvbGxlcl9kZXYgKnJjZGV2LA0KKwkJCSAgIHVuc2lnbmVkIGxvbmcg aWQpDQorew0KKwl0aV9zeXNjb25fcmVzZXRfYXNzZXJ0KHJjZGV2LCBpZCk7DQorDQorCXJldHVy biB0aV9zeXNjb25fcmVzZXRfZGVhc3NlcnQocmNkZXYsIGlkKTsNCit9DQorDQogc3RhdGljIGNv bnN0IHN0cnVjdCByZXNldF9jb250cm9sX29wcyB0aV9zeXNjb25fcmVzZXRfb3BzID0gew0KIAku YXNzZXJ0CQk9IHRpX3N5c2Nvbl9yZXNldF9hc3NlcnQsDQogCS5kZWFzc2VydAk9IHRpX3N5c2Nv bl9yZXNldF9kZWFzc2VydCwNCiAJLnN0YXR1cwkJPSB0aV9zeXNjb25fcmVzZXRfc3RhdHVzLA0K KwkucmVzZXQJCT0gdGlfc3lzY29uX3Jlc2V0LA0KIH07DQogDQogc3RhdGljIGludCB0aV9zeXNj b25fcmVzZXRfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCi0tIA0KMS44LjEu MS5kaXJ0eQ0K