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Wed, 29 Jul 2020 22:27:52 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 23:27:48 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 14:27:46 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 14:27:45 +0800 Message-ID: <1596090441.11360.27.camel@mhfsdcap03> Subject: Re: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface From: Crystal Guo To: Philipp Zabel Date: Thu, 30 Jul 2020 14:27:21 +0800 In-Reply-To: References: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> <1596008357-11213-2-git-send-email-crystal.guo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_022759_026978_5A3E1C20 X-CRM114-Status: GOOD ( 32.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , fan.chen@mediatek.com, "robh+dt@kernel.org" , "linux-mediatek@lists.infradead.org" , Matthias Brugger , yingjoe.chen@mediatek.com, stanley.chu@mediatek.com, "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-07-29 at 16:02 +0800, Philipp Zabel wrote: > Hi Crystal, Matthias, > > On Wed, 2020-07-29 at 09:48 +0200, Matthias Brugger wrote: > > > > On 29/07/2020 09:39, Crystal Guo wrote: > > > Add ti_syscon_reset() to integrate assert and deassert together, > > > and change return value of the reset assert and deassert interface > > > from regmap_update_bits to regmap_write_bits. > > > > > > when clear bit is already 1, regmap_update_bits can not write 1 to it again. > > > Some IC has the feature that, when set bit is 1, the clear bit change > > > to 1 together. It will truly clear bit to 0 by write 1 to the clear bit > > > > > > Signed-off-by: Crystal Guo > > > --- > > > drivers/reset/reset-ti-syscon.c | 13 +++++++++++-- > > > 1 file changed, 11 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c > > > index a2635c2..5a8ec8f 100644 > > > --- a/drivers/reset/reset-ti-syscon.c > > > +++ b/drivers/reset/reset-ti-syscon.c > > > @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, > > > mask = BIT(control->assert_bit); > > > value = (control->flags & ASSERT_SET) ? mask : 0x0; > > > > > > - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); > > > + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); > > > > Nack, this will break the driver for the other devices. > > I don't think this will break the driver for existing hardware. > regmap_write_bits() is the same as regmap_update_bits(), it just forces > the write in case the read already happens to return the correct value. > Of course it would be good to check that this actually works. Yes, regmap_write_bits() is the same as regmap_update_bits(), it would not affect existed users. Or should I use a property to separate regmap_write_bits() and regmap_update_bits() ? > > > The kernel has to work not just for your SoC but for all devices of all > > architectures. You can't just hack something up, that will work on your specific > > SoC. > > > > Regards, > > Matthias > > This TI driver was intend to be a generic reset controller (https://lore.kernel.org/patchwork/cover/683585/), so this patch may not just work on a specific SoC. Thanks, Crystal > > > } > > > > > > /** > > > @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, > > > mask = BIT(control->deassert_bit); > > > value = (control->flags & DEASSERT_SET) ? mask : 0x0; > > > > > > - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); > > > + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); > > > } > > > > > > /** > > > @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, > > > !(control->flags & STATUS_SET); > > > } > > > > > > +static int ti_syscon_reset(struct reset_controller_dev *rcdev, > > > + unsigned long id) > > > +{ > > > + ti_syscon_reset_assert(rcdev, id); > > > + > > > + return ti_syscon_reset_deassert(rcdev, id); > > > +} > > > + > > I'm unsure about this one, though. This is an incompatible change. At > the very least this would have to be optional depending on compatible. > > regards > Philipp I will add a property to make this change be optional, thanks for you advice. Thanks, Crystal _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81B74C433DF for ; Thu, 30 Jul 2020 06:29:59 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E5502075F for ; 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bh=8lty/uyzCDwACFd7jNKNUuVqC+GMWXy2t8oEvgAMM2Q=; b=qfsWkCdWlfL0cl4OTeF8Cz8oj5cetDwwD1bIqxQrWEWGKwI3CxNw5KXV00UT2cVSNFSCljEzCzF7cYIdDePPJIxyFeJsNh8TizXx9roZ4zSzPcjFdqV2tfhA/rMgBnCK7DbubVDn6AvypnvoCZ1XtcQQ1uu+Nlglbho09RCIqdQ=; X-UUID: f79a17b8a20d417aabe641e183539a71-20200729 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 741957506; Wed, 29 Jul 2020 22:27:52 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 23:27:48 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 14:27:46 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 14:27:45 +0800 Message-ID: <1596090441.11360.27.camel@mhfsdcap03> Subject: Re: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface From: Crystal Guo To: Philipp Zabel Date: Thu, 30 Jul 2020 14:27:21 +0800 In-Reply-To: References: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> <1596008357-11213-2-git-send-email-crystal.guo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_022759_026978_5A3E1C20 X-CRM114-Status: GOOD ( 32.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , fan.chen@mediatek.com, "robh+dt@kernel.org" , "linux-mediatek@lists.infradead.org" , Matthias Brugger , yingjoe.chen@mediatek.com, stanley.chu@mediatek.com, "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-07-29 at 16:02 +0800, Philipp Zabel wrote: > Hi Crystal, Matthias, > > On Wed, 2020-07-29 at 09:48 +0200, Matthias Brugger wrote: > > > > On 29/07/2020 09:39, Crystal Guo wrote: > > > Add ti_syscon_reset() to integrate assert and deassert together, > > > and change return value of the reset assert and deassert interface > > > from regmap_update_bits to regmap_write_bits. > > > > > > when clear bit is already 1, regmap_update_bits can not write 1 to it again. > > > Some IC has the feature that, when set bit is 1, the clear bit change > > > to 1 together. It will truly clear bit to 0 by write 1 to the clear bit > > > > > > Signed-off-by: Crystal Guo > > > --- > > > drivers/reset/reset-ti-syscon.c | 13 +++++++++++-- > > > 1 file changed, 11 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c > > > index a2635c2..5a8ec8f 100644 > > > --- a/drivers/reset/reset-ti-syscon.c > > > +++ b/drivers/reset/reset-ti-syscon.c > > > @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, > > > mask = BIT(control->assert_bit); > > > value = (control->flags & ASSERT_SET) ? mask : 0x0; > > > > > > - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); > > > + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); > > > > Nack, this will break the driver for the other devices. > > I don't think this will break the driver for existing hardware. > regmap_write_bits() is the same as regmap_update_bits(), it just forces > the write in case the read already happens to return the correct value. > Of course it would be good to check that this actually works. Yes, regmap_write_bits() is the same as regmap_update_bits(), it would not affect existed users. Or should I use a property to separate regmap_write_bits() and regmap_update_bits() ? > > > The kernel has to work not just for your SoC but for all devices of all > > architectures. You can't just hack something up, that will work on your specific > > SoC. > > > > Regards, > > Matthias > > This TI driver was intend to be a generic reset controller (https://lore.kernel.org/patchwork/cover/683585/), so this patch may not just work on a specific SoC. Thanks, Crystal > > > } > > > > > > /** > > > @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, > > > mask = BIT(control->deassert_bit); > > > value = (control->flags & DEASSERT_SET) ? mask : 0x0; > > > > > > - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); > > > + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); > > > } > > > > > > /** > > > @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, > > > !(control->flags & STATUS_SET); > > > } > > > > > > +static int ti_syscon_reset(struct reset_controller_dev *rcdev, > > > + unsigned long id) > > > +{ > > > + ti_syscon_reset_assert(rcdev, id); > > > + > > > + return ti_syscon_reset_deassert(rcdev, id); > > > +} > > > + > > I'm unsure about this one, though. This is an incompatible change. At > the very least this would have to be optional depending on compatible. > > regards > Philipp I will add a property to make this change be optional, thanks for you advice. Thanks, Crystal _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 114F7C433E0 for ; Thu, 30 Jul 2020 06:27:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E17232075F for ; Thu, 30 Jul 2020 06:27:55 +0000 (UTC) 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Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1567981899; Thu, 30 Jul 2020 14:27:50 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 14:27:46 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 14:27:45 +0800 Message-ID: <1596090441.11360.27.camel@mhfsdcap03> Subject: Re: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface From: Crystal Guo To: Philipp Zabel CC: Matthias Brugger , "robh+dt@kernel.org" , srv_heupstream , "linux-mediatek@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , , , Date: Thu, 30 Jul 2020 14:27:21 +0800 In-Reply-To: References: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> <1596008357-11213-2-git-send-email-crystal.guo@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gV2VkLCAyMDIwLTA3LTI5IGF0IDE2OjAyICswODAwLCBQaGlsaXBwIFphYmVsIHdyb3RlOg0K PiBIaSBDcnlzdGFsLCBNYXR0aGlhcywNCj4gDQo+IE9uIFdlZCwgMjAyMC0wNy0yOSBhdCAwOTo0 OCArMDIwMCwgTWF0dGhpYXMgQnJ1Z2dlciB3cm90ZToNCj4gPiANCj4gPiBPbiAyOS8wNy8yMDIw IDA5OjM5LCBDcnlzdGFsIEd1byB3cm90ZToNCj4gPiA+IEFkZCB0aV9zeXNjb25fcmVzZXQoKSB0 byBpbnRlZ3JhdGUgYXNzZXJ0IGFuZCBkZWFzc2VydCB0b2dldGhlciwNCj4gPiA+IGFuZCBjaGFu Z2UgcmV0dXJuIHZhbHVlIG9mIHRoZSByZXNldCBhc3NlcnQgYW5kIGRlYXNzZXJ0IGludGVyZmFj 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