From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CA0DC433DF for ; Thu, 30 Jul 2020 13:30:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 418C220838 for ; Thu, 30 Jul 2020 13:30:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XMWn1nPr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729145AbgG3Nah (ORCPT ); Thu, 30 Jul 2020 09:30:37 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:64199 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727883AbgG3Nad (ORCPT ); Thu, 30 Jul 2020 09:30:33 -0400 X-UUID: 1bb320a6777149d7be1e67de3b4b7a3b-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EFC4xeBmcmvSxTLCFwKXro7Tw1yoAmDYNXqQcPM0FLA=; b=XMWn1nPrlnPm3Ypivb4SjgaNtNr/YlM9B/Qd2aNwN6jlkrseoOavr6e77QUOAUP8bkSFlYxklphwrf2wHSKzhHJ3L0/Ii4bw6715bP2QFpSaEhxzNK2y01j8yOc7EDWwTimbXsWSy/mlVcL9PbEQzRsl6dyvZmkBswqfUty6Mdk=; X-UUID: 1bb320a6777149d7be1e67de3b4b7a3b-20200730 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 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X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org dGhpcyBhZGRzIGluaXRpYWwgTVQ2Nzc5IGR0cyBzZXR0aW5ncyBmb3IgYm9hcmQgc3VwcG9ydCwN CmluY2x1ZGluZyBjcHUsIGdpYywgdGltZXIsIGNjZiwgcGluY3RybCwgdWFydCwgc3lzaXJxLi4u ZXRjLg0KDQpTaWduZWQtb2ZmLWJ5OiBIYW5rcyBDaGVuIDxoYW5rcy5jaGVuQG1lZGlhdGVrLmNv bT4NCi0tLQ0KIGFyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvTWFrZWZpbGUgICAgICAgfCAg IDEgKw0KIGFyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ2Nzc5LWV2Yi5kdHMgfCAgMzEg KysrDQogYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDY3NzkuZHRzaSAgICB8IDI3MSAr KysrKysrKysrKysrKysrKysrKw0KIDMgZmlsZXMgY2hhbmdlZCwgMzAzIGluc2VydGlvbnMoKykN CiBjcmVhdGUgbW9kZSAxMDA2NDQgYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDY3Nzkt ZXZiLmR0cw0KIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVr L210Njc3OS5kdHNpDQoNCmRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVr L01ha2VmaWxlIGIvYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9NYWtlZmlsZQ0KaW5kZXgg YTU3YWY5ZGE5ZjVjLi40ZDFiMGY5ZDhkMWMgMTAwNjQ0DQotLS0gYS9hcmNoL2FybTY0L2Jvb3Qv ZHRzL21lZGlhdGVrL01ha2VmaWxlDQorKysgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVr L01ha2VmaWxlDQpAQCAtMSw2ICsxLDcgQEANCiAjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBH UEwtMi4wDQogZHRiLSQoQ09ORklHX0FSQ0hfTUVESUFURUspICs9IG10MjcxMi1ldmIuZHRiDQog ZHRiLSQoQ09ORklHX0FSQ0hfTUVESUFURUspICs9IG10Njc1NS1ldmIuZHRiDQorZHRiLSQoQ09O RklHX0FSQ0hfTUVESUFURUspICs9IG10Njc3OS1ldmIuZHRiDQogZHRiLSQoQ09ORklHX0FSQ0hf TUVESUFURUspICs9IG10Njc5NS1ldmIuZHRiDQogZHRiLSQoQ09ORklHX0FSQ0hfTUVESUFURUsp ICs9IG10Njc5Ny1ldmIuZHRiDQogZHRiLSQoQ09ORklHX0FSQ0hfTUVESUFURUspICs9IG10Njc5 Ny14MjAtZGV2LmR0Yg0KZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsv bXQ2Nzc5LWV2Yi5kdHMgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210Njc3OS1ldmIu ZHRzDQpuZXcgZmlsZSBtb2RlIDEwMDY0NA0KaW5kZXggMDAwMDAwMDAwMDAwLi4xNjRmNWNiYjM4 MjENCi0tLSAvZGV2L251bGwNCisrKyBiL2FyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ2 Nzc5LWV2Yi5kdHMNCkBAIC0wLDAgKzEsMzEgQEANCisvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmll cjogR1BMLTIuMCsNCisvKg0KKyAqIENvcHlyaWdodCAoYykgMjAxOSBNZWRpYVRlayBJbmMuDQor ICogQXV0aG9yOiBNYXJzLkMgPG1hcnMuY2hlbmdAbWVkaWF0ZWsuY29tPg0KKyAqDQorICovDQor DQorL2R0cy12MS87DQorI2luY2x1ZGUgIm10Njc3OS5kdHNpIg0KKw0KKy8gew0KKwltb2RlbCA9 ICJNZWRpYVRlayBNVDY3NzkgRVZCIjsNCisJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDY3Nzkt ZXZiIiwgIm1lZGlhdGVrLG10Njc3OSI7DQorDQorCWFsaWFzZXMgew0KKwkJc2VyaWFsMCA9ICZ1 YXJ0MDsNCisJfTsNCisNCisJbWVtb3J5QDQwMDAwMDAwIHsNCisJCWRldmljZV90eXBlID0gIm1l bW9yeSI7DQorCQlyZWcgPSA8MCAweDQwMDAwMDAwIDAgMHgxZTgwMDAwMD47DQorCX07DQorDQor CWNob3NlbiB7DQorCQlzdGRvdXQtcGF0aCA9ICJzZXJpYWwwOjkyMTYwMG44IjsNCisJfTsNCit9 Ow0KKw0KKyZ1YXJ0MCB7DQorCXN0YXR1cyA9ICJva2F5IjsNCit9Ow0KZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ2Nzc5LmR0c2kgYi9hcmNoL2FybTY0L2Jvb3Qv ZHRzL21lZGlhdGVrL210Njc3OS5kdHNpDQpuZXcgZmlsZSBtb2RlIDEwMDY0NA0KaW5kZXggMDAw MDAwMDAwMDAwLi4zNzBmMzA5ZDMyZGUNCi0tLSAvZGV2L251bGwNCisrKyBiL2FyY2gvYXJtNjQv Ym9vdC9kdHMvbWVkaWF0ZWsvbXQ2Nzc5LmR0c2kNCkBAIC0wLDAgKzEsMjcxIEBADQorLy8gU1BE WC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjArDQorLyoNCisgKiBDb3B5cmlnaHQgKGMpIDIw MTkgTWVkaWFUZWsgSW5jLg0KKyAqIEF1dGhvcjogTWFycy5DIDxtYXJzLmNoZW5nQG1lZGlhdGVr LmNvbT4NCisgKg0KKyAqLw0KKw0KKyNpbmNsdWRlIDxkdC1iaW5kaW5ncy9jbG9jay9tdDY3Nzkt Y2xrLmg+DQorI2luY2x1ZGUgPGR0LWJpbmRpbmdzL2ludGVycnVwdC1jb250cm9sbGVyL2lycS5o Pg0KKyNpbmNsdWRlIDxkdC1iaW5kaW5ncy9pbnRlcnJ1cHQtY29udHJvbGxlci9hcm0tZ2ljLmg+ DQorI2luY2x1ZGUgPGR0LWJpbmRpbmdzL3BpbmN0cmwvbXQ2Nzc5LXBpbmZ1bmMuaD4NCisNCisv IHsNCisJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDY3NzkiOw0KKwlpbnRlcnJ1cHQtcGFyZW50 ID0gPCZzeXNpcnE+Ow0KKwkjYWRkcmVzcy1jZWxscyA9IDwyPjsNCisJI3NpemUtY2VsbHMgPSA8 Mj47DQorDQorCXBzY2kgew0KKwkJY29tcGF0aWJsZSA9ICJhcm0scHNjaS0wLjIiOw0KKwkJbWV0 aG9kID0gInNtYyI7DQorCX07DQorDQorCWNwdXMgew0KKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47 DQorCQkjc2l6ZS1jZWxscyA9IDwwPjsNCisNCisJCWNwdTA6IGNwdUAwIHsNCisJCQlkZXZpY2Vf dHlwZSA9ICJjcHUiOw0KKwkJCWNvbXBhdGlibGUgPSAiYXJtLGNvcnRleC1hNTUiOw0KKwkJCWVu YWJsZS1tZXRob2QgPSAicHNjaSI7DQorCQkJcmVnID0gPDB4MDAwPjsNCisJCX07DQorDQorCQlj cHUxOiBjcHVAMSB7DQorCQkJZGV2aWNlX3R5cGUgPSAiY3B1IjsNCisJCQljb21wYXRpYmxlID0g ImFybSxjb3J0ZXgtYTU1IjsNCisJCQllbmFibGUtbWV0aG9kID0gInBzY2kiOw0KKwkJCXJlZyA9 IDwweDEwMD47DQorCQl9Ow0KKw0KKwkJY3B1MjogY3B1QDIgew0KKwkJCWRldmljZV90eXBlID0g ImNwdSI7DQorCQkJY29tcGF0aWJsZSA9ICJhcm0sY29ydGV4LWE1NSI7DQorCQkJZW5hYmxlLW1l dGhvZCA9ICJwc2NpIjsNCisJCQlyZWcgPSA8MHgyMDA+Ow0KKwkJfTsNCisNCisJCWNwdTM6IGNw dUAzIHsNCisJCQlkZXZpY2VfdHlwZSA9ICJjcHUiOw0KKwkJCWNvbXBhdGlibGUgPSAiYXJtLGNv cnRleC1hNTUiOw0KKwkJCWVuYWJsZS1tZXRob2QgPSAicHNjaSI7DQorCQkJcmVnID0gPDB4MzAw PjsNCisJCX07DQorDQorCQljcHU0OiBjcHVANCB7DQorCQkJZGV2aWNlX3R5cGUgPSAiY3B1IjsN CisJCQljb21wYXRpYmxlID0gImFybSxjb3J0ZXgtYTU1IjsNCisJCQllbmFibGUtbWV0aG9kID0g InBzY2kiOw0KKwkJCXJlZyA9IDwweDQwMD47DQorCQl9Ow0KKw0KKwkJY3B1NTogY3B1QDUgew0K KwkJCWRldmljZV90eXBlID0gImNwdSI7DQorCQkJY29tcGF0aWJsZSA9ICJhcm0sY29ydGV4LWE1 NSI7DQorCQkJZW5hYmxlLW1ldGhvZCA9ICJwc2NpIjsNCisJCQlyZWcgPSA8MHg1MDA+Ow0KKwkJ fTsNCisNCisJCWNwdTY6IGNwdUA2IHsNCisJCQlkZXZpY2VfdHlwZSA9ICJjcHUiOw0KKwkJCWNv bXBhdGlibGUgPSAiYXJtLGNvcnRleC1hNzUiOw0KKwkJCWVuYWJsZS1tZXRob2QgPSAicHNjaSI7 DQorCQkJcmVnID0gPDB4NjAwPjsNCisJCX07DQorDQorCQljcHU3OiBjcHVANyB7DQorCQkJZGV2 aWNlX3R5cGUgPSAiY3B1IjsNCisJCQljb21wYXRpYmxlID0gImFybSxjb3J0ZXgtYTc1IjsNCisJ CQllbmFibGUtbWV0aG9kID0gInBzY2kiOw0KKwkJCXJlZyA9IDwweDcwMD47DQorCQl9Ow0KKwl9 Ow0KKw0KKwlwbXUgew0KKwkJY29tcGF0aWJsZSA9ICJhcm0sYXJtdjgtcG11djMiOw0KKwkJaW50 ZXJydXB0LXBhcmVudCA9IDwmZ2ljPjsNCisJCWludGVycnVwdHMgPSA8R0lDX1BQSSA3IElSUV9U WVBFX0xFVkVMX0xPVyAwPjsNCisJfTsNCisNCisJY2xrMjZtOiBvc2NpbGxhdG9yQDAgew0KKwkJ Y29tcGF0aWJsZSA9ICJmaXhlZC1jbG9jayI7DQorCQkjY2xvY2stY2VsbHMgPSA8MD47DQorCQlj bG9jay1mcmVxdWVuY3kgPSA8MjYwMDAwMDA+Ow0KKwkJY2xvY2stb3V0cHV0LW5hbWVzID0gImNs azI2bSI7DQorCX07DQorDQorCWNsazMyazogb3NjaWxsYXRvckAxIHsNCisJCWNvbXBhdGlibGUg PSAiZml4ZWQtY2xvY2siOw0KKwkJI2Nsb2NrLWNlbGxzID0gPDA+Ow0KKwkJY2xvY2stZnJlcXVl bmN5ID0gPDMyNzY4PjsNCisJCWNsb2NrLW91dHB1dC1uYW1lcyA9ICJjbGszMmsiOw0KKwl9Ow0K Kw0KKwl0aW1lciB7DQorCQljb21wYXRpYmxlID0gImFybSxhcm12OC10aW1lciI7DQorCQlpbnRl cnJ1cHQtcGFyZW50ID0gPCZnaWM+Ow0KKwkJaW50ZXJydXB0cyA9IDxHSUNfUFBJIDEzIElSUV9U WVBFX0xFVkVMX0xPVyAwPiwNCisJCQkgICAgIDxHSUNfUFBJIDE0IElSUV9UWVBFX0xFVkVMX0xP VyAwPiwNCisJCQkgICAgIDxHSUNfUFBJIDExIElSUV9UWVBFX0xFVkVMX0xPVyAwPiwNCisJCQkg ICAgIDxHSUNfUFBJIDEwIElSUV9UWVBFX0xFVkVMX0xPVyAwPjsNCisJfTsNCisNCisJc29jIHsN CisJCSNhZGRyZXNzLWNlbGxzID0gPDI+Ow0KKwkJI3NpemUtY2VsbHMgPSA8Mj47DQorCQljb21w YXRpYmxlID0gInNpbXBsZS1idXMiOw0KKwkJcmFuZ2VzOw0KKw0KKwkJZ2ljOiBpbnRlcnJ1cHQt Y29udHJvbGxlckAwYzAwMDAwMCB7DQorCQkJY29tcGF0aWJsZSA9ICJhcm0sZ2ljLXYzIjsNCisJ CQkjaW50ZXJydXB0LWNlbGxzID0gPDQ+Ow0KKwkJCWludGVycnVwdC1wYXJlbnQgPSA8JmdpYz47 DQorCQkJaW50ZXJydXB0LWNvbnRyb2xsZXI7DQorCQkJcmVnID0gPDAgMHgwYzAwMDAwMCAwIDB4 NDAwMDA+LCAgLyogR0lDRCAqLw0KKwkJCSAgICAgIDwwIDB4MGMwNDAwMDAgMCAweDIwMDAwMD47 IC8qIEdJQ1IgKi8NCisJCQlpbnRlcnJ1cHRzID0gPEdJQ19QUEkgOSBJUlFfVFlQRV9MRVZFTF9I SUdIIDA+Ow0KKw0KKwkJCXBwaS1wYXJ0aXRpb25zIHsNCisJCQkJcHBpX2NsdXN0ZXIwOiBpbnRl cnJ1cHQtcGFydGl0aW9uLTAgew0KKwkJCQkJYWZmaW5pdHkgPSA8JmNwdTAgJmNwdTEgXA0KKwkJ CQkJCSZjcHUyICZjcHUzICZjcHU0ICZjcHU1PjsNCisJCQkJfTsNCisJCQkJcHBpX2NsdXN0ZXIx OiBpbnRlcnJ1cHQtcGFydGl0aW9uLTEgew0KKwkJCQkJYWZmaW5pdHkgPSA8JmNwdTYgJmNwdTc+ Ow0KKwkJCQl9Ow0KKwkJCX07DQorDQorCQl9Ow0KKw0KKwkJc3lzaXJxOiBpbnRwb2wtY29udHJv bGxlckAwYzUzYTY1MCB7DQorCQkJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDY3Nzktc3lzaXJx IiwNCisJCQkJICAgICAibWVkaWF0ZWssbXQ2NTc3LXN5c2lycSI7DQorCQkJaW50ZXJydXB0LWNv bnRyb2xsZXI7DQorCQkJI2ludGVycnVwdC1jZWxscyA9IDwzPjsNCisJCQlpbnRlcnJ1cHQtcGFy ZW50ID0gPCZnaWM+Ow0KKwkJCXJlZyA9IDwwIDB4MGM1M2E2NTAgMCAweDUwPjsNCisJCX07DQor DQorCQl0b3Bja2dlbjogY2xvY2stY29udHJvbGxlckAxMDAwMDAwMCB7DQorCQkJY29tcGF0aWJs ZSA9ICJtZWRpYXRlayxtdDY3NzktdG9wY2tnZW4iLCAic3lzY29uIjsNCisJCQlyZWcgPSA8MCAw eDEwMDAwMDAwIDAgMHgxMDAwPjsNCisJCQkjY2xvY2stY2VsbHMgPSA8MT47DQorCQl9Ow0KKw0K KwkJaW5mcmFjZmdfYW86IGNsb2NrLWNvbnRyb2xsZXJAMTAwMDEwMDAgew0KKwkJCWNvbXBhdGli bGUgPSAibWVkaWF0ZWssbXQ2Nzc5LWluZnJhY2ZnX2FvIiwgInN5c2NvbiI7DQorCQkJcmVnID0g PDAgMHgxMDAwMTAwMCAwIDB4MTAwMD47DQorCQkJI2Nsb2NrLWNlbGxzID0gPDE+Ow0KKwkJfTsN CisNCisJCXBpbzogcGluY3RybEAxMDAwNTAwMCB7DQorCQkJY29tcGF0aWJsZSA9ICJtZWRpYXRl ayxtdDY3NzktcGluY3RybCIsICJzeXNjb24iOw0KKwkJCXJlZyA9IDwwIDB4MTAwMDUwMDAgMCAw eDEwMDA+LA0KKwkJCSAgICAgIDwwIDB4MTFjMjAwMDAgMCAweDEwMDA+LA0KKwkJCSAgICAgIDww IDB4MTFkMTAwMDAgMCAweDEwMDA+LA0KKwkJCSAgICAgIDwwIDB4MTFlMjAwMDAgMCAweDEwMDA+ LA0KKwkJCSAgICAgIDwwIDB4MTFlNzAwMDAgMCAweDEwMDA+LA0KKwkJCSAgICAgIDwwIDB4MTFl YTAwMDAgMCAweDEwMDA+LA0KKwkJCSAgICAgIDwwIDB4MTFmMjAwMDAgMCAweDEwMDA+LA0KKwkJ CSAgICAgIDwwIDB4MTFmMzAwMDAgMCAweDEwMDA+LA0KKwkJCSAgICAgIDwwIDB4MTAwMGIwMDAg MCAweDEwMDA+Ow0KKwkJCXJlZy1uYW1lcyA9ICJncGlvIiwgImlvY2ZnX3JtIiwNCisJCQkJICAg ICJpb2NmZ19iciIsICJpb2NmZ19sbSIsDQorCQkJCSAgICAiaW9jZmdfbGIiLCAiaW9jZmdfcnQi LA0KKwkJCQkgICAgImlvY2ZnX2x0IiwgImlvY2ZnX3RsIiwNCisJCQkJICAgICJlaW50IjsNCisJ CQlncGlvLWNvbnRyb2xsZXI7DQorCQkJI2dwaW8tY2VsbHMgPSA8Mj47DQorCQkJZ3Bpby1yYW5n ZXMgPSA8JnBpbyAwIDAgMjEwPjsNCisJCQlpbnRlcnJ1cHQtY29udHJvbGxlcjsNCisJCQkjaW50 ZXJydXB0LWNlbGxzID0gPDI+Ow0KKwkJCWludGVycnVwdHMgPSA8R0lDX1NQSSAyMDQgSVJRX1RZ UEVfTEVWRUxfSElHSD47DQorCQl9Ow0KKw0KKwkJYXBtaXhlZDogY2xvY2stY29udHJvbGxlckAx MDAwYzAwMCB7DQorCQkJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDY3NzktYXBtaXhlZCIsICJz eXNjb24iOw0KKwkJCXJlZyA9IDwwIDB4MTAwMGMwMDAgMCAweGUwMD47DQorCQkJI2Nsb2NrLWNl bGxzID0gPDE+Ow0KKwkJfTsNCisNCisJCXVhcnQwOiBzZXJpYWxAMTEwMDIwMDAgew0KKwkJCWNv bXBhdGlibGUgPSAibWVkaWF0ZWssbXQ2Nzc5LXVhcnQiLA0KKwkJCQkgICAgICJtZWRpYXRlayxt dDY1NzctdWFydCI7DQorCQkJcmVnID0gPDAgMHgxMTAwMjAwMCAwIDB4NDAwPjsNCisJCQlpbnRl cnJ1cHRzID0gPEdJQ19TUEkgMTE1IElSUV9UWVBFX0xFVkVMX0xPVz47DQorCQkJY2xvY2tzID0g PCZjbGsyNm0+LCA8JmluZnJhY2ZnX2FvIENMS19JTkZSQV9VQVJUMD47DQorCQkJY2xvY2stbmFt ZXMgPSAiYmF1ZCIsICJidXMiOw0KKwkJCXN0YXR1cyA9ICJkaXNhYmxlZCI7DQorCQl9Ow0KKw0K KwkJdWFydDE6IHNlcmlhbEAxMTAwMzAwMCB7DQorCQkJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxt dDY3NzktdWFydCIsDQorCQkJCSAgICAgIm1lZGlhdGVrLG10NjU3Ny11YXJ0IjsNCisJCQlyZWcg PSA8MCAweDExMDAzMDAwIDAgMHg0MDA+Ow0KKwkJCWludGVycnVwdHMgPSA8R0lDX1NQSSAxMTYg SVJRX1RZUEVfTEVWRUxfTE9XPjsNCisJCQljbG9ja3MgPSA8JmNsazI2bT4sIDwmaW5mcmFjZmdf YW8gQ0xLX0lORlJBX1VBUlQxPjsNCisJCQljbG9jay1uYW1lcyA9ICJiYXVkIiwgImJ1cyI7DQor CQkJc3RhdHVzID0gImRpc2FibGVkIjsNCisJCX07DQorDQorCQl1YXJ0Mjogc2VyaWFsQDExMDA0 MDAwIHsNCisJCQljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10Njc3OS11YXJ0IiwNCisJCQkJICAg ICAibWVkaWF0ZWssbXQ2NTc3LXVhcnQiOw0KKwkJCXJlZyA9IDwwIDB4MTEwMDQwMDAgMCAweDQw MD47DQorCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDExNyBJUlFfVFlQRV9MRVZFTF9MT1c+Ow0K KwkJCWNsb2NrcyA9IDwmY2xrMjZtPiwgPCZpbmZyYWNmZ19hbyBDTEtfSU5GUkFfVUFSVDI+Ow0K KwkJCWNsb2NrLW5hbWVzID0gImJhdWQiLCAiYnVzIjsNCisJCQlzdGF0dXMgPSAiZGlzYWJsZWQi Ow0KKwkJfTsNCisNCisJCWF1ZGlvOiBjbG9jay1jb250cm9sbGVyQDExMjEwMDAwIHsNCisJCQlj b21wYXRpYmxlID0gIm1lZGlhdGVrLG10Njc3OS1hdWRpbyIsICJzeXNjb24iOw0KKwkJCXJlZyA9 IDwwIDB4MTEyMTAwMDAgMCAweDEwMDA+Ow0KKwkJCSNjbG9jay1jZWxscyA9IDwxPjsNCisJCX07 DQorDQorCQltZmdjZmc6IGNsb2NrLWNvbnRyb2xsZXJAMTNmYmYwMDAgew0KKwkJCWNvbXBhdGli bGUgPSAibWVkaWF0ZWssbXQ2Nzc5LW1mZ2NmZyIsICJzeXNjb24iOw0KKwkJCXJlZyA9IDwwIDB4 MTNmYmYwMDAgMCAweDEwMDA+Ow0KKwkJCSNjbG9jay1jZWxscyA9IDwxPjsNCisJCX07DQorDQor CQltbXN5czogc3lzY29uQDE0MDAwMDAwIHsNCisJCQljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10 Njc3OS1tbXN5cyIsICJzeXNjb24iOw0KKwkJCXJlZyA9IDwwIDB4MTQwMDAwMDAgMCAweDEwMDA+ Ow0KKwkJCSNjbG9jay1jZWxscyA9IDwxPjsNCisJCX07DQorDQorCQlpbWdzeXM6IGNsb2NrLWNv bnRyb2xsZXJAMTUwMjAwMDAgew0KKwkJCWNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ2Nzc5LWlt Z3N5cyIsICJzeXNjb24iOw0KKwkJCXJlZyA9IDwwIDB4MTUwMjAwMDAgMCAweDEwMDA+Ow0KKwkJ CSNjbG9jay1jZWxscyA9IDwxPjsNCisJCX07DQorDQorCQl2ZGVjc3lzOiBjbG9jay1jb250cm9s bGVyQDE2MDAwMDAwIHsNCisJCQljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10Njc3OS12ZGVjc3lz IiwgInN5c2NvbiI7DQorCQkJcmVnID0gPDAgMHgxNjAwMDAwMCAwIDB4MTAwMD47DQorCQkJI2Ns b2NrLWNlbGxzID0gPDE+Ow0KKwkJfTsNCisNCisJCXZlbmNzeXM6IGNsb2NrLWNvbnRyb2xsZXJA MTcwMDAwMDAgew0KKwkJCWNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ2Nzc5LXZlbmNzeXMiLCAi c3lzY29uIjsNCisJCQlyZWcgPSA8MCAweDE3MDAwMDAwIDAgMHgxMDAwPjsNCisJCQkjY2xvY2st Y2VsbHMgPSA8MT47DQorCQl9Ow0KKw0KKwkJY2Ftc3lzOiBjbG9jay1jb250cm9sbGVyQDFhMDAw MDAwIHsNCisJCQljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10Njc3OS1jYW1zeXMiLCAic3lzY29u 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by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 21:30:15 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 21:30:15 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , "Michael Turquette" , Stephen Boyd Subject: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Date: Thu, 30 Jul 2020 21:30:15 +0800 Message-ID: <1596115816-11758-3-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> References: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_093043_297427_23FD90C0 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , Andy Teng , Hanks Chen , YueHaibing , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, Loda Chou , mtk01761 , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a57af9da9f5c..4d1b0f9d8d1c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000000..164f5cbb3821 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000000..370f309d32de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@0c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org 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13:31:06 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k18du-00048A-Uu; Thu, 30 Jul 2020 13:30:45 +0000 X-UUID: dbf2d1fc9f474217a6eda7d4fe852367-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EFC4xeBmcmvSxTLCFwKXro7Tw1yoAmDYNXqQcPM0FLA=; b=MjlWtpgcjfWP5Iy5I5ZRnO5lQHAud+7X+qWC4dTS+Y8THskANgkfCENfpJFXfhIuZ0kZCt2NRFwdpVeewRnFVwhwLj+Ss20VaQ8APOkzVB8Xkd3VbS9WlI9P6Ml/CLLU3NUhSUsqIeBYlB7mZTsAPbBtK3f/d5jNuzwaalFDJIw=; X-UUID: dbf2d1fc9f474217a6eda7d4fe852367-20200730 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 2032431452; Thu, 30 Jul 2020 05:30:20 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 06:30:31 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 21:30:15 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 21:30:15 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , "Michael Turquette" , Stephen Boyd Subject: [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Date: Thu, 30 Jul 2020 21:30:15 +0800 Message-ID: <1596115816-11758-3-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> References: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_093043_297427_23FD90C0 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , Andy Teng , Hanks Chen , YueHaibing , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, Loda Chou , mtk01761 , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a57af9da9f5c..4d1b0f9d8d1c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000000..164f5cbb3821 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000000..370f309d32de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@0c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel