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[5.147.80.91]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42d9b1899efsm136849505e9.30.2024.09.17.06.28.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Sep 2024 06:28:44 -0700 (PDT) Message-ID: <15c359a4-b3c1-4cb0-be2e-d5ca5537bc5b@canonical.com> Date: Tue, 17 Sep 2024 15:28:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] target/riscv: enable floating point unit To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <20240916181633.366449-1-heinrich.schuchardt@canonical.com> <20240917-f45624310204491aede04703@orel> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <20240917-f45624310204491aede04703@orel> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=185.125.188.122; envelope-from=heinrich.schuchardt@canonical.com; helo=smtp-relay-internal-0.canonical.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 17.09.24 14:13, Andrew Jones wrote: > On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote: >> OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM >> should do the same. >> >> Without this patch EDK II with TLS enabled crashes when hitting the first >> floating point instruction while running QEMU with --accel kvm and runs >> fine with --accel tcg. >> >> Additionally to this patch EDK II should be changed to make no assumptions >> about the state of the floating point unit. >> >> Signed-off-by: Heinrich Schuchardt >> --- >> target/riscv/cpu.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 4bda754b01..c32e2721d4 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -923,6 +923,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) >> if (mcc->parent_phases.hold) { >> mcc->parent_phases.hold(obj, type); >> } >> + if (riscv_has_ext(env, RVF) || riscv_has_ext(env, RVD)) { >> + env->mstatus = set_field(env->mstatus, MSTATUS_FS, env->misa_mxl); >> + for (int regnr = 0; regnr < 32; ++regnr) { >> + env->fpr[regnr] = 0; >> + } >> + riscv_csrrw(env, CSR_FCSR, NULL, 0, -1); >> + } > > If this is only fixing KVM, then I think it belongs in > kvm_riscv_reset_vcpu(). But, I feel like we're working around an issue > with KVM synchronization with this, as well as with the "clear CSR values" > part of commit 8633951530cc ("target/riscv: Clear CSR values at reset and > sync MPSTATE with host"). KVM knows how to reset VCPUs. It does so on > VCPU creation and for any secondaries started with SBI HSM start. KVM's > reset would set sstatus.FS to 1 ("Initial") and zero out all the fp > registers and fcsr. So it seems like we're either synchronizing prior to > KVM resetting the boot VCPU, not synchronizing at all, or KVM isn't doing > the reset of the boot VCPU. > > Thanks, > drew Hello Drew, Thanks for reviewing. Concerning the question whether kvm_riscv_reset_vcpu() would be a better place for the change: Is there any specification prescribing what the state of the FS bits should be when entering M-mode and when entering S-mode? Patch 8633951530cc seems not to touch the status register in QEMU's kvm_riscv_reset_vcpu(). So it is not obvious that this patch could have caused the problem. Looking at the call sequences in Linux gives some ideas where to debug: kvm_arch_vcpu_create calls kvm_riscv_reset_vcpu which calls kvm_riscv_vcpu_fp_reset. riscv_vcpu_set_isa_ext_single and kvm_riscv_vcpu_set_reg_config only call kvm_riscv_vcpu_fp_reset if !vcpu->arch.ran_atleast_once. kvm_riscv_vcpu_fp_reset sets FS bits to "initial" if CONFIG_FPU=y and extension F or D is available. It seems that in KVM only the creation of a vcpu will set the FS bits but rebooting will not. Best regards Heinrich