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([2804:7f0:bcc2:6962:5520:30ca:9e66:df39]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7e94424c93fsm15123632a34.14.2026.06.25.05.14.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2026 05:14:04 -0700 (PDT) Message-ID: <15e2ffbd-cb14-4767-ab56-e647fdc38b15@oss.qualcomm.com> Date: Thu, 25 Jun 2026 09:13:59 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/riscv: Report QEMU CPU archid as 42 To: Charlie Jenkins , qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Atish Patra , qemu-riscv@nongnu.org References: <20260624-marchid-v1-1-a0af7997071f@gmail.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20260624-marchid-v1-1-a0af7997071f@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OL8XGyaB c=1 sm=1 tr=0 ts=6a3d1b8e cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=xvfqbYfxAAAA:20 a=VwQbUJbxAAAA:8 a=h0uksLzaAAAA:8 a=pGLkceISAAAA:8 a=-mnagkuO7avN7E2oGvQA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 a=MSi_79tMYmZZG2gvAgS0:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDEwNSBTYWx0ZWRfXwTSXlitPFQ+6 1g+1EOTZBJm6RzubY10twfnQZtV5PXs4TQMqUMld817YkLOlOeX91LWTebYdG1PtmkgTYxQagTK +4bUMV1Ewd7VnT1CuCDtOUqn+p0s+YLg67V661KAqKmOJES/5QrSGcyFggF9ElST42if0I1//9D BWf0R0iMuvH+jK+s4NjtGWmz/9YVAWcN6xBiTtQ+wUH8XmqeOr+f1dkaxUDshIDgRlf2W5YmHBY YDT2n2bMBJh6N36zUnr/9rD1RNfZa/c2BJqt6+eAC4goMkVVwr7Tc6p+NkdQIhMeJ/DB1aMLJKS DxOPtLATVqP/ukkgyl8wVfZgoQ/Td7wtVtlAQ/EdEd0C70Jdq/BMK4134RurCej9BgaCkBSWbWO jFFicxTGkaRVLVXlhPHqho+MmEo86x2NZgCJ8ompXKQa9N4X5UfDQRYeejxj7ykWbb38u7PAdFn Lf+878fsrPaykqfeXzQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDEwNSBTYWx0ZWRfXyng8J+H/QVdZ s7d9mXIG6igbbcUOwZz4+kWZXORwRJn0+6v48U7tjx+wSNjKRJlrcmDEcmGsPJ2k66Jm5Uw9Mwl gj5KhJMgrEdMpQmhMm5ksmpFx+TtPIM= X-Proofpoint-ORIG-GUID: ROOr40_nYijBdlp1wsBsjE2OiaHu2ERX X-Proofpoint-GUID: ROOr40_nYijBdlp1wsBsjE2OiaHu2ERX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250105 Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Hi, On 6/25/2026 3:26 AM, Charlie Jenkins wrote: > When a non-vendor CPU is used, report the archid as 42 which has been > allocated for QEMU in the riscv isa manual [1]. This can help software > check if it is running in QEMU. > > [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md > > Signed-off-by: Charlie Jenkins > --- > This series was original proposed by Palmer Dabbelt [1] with a follow up > by Daniel Henrique Barboza. This patch implement's Daniel's suggestion. > > When booting with a non-vendor CPU such as with the qemu arg "-cpu rv64" > marchid will now be reported as 42. > >> qemu-system-riscv64 ... -cpu rv64 > > processor : 0 > hart : 0 > isa : rv64imafdch_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sstc_svadu_svvptc > mmu : sv57 > mvendorid : 0x0 > marchid : 0x2a > mimpid : 0x0 > hart isa : rv64imafdch_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sstc_svadu_svvptc > > When booting with a vendor CPU like veyron-v1, the proper marchid will > still appear. > >> qemu-system-riscv64 ... -cpu veyron-v1 > > processor : 0 > hart : 0 > isa : rv64imafdch_zicbom_zicboz_ziccrse_zicntr_zicsr_zifencei_zihpm_zaamo_zalrsc_zca_zcd_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt > mmu : sv48 > mvendorid : 0x61f > marchid : 0x8000000000010000 > mimpid : 0x111 > hart isa : rv64imafdch_zicbom_zicboz_ziccrse_zicntr_zicsr_zifencei_zihpm_zaamo_zalrsc_zca_zcd_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt > > [1] https://lore.kernel.org/all/20240131182430.20174-1-palmer@rivosinc.com/ Thanks for linking the discussion. I have but a vague memory of it and the link helped. > --- > target/riscv/cpu.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fa497e5e8a..59d63f82c2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -44,6 +44,9 @@ > #endif > > /* RISC-V CPU definitions */ > +#define RISCV_CPU_MVENDORID 0 > +#define RISCV_CPU_MARCHID 42 > +#define RISCV_CPU_MIMPID 0 > static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; > const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, > RVC, RVS, RVU, RVH, RVG, RVB, 0}; > @@ -1198,6 +1201,12 @@ static void riscv_cpu_init(Object *obj) > } > #endif > > + if (!riscv_cpu_is_vendor(obj)) { > + RISCV_CPU(obj)->cfg.mvendorid = RISCV_CPU_MVENDORID; > + RISCV_CPU(obj)->cfg.marchid = RISCV_CPU_MARCHID; > + RISCV_CPU(obj)->cfg.mimpid = RISCV_CPU_MIMPID; > + } > + Two things: - we have a 'cpu' pointer at the start so you can use cpu->cfg... instead; - the "cpu_is_vendor" check shouldn't be needed. Whatever is set as default during cpu_init() must be overwritten by CPUDef settings done in each DEFINE_RISCV_CPU() macro. This happens at this point: env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); <================ Therefore we can remove the "cpu_is_vendor" check and just assign the default QEMU IDs as long as we do it before cpu_cfg_merge(e.g. right after "cpu->cfg.max_satp_mode = -1;"). If we do that we'll ensure that all CPUs will carry the RVI archid 42 unless told otherwise by the CPU definition. Yes, this will end up changing the IDs for vendor CPUs that don't set their own IDs. This is fine - if the CPU doesn't bother setting its own ID this means that the CPU is perfectly fine with whatever default ID QEMU will provide. Thanks, Daniel > accel_cpu_instance_init(CPU(obj)); > } > > > --- > base-commit: b83371668192a705b878e909c5ae9c1233cbd5fb > change-id: 20260624-marchid-80d176b873d8 > > Best regards, > -- > - Charlie >