From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 300E9C46466 for ; Tue, 6 Oct 2020 06:54:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0A0E20757 for ; Tue, 6 Oct 2020 06:54:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="q1sN+Zc+"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ZloxSqHc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0A0E20757 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0hy6dCsFXChH8nuq5ofHRjRs0KCONTY5L8qSneB/OVc=; b=q1sN+Zc+ybm/I3v8HCpuj8Nnq 2pxgj+SD4CpsYGaNeXuI5KrZJhcxcvAwcIQkZkFLOPV59ih2v6pWxT3XFdLMJF1h6lyihjfKiDxMK eE6yInFMw+1UdvcwdFXn/yBcJ/5O9LD+ZnIxQK33E/iMPbwTSsXKFhzSXdaOoUqccYIP3KzPW3imK Yc1EPyYb+eYS1SwVjgspN2eTaYQIDG3eW+hn1wlLTQozYUIos9Rvuzhr1qemaJMq7f5JuqE3GQaMq OwYRMRlLSxHkX7FBlS1MXsMv8oKCzhgHthdN1RQIptd4H14EodI8bWAstE7J+SQTg4Jz36m83NmgN zSomQX7aA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPgrC-0002NG-Vm; Tue, 06 Oct 2020 06:53:55 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPgr8-0002Kw-MZ; Tue, 06 Oct 2020 06:53:54 +0000 X-UUID: 85a3d4d5d2ee4b77abfb6e42d1bfaf10-20201005 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=0mBtm/fCfqfZesQrhxR5PAO+6fo5yZk/+rrmxHbf6SI=; b=ZloxSqHc45HuaK+nctBUhapu1q54qPxSma5UZYtJhHUvf8HuKfYyEYGtfNoOXl5qeg20yXjSjIA01KOOTRQL0rjJXhs16N0Ggf5ADFBgm4mdj2v6LCYtBa0QbtJkak2lCBzLvmnnmDH2h8AAsqrJvmq88lNcfDJPqevWuEQvnYU=; X-UUID: 85a3d4d5d2ee4b77abfb6e42d1bfaf10-20201005 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 78218353; Mon, 05 Oct 2020 22:53:30 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Oct 2020 23:53:28 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Oct 2020 14:53:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Oct 2020 14:53:26 +0800 Message-ID: <1601967207.8638.4.camel@mtksdaap41> Subject: Re: [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller From: Weiyi Lu To: Matthias Brugger Date: Tue, 6 Oct 2020 14:53:27 +0800 In-Reply-To: <19678952-e354-2067-e619-ffac28b347be@gmail.com> References: <20200910172826.3074357-1-enric.balletbo@collabora.com> <1601028361.1346.38.camel@mtksdaap41> <19678952-e354-2067-e619-ffac28b347be@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_025350_864662_81A466AC X-CRM114-Status: GOOD ( 40.08 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, drinkcat@chromium.org, linux-kernel@vger.kernel.org, fparent@baylibre.com, Rob Herring , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Enric Balletbo i Serra , Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Fri, 2020-09-25 at 16:04 +0200, Matthias Brugger wrote: > > On 25/09/2020 12:06, Weiyi Lu wrote: > > On Thu, 2020-09-10 at 19:28 +0200, Enric Balletbo i Serra wrote: > >> Dear all, > >> > >> This is a new driver with the aim to deprecate the mtk-scpsys driver. > >> The problem with that driver is that, in order to support more Mediatek > >> SoCs you need to add some logic to handle properly the power-up > >> sequence of newer Mediatek SoCs, doesn't handle parent-child power > >> domains and need to hardcode all the clocks in the driver itself. The > >> result is that the driver is getting bigger and bigger every time a > >> new SoC needs to be supported. > >> > > > > Hi Enric and Matthias, > > > > First of all, thank you for the patch. But I'm worried the problem you > > mentioned won't be solved even if we work on this new driver in the > > future. My work on the MT8183 scpsys(now v17) is to implement the new > > hardware logic. Here, I also see related patches, which means that these > > new logics are necessary. Why can't we work on the original driver? > > Well the decision was to change the driver in a not compatible way to make > device tree entries better. If we work on the old driver, we would need to find > some creative ways to handle old bindings vs new bindings. > > So I thought it would be better doing a fresh start implementing mt1873 support > for reference and add mt8183 as new SoC. From what I have seen mt8192 and others > fit the driver structure too. > > > Meanwhile, I thought maybe we should separate the driver into general > > control and platform data for each SoC, otherwise it'll keep getting > > bigger and bigger if it need to be support new SoC. > > > > We could in a later series split the SoC depended data structures and put them > in drivers/soc/mediatek/pm-domains-mt8183.h or something like this. Is that what > you mean? > Yes, that is what I want. And I guess it could avoid the collisions in the different defines to the control registers and power status bits you mentioned. Hope this will happen in this series. > > And consider DVFSRC > > (dynamic voltage and frequency scaling resource collector), should we > > keep the original driver name "scpsys" instead of "pm-domains" because > > it may provide more functions than power domains? > > > > It's on my list to look deeper into this series. The thing with the new driver > is, that the binding takes into account, that scpsys has several hardware block, > which are represented as child nodes in DTS. The pm-domains is just one of these > functionalities and I think DVFSRC should be a new driver with a child node of > scpsys in DTS. Does this make sense? > > Regards, > Matthias > > >> All this information can be getted from a properly defined binding, so > >> can be cleaner and smaller, hence, we implemented a new driver. For > >> now, only MT8173 and MT8183 is supported but should be fairly easy to > >> add support for new SoCs. > >> > >> Best regards, > >> Enric > >> > >> Enric Balletbo i Serra (4): > >> dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains > >> controller > >> soc: mediatek: Add MediaTek SCPSYS power domains > >> arm64: dts: mediatek: Add mt8173 power domain controller > >> dt-bindings: power: Add MT8183 power domains > >> > >> Matthias Brugger (8): > >> soc: mediatek: pm-domains: Add bus protection protocol > >> soc: mediatek: pm_domains: Make bus protection generic > >> soc: mediatek: pm-domains: Add SMI block as bus protection block > >> soc: mediatek: pm-domains: Add extra sram control > >> soc: mediatek: pm-domains: Add subsystem clocks > >> soc: mediatek: pm-domains: Allow bus protection to ignore clear ack > >> soc: mediatek: pm-domains: Add support for mt8183 > >> arm64: dts: mediatek: Add mt8183 power domains controller > >> > >> .../power/mediatek,power-controller.yaml | 173 ++++ > >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 78 +- > >> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 160 +++ > >> drivers/soc/mediatek/Kconfig | 13 + > >> drivers/soc/mediatek/Makefile | 1 + > >> drivers/soc/mediatek/mtk-infracfg.c | 5 - > >> drivers/soc/mediatek/mtk-pm-domains.c | 952 ++++++++++++++++++ > >> include/dt-bindings/power/mt8183-power.h | 26 + > >> include/linux/soc/mediatek/infracfg.h | 39 + > >> 9 files changed, 1433 insertions(+), 14 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > >> create mode 100644 drivers/soc/mediatek/mtk-pm-domains.c > >> create mode 100644 include/dt-bindings/power/mt8183-power.h > >> > > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E79F3C41604 for ; Tue, 6 Oct 2020 06:55:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49BFF20757 for ; Tue, 6 Oct 2020 06:55:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hwdTtq1H"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ZloxSqHc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 49BFF20757 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5jx587KBK+aMDcE6tVpZC5CSS+nmrANFODKTEqV8Fio=; b=hwdTtq1HygRE9cIzVZP6QIvhZ ZR4NvaqIsxVQ92PAsngg6gnNxBlseFcgrHV+VCfMz3IGWjEBvCKtwmb2RyeoVUaJFsIqVMNROPleQ fThNt/aWnrlLeSZ6B+e2c0bNZZWF0gDtWEswbQ8JLPCkIAkhHi2tOqjeKRfaqvFHAYxTCO8MS6ggA MYCwdARvo7nAHz+qdoyf6visVhuIQNpQ1ZYE3/i5kfVl2e9s9eTuyO+cx7DQuHmDagihINiAzSXS8 8Rh1l7wTWIrwAeTME+xvDb+NO6FyAM81By0fih+aRDn/c6Xy13yCQY+vEM5rbv0TiyUgjoVgfL9pM fH49iWu2w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPgrD-0002NM-Ql; Tue, 06 Oct 2020 06:53:55 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPgr8-0002Kw-MZ; Tue, 06 Oct 2020 06:53:54 +0000 X-UUID: 85a3d4d5d2ee4b77abfb6e42d1bfaf10-20201005 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=0mBtm/fCfqfZesQrhxR5PAO+6fo5yZk/+rrmxHbf6SI=; b=ZloxSqHc45HuaK+nctBUhapu1q54qPxSma5UZYtJhHUvf8HuKfYyEYGtfNoOXl5qeg20yXjSjIA01KOOTRQL0rjJXhs16N0Ggf5ADFBgm4mdj2v6LCYtBa0QbtJkak2lCBzLvmnnmDH2h8AAsqrJvmq88lNcfDJPqevWuEQvnYU=; X-UUID: 85a3d4d5d2ee4b77abfb6e42d1bfaf10-20201005 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 78218353; Mon, 05 Oct 2020 22:53:30 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Oct 2020 23:53:28 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Oct 2020 14:53:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Oct 2020 14:53:26 +0800 Message-ID: <1601967207.8638.4.camel@mtksdaap41> Subject: Re: [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller From: Weiyi Lu To: Matthias Brugger Date: Tue, 6 Oct 2020 14:53:27 +0800 In-Reply-To: <19678952-e354-2067-e619-ffac28b347be@gmail.com> References: <20200910172826.3074357-1-enric.balletbo@collabora.com> <1601028361.1346.38.camel@mtksdaap41> <19678952-e354-2067-e619-ffac28b347be@gmail.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_025350_864662_81A466AC X-CRM114-Status: GOOD ( 40.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, drinkcat@chromium.org, linux-kernel@vger.kernel.org, fparent@baylibre.com, Rob Herring , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Enric Balletbo i Serra , Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2020-09-25 at 16:04 +0200, Matthias Brugger wrote: > > On 25/09/2020 12:06, Weiyi Lu wrote: > > On Thu, 2020-09-10 at 19:28 +0200, Enric Balletbo i Serra wrote: > >> Dear all, > >> > >> This is a new driver with the aim to deprecate the mtk-scpsys driver. > >> The problem with that driver is that, in order to support more Mediatek > >> SoCs you need to add some logic to handle properly the power-up > >> sequence of newer Mediatek SoCs, doesn't handle parent-child power > >> domains and need to hardcode all the clocks in the driver itself. The > >> result is that the driver is getting bigger and bigger every time a > >> new SoC needs to be supported. > >> > > > > Hi Enric and Matthias, > > > > First of all, thank you for the patch. But I'm worried the problem you > > mentioned won't be solved even if we work on this new driver in the > > future. My work on the MT8183 scpsys(now v17) is to implement the new > > hardware logic. Here, I also see related patches, which means that these > > new logics are necessary. Why can't we work on the original driver? > > Well the decision was to change the driver in a not compatible way to make > device tree entries better. If we work on the old driver, we would need to find > some creative ways to handle old bindings vs new bindings. > > So I thought it would be better doing a fresh start implementing mt1873 support > for reference and add mt8183 as new SoC. From what I have seen mt8192 and others > fit the driver structure too. > > > Meanwhile, I thought maybe we should separate the driver into general > > control and platform data for each SoC, otherwise it'll keep getting > > bigger and bigger if it need to be support new SoC. > > > > We could in a later series split the SoC depended data structures and put them > in drivers/soc/mediatek/pm-domains-mt8183.h or something like this. Is that what > you mean? > Yes, that is what I want. And I guess it could avoid the collisions in the different defines to the control registers and power status bits you mentioned. Hope this will happen in this series. > > And consider DVFSRC > > (dynamic voltage and frequency scaling resource collector), should we > > keep the original driver name "scpsys" instead of "pm-domains" because > > it may provide more functions than power domains? > > > > It's on my list to look deeper into this series. The thing with the new driver > is, that the binding takes into account, that scpsys has several hardware block, > which are represented as child nodes in DTS. The pm-domains is just one of these > functionalities and I think DVFSRC should be a new driver with a child node of > scpsys in DTS. Does this make sense? > > Regards, > Matthias > > >> All this information can be getted from a properly defined binding, so > >> can be cleaner and smaller, hence, we implemented a new driver. For > >> now, only MT8173 and MT8183 is supported but should be fairly easy to > >> add support for new SoCs. > >> > >> Best regards, > >> Enric > >> > >> Enric Balletbo i Serra (4): > >> dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains > >> controller > >> soc: mediatek: Add MediaTek SCPSYS power domains > >> arm64: dts: mediatek: Add mt8173 power domain controller > >> dt-bindings: power: Add MT8183 power domains > >> > >> Matthias Brugger (8): > >> soc: mediatek: pm-domains: Add bus protection protocol > >> soc: mediatek: pm_domains: Make bus protection generic > >> soc: mediatek: pm-domains: Add SMI block as bus protection block > >> soc: mediatek: pm-domains: Add extra sram control > >> soc: mediatek: pm-domains: Add subsystem clocks > >> soc: mediatek: pm-domains: Allow bus protection to ignore clear ack > >> soc: mediatek: pm-domains: Add support for mt8183 > >> arm64: dts: mediatek: Add mt8183 power domains controller > >> > >> .../power/mediatek,power-controller.yaml | 173 ++++ > >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 78 +- > >> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 160 +++ > >> drivers/soc/mediatek/Kconfig | 13 + > >> drivers/soc/mediatek/Makefile | 1 + > >> drivers/soc/mediatek/mtk-infracfg.c | 5 - > >> drivers/soc/mediatek/mtk-pm-domains.c | 952 ++++++++++++++++++ > >> include/dt-bindings/power/mt8183-power.h | 26 + > >> include/linux/soc/mediatek/infracfg.h | 39 + > >> 9 files changed, 1433 insertions(+), 14 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > >> create mode 100644 drivers/soc/mediatek/mtk-pm-domains.c > >> create mode 100644 include/dt-bindings/power/mt8183-power.h > >> > > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF8FDC46466 for ; Tue, 6 Oct 2020 06:53:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 84CC920796 for ; Tue, 6 Oct 2020 06:53:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ZloxSqHc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727119AbgJFGxd (ORCPT ); Tue, 6 Oct 2020 02:53:33 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:59056 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725962AbgJFGxc (ORCPT ); Tue, 6 Oct 2020 02:53:32 -0400 X-UUID: f260151aa4514150892dcfff7668d041-20201006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=0mBtm/fCfqfZesQrhxR5PAO+6fo5yZk/+rrmxHbf6SI=; b=ZloxSqHc45HuaK+nctBUhapu1q54qPxSma5UZYtJhHUvf8HuKfYyEYGtfNoOXl5qeg20yXjSjIA01KOOTRQL0rjJXhs16N0Ggf5ADFBgm4mdj2v6LCYtBa0QbtJkak2lCBzLvmnnmDH2h8AAsqrJvmq88lNcfDJPqevWuEQvnYU=; X-UUID: f260151aa4514150892dcfff7668d041-20201006 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2049005359; Tue, 06 Oct 2020 14:53:28 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Oct 2020 14:53:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Oct 2020 14:53:26 +0800 Message-ID: <1601967207.8638.4.camel@mtksdaap41> Subject: Re: [PATCH 00/12] soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller From: Weiyi Lu To: Matthias Brugger CC: Enric Balletbo i Serra , , , , , Rob Herring , , , Collabora Kernel ML , Date: Tue, 6 Oct 2020 14:53:27 +0800 In-Reply-To: <19678952-e354-2067-e619-ffac28b347be@gmail.com> References: <20200910172826.3074357-1-enric.balletbo@collabora.com> <1601028361.1346.38.camel@mtksdaap41> <19678952-e354-2067-e619-ffac28b347be@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gRnJpLCAyMDIwLTA5LTI1IGF0IDE2OjA0ICswMjAwLCBNYXR0aGlhcyBCcnVnZ2VyIHdyb3Rl Og0KPiANCj4gT24gMjUvMDkvMjAyMCAxMjowNiwgV2VpeWkgTHUgd3JvdGU6DQo+ID4gT24gVGh1 LCAyMDIwLTA5LTEwIGF0IDE5OjI4ICswMjAwLCBFbnJpYyBCYWxsZXRibyBpIFNlcnJhIHdyb3Rl Og0KPiA+PiBEZWFyIGFsbCwNCj4gPj4NCj4gPj4gVGhpcyBpcyBhIG5ldyBkcml2ZXIgd2l0aCB0 aGUgYWltIHRvIGRlcHJlY2F0ZSB0aGUgbXRrLXNjcHN5cyBkcml2ZXIuDQo+ID4+IFRoZSBwcm9i bGVtIHdpdGggdGhhdCBkcml2ZXIgaXMgdGhhdCwgaW4gb3JkZXIgdG8gc3VwcG9ydCBtb3JlIE1l ZGlhdGVrDQo+ID4+IFNvQ3MgeW91IG5lZWQgdG8gYWRkIHNvbWUgbG9naWMgdG8gaGFuZGxlIHBy b3Blcmx5IHRoZSBwb3dlci11cA0KPiA+PiBzZXF1ZW5jZSBvZiBuZXdlciBNZWRpYXRlayBTb0Nz LCBkb2Vzbid0IGhhbmRsZSBwYXJlbnQtY2hpbGQgcG93ZXINCj4gPj4gZG9tYWlucyBhbmQgbmVl ZCB0byBoYXJkY29kZSBhbGwgdGhlIGNsb2NrcyBpbiB0aGUgZHJpdmVyIGl0c2VsZi4gVGhlDQo+ ID4+IHJlc3VsdCBpcyB0aGF0IHRoZSBkcml2ZXIgaXMgZ2V0dGluZyBiaWdnZXIgYW5kIGJpZ2dl ciBldmVyeSB0aW1lIGENCj4gPj4gbmV3IFNvQyBuZWVkcyB0byBiZSBzdXBwb3J0ZWQuDQo+ID4+ DQo+ID4gDQo+ID4gSGkgRW5yaWMgYW5kIE1hdHRoaWFzLA0KPiA+IA0KPiA+IEZpcnN0IG9mIGFs bCwgdGhhbmsgeW91IGZvciB0aGUgcGF0Y2guIEJ1dCBJJ20gd29ycmllZCB0aGUgcHJvYmxlbSB5 b3UNCj4gPiBtZW50aW9uZWQgd29uJ3QgYmUgc29sdmVkIGV2ZW4gaWYgd2Ugd29yayBvbiB0aGlz IG5ldyBkcml2ZXIgaW4gdGhlDQo+ID4gZnV0dXJlLiBNeSB3b3JrIG9uIHRoZSBNVDgxODMgc2Nw c3lzKG5vdyB2MTcpIGlzIHRvIGltcGxlbWVudCB0aGUgbmV3DQo+ID4gaGFyZHdhcmUgbG9naWMu IEhlcmUsIEkgYWxzbyBzZWUgcmVsYXRlZCBwYXRjaGVzLCB3aGljaCBtZWFucyB0aGF0IHRoZXNl DQo+ID4gbmV3IGxvZ2ljcyBhcmUgbmVjZXNzYXJ5LiBXaHkgY2FuJ3Qgd2Ugd29yayBvbiB0aGUg b3JpZ2luYWwgZHJpdmVyPw0KPiANCj4gV2VsbCB0aGUgZGVjaXNpb24gd2FzIHRvIGNoYW5nZSB0 aGUgZHJpdmVyIGluIGEgbm90IGNvbXBhdGlibGUgd2F5IHRvIG1ha2UgDQo+IGRldmljZSB0cmVl IGVudHJpZXMgYmV0dGVyLiBJZiB3ZSB3b3JrIG9uIHRoZSBvbGQgZHJpdmVyLCB3ZSB3b3VsZCBu ZWVkIHRvIGZpbmQgDQo+IHNvbWUgY3JlYXRpdmUgd2F5cyB0byBoYW5kbGUgb2xkIGJpbmRpbmdz IHZzIG5ldyBiaW5kaW5ncy4NCj4gDQo+IFNvIEkgdGhvdWdodCBpdCB3b3VsZCBiZSBiZXR0ZXIg ZG9pbmcgYSBmcmVzaCBzdGFydCBpbXBsZW1lbnRpbmcgbXQxODczIHN1cHBvcnQgDQo+IGZvciBy ZWZlcmVuY2UgYW5kIGFkZCBtdDgxODMgYXMgbmV3IFNvQy4gRnJvbSB3aGF0IEkgaGF2ZSBzZWVu IG10ODE5MiBhbmQgb3RoZXJzIA0KPiBmaXQgdGhlIGRyaXZlciBzdHJ1Y3R1cmUgdG9vLg0KPiAN Cj4gPiBNZWFud2hpbGUsIEkgdGhvdWdodCBtYXliZSB3ZSBzaG91bGQgc2VwYXJhdGUgdGhlIGRy aXZlciBpbnRvIGdlbmVyYWwNCj4gPiBjb250cm9sIGFuZCBwbGF0Zm9ybSBkYXRhIGZvciBlYWNo IFNvQywgb3RoZXJ3aXNlIGl0J2xsIGtlZXAgZ2V0dGluZw0KPiA+IGJpZ2dlciBhbmQgYmlnZ2Vy IGlmIGl0IG5lZWQgdG8gYmUgc3VwcG9ydCBuZXcgU29DLg0KPiA+IA0KPiANCj4gV2UgY291bGQg aW4gYSBsYXRlciBzZXJpZXMgc3BsaXQgdGhlIFNvQyBkZXBlbmRlZCBkYXRhIHN0cnVjdHVyZXMg YW5kIHB1dCB0aGVtIA0KPiBpbiBkcml2ZXJzL3NvYy9tZWRpYXRlay9wbS1kb21haW5zLW10ODE4 My5oIG9yIHNvbWV0aGluZyBsaWtlIHRoaXMuIElzIHRoYXQgd2hhdCANCj4geW91IG1lYW4/DQo+ IA0KDQpZZXMsIHRoYXQgaXMgd2hhdCBJIHdhbnQuIEFuZCBJIGd1ZXNzIGl0IGNvdWxkIGF2b2lk IHRoZSBjb2xsaXNpb25zIGluDQp0aGUgZGlmZmVyZW50IGRlZmluZXMgdG8gdGhlIGNvbnRyb2wg cmVnaXN0ZXJzIGFuZCBwb3dlciBzdGF0dXMgYml0cyB5b3UNCm1lbnRpb25lZC4gSG9wZSB0aGlz IHdpbGwgaGFwcGVuIGluIHRoaXMgc2VyaWVzLg0KDQo+ID4gQW5kIGNvbnNpZGVyIERWRlNSQw0K PiA+IChkeW5hbWljIHZvbHRhZ2UgYW5kIGZyZXF1ZW5jeSBzY2FsaW5nIHJlc291cmNlIGNvbGxl Y3RvciksIHNob3VsZCB3ZQ0KPiA+IGtlZXAgdGhlIG9yaWdpbmFsIGRyaXZlciBuYW1lICJzY3Bz eXMiIGluc3RlYWQgb2YgInBtLWRvbWFpbnMiIGJlY2F1c2UNCj4gPiBpdCBtYXkgcHJvdmlkZSBt b3JlIGZ1bmN0aW9ucyB0aGFuIHBvd2VyIGRvbWFpbnM/DQo+ID4gDQo+IA0KPiBJdCdzIG9uIG15 IGxpc3QgdG8gbG9vayBkZWVwZXIgaW50byB0aGlzIHNlcmllcy4gVGhlIHRoaW5nIHdpdGggdGhl IG5ldyBkcml2ZXIgDQo+IGlzLCB0aGF0IHRoZSBiaW5kaW5nIHRha2VzIGludG8gYWNjb3VudCwg dGhhdCBzY3BzeXMgaGFzIHNldmVyYWwgaGFyZHdhcmUgYmxvY2ssIA0KPiB3aGljaCBhcmUgcmVw cmVzZW50ZWQgYXMgY2hpbGQgbm9kZXMgaW4gRFRTLiBUaGUgcG0tZG9tYWlucyBpcyBqdXN0IG9u ZSBvZiB0aGVzZSANCj4gZnVuY3Rpb25hbGl0aWVzIGFuZCBJIHRoaW5rIERWRlNSQyBzaG91bGQg YmUgYSBuZXcgZHJpdmVyIHdpdGggYSBjaGlsZCBub2RlIG9mIA0KPiBzY3BzeXMgaW4gRFRTLiBE b2VzIHRoaXMgbWFrZSBzZW5zZT8NCj4gDQo+IFJlZ2FyZHMsDQo+IE1hdHRoaWFzDQo+IA0KPiA+ PiBBbGwgdGhpcyBpbmZvcm1hdGlvbiBjYW4gYmUgZ2V0dGVkIGZyb20gYSBwcm9wZXJseSBkZWZp bmVkIGJpbmRpbmcsIHNvDQo+ID4+IGNhbiBiZSBjbGVhbmVyIGFuZCBzbWFsbGVyLCBoZW5jZSwg d2UgaW1wbGVtZW50ZWQgYSBuZXcgZHJpdmVyLiBGb3INCj4gPj4gbm93LCBvbmx5IE1UODE3MyBh bmQgTVQ4MTgzIGlzIHN1cHBvcnRlZCBidXQgc2hvdWxkIGJlIGZhaXJseSBlYXN5IHRvDQo+ID4+ IGFkZCBzdXBwb3J0IGZvciBuZXcgU29Dcy4NCj4gPj4NCj4gPj4gQmVzdCByZWdhcmRzLA0KPiA+ PiAgICBFbnJpYw0KPiA+Pg0KPiA+PiBFbnJpYyBCYWxsZXRibyBpIFNlcnJhICg0KToNCj4gPj4g ICAgZHQtYmluZGluZ3M6IHBvd2VyOiBBZGQgYmluZGluZ3MgZm9yIHRoZSBNZWRpYXRlayBTQ1BT WVMgcG93ZXIgZG9tYWlucw0KPiA+PiAgICAgIGNvbnRyb2xsZXINCj4gPj4gICAgc29jOiBtZWRp YXRlazogQWRkIE1lZGlhVGVrIFNDUFNZUyBwb3dlciBkb21haW5zDQo+ID4+ICAgIGFybTY0OiBk dHM6IG1lZGlhdGVrOiBBZGQgbXQ4MTczIHBvd2VyIGRvbWFpbiBjb250cm9sbGVyDQo+ID4+ICAg IGR0LWJpbmRpbmdzOiBwb3dlcjogQWRkIE1UODE4MyBwb3dlciBkb21haW5zDQo+ID4+DQo+ID4+ IE1hdHRoaWFzIEJydWdnZXIgKDgpOg0KPiA+PiAgICBzb2M6IG1lZGlhdGVrOiBwbS1kb21haW5z OiBBZGQgYnVzIHByb3RlY3Rpb24gcHJvdG9jb2wNCj4gPj4gICAgc29jOiBtZWRpYXRlazogcG1f ZG9tYWluczogTWFrZSBidXMgcHJvdGVjdGlvbiBnZW5lcmljDQo+ID4+ICAgIHNvYzogbWVkaWF0 ZWs6IHBtLWRvbWFpbnM6IEFkZCBTTUkgYmxvY2sgYXMgYnVzIHByb3RlY3Rpb24gYmxvY2sNCj4g Pj4gICAgc29jOiBtZWRpYXRlazogcG0tZG9tYWluczogQWRkIGV4dHJhIHNyYW0gY29udHJvbA0K PiA+PiAgICBzb2M6IG1lZGlhdGVrOiBwbS1kb21haW5zOiBBZGQgc3Vic3lzdGVtIGNsb2Nrcw0K PiA+PiAgICBzb2M6IG1lZGlhdGVrOiBwbS1kb21haW5zOiBBbGxvdyBidXMgcHJvdGVjdGlvbiB0 byBpZ25vcmUgY2xlYXIgYWNrDQo+ID4+ICAgIHNvYzogbWVkaWF0ZWs6IHBtLWRvbWFpbnM6IEFk ZCBzdXBwb3J0IGZvciBtdDgxODMNCj4gPj4gICAgYXJtNjQ6IGR0czogbWVkaWF0ZWs6IEFkZCBt dDgxODMgcG93ZXIgZG9tYWlucyBjb250cm9sbGVyDQo+ID4+DQo+ID4+ICAgLi4uL3Bvd2VyL21l ZGlhdGVrLHBvd2VyLWNvbnRyb2xsZXIueWFtbCAgICAgIHwgMTczICsrKysNCj4gPj4gICBhcmNo L2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210ODE3My5kdHNpICAgICAgfCAgNzggKy0NCj4gPj4g ICBhcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210ODE4My5kdHNpICAgICAgfCAxNjAgKysr DQo+ID4+ICAgZHJpdmVycy9zb2MvbWVkaWF0ZWsvS2NvbmZpZyAgICAgICAgICAgICAgICAgIHwg IDEzICsNCj4gPj4gICBkcml2ZXJzL3NvYy9tZWRpYXRlay9NYWtlZmlsZSAgICAgICAgICAgICAg ICAgfCAgIDEgKw0KPiA+PiAgIGRyaXZlcnMvc29jL21lZGlhdGVrL210ay1pbmZyYWNmZy5jICAg ICAgICAgICB8ICAgNSAtDQo+ID4+ICAgZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLXBtLWRvbWFp bnMuYyAgICAgICAgIHwgOTUyICsrKysrKysrKysrKysrKysrKw0KPiA+PiAgIGluY2x1ZGUvZHQt YmluZGluZ3MvcG93ZXIvbXQ4MTgzLXBvd2VyLmggICAgICB8ICAyNiArDQo+ID4+ICAgaW5jbHVk ZS9saW51eC9zb2MvbWVkaWF0ZWsvaW5mcmFjZmcuaCAgICAgICAgIHwgIDM5ICsNCj4gPj4gICA5 IGZpbGVzIGNoYW5nZWQsIDE0MzMgaW5zZXJ0aW9ucygrKSwgMTQgZGVsZXRpb25zKC0pDQo+ID4+ ICAgY3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9w b3dlci9tZWRpYXRlayxwb3dlci1jb250cm9sbGVyLnlhbWwNCj4gPj4gICBjcmVhdGUgbW9kZSAx MDA2NDQgZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRrLXBtLWRvbWFpbnMuYw0KPiA+PiAgIGNyZWF0 ZSBtb2RlIDEwMDY0NCBpbmNsdWRlL2R0LWJpbmRpbmdzL3Bvd2VyL210ODE4My1wb3dlci5oDQo+ ID4+DQo+ID4gDQo+IA0KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXw0KPiBMaW51eC1tZWRpYXRlayBtYWlsaW5nIGxpc3QNCj4gTGludXgtbWVkaWF0ZWtA bGlzdHMuaW5mcmFkZWFkLm9yZw0KPiBodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2xpbnV4LW1lZGlhdGVrDQoNCg==