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Fri, 09 Oct 2020 05:01:18 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Oct 2020 05:53:08 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Oct 2020 20:53:04 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Oct 2020 20:53:04 +0800 Message-ID: <1602247986.31946.7.camel@mhfsdcap03> Subject: Re: [PATCH v6 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base and irq From: Chuanjia Liu To: Rob Herring Date: Fri, 9 Oct 2020 20:53:06 +0800 In-Reply-To: <20200930152317.GA2891120@bogus> References: <20200914112659.7091-1-chuanjia.liu@mediatek.com> <20200914112659.7091-3-chuanjia.liu@mediatek.com> <20200930152317.GA2891120@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3F21F7E52E8679CF364EFB6F4570F032D594BEA8EFFEA4739B3B03C72BF09E392000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201009_090131_739452_B031908A X-CRM114-Status: GOOD ( 26.86 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lorenzo Pieralisi , Frank Wunderlich , linux-pci@vger.kernel.org, Matthias Brugger , Ryder Lee , linux-mediatek@lists.infradead.org, yong.wu@mediatek.com, Bjorn Helgaas , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 2020-09-30 at 10:23 -0500, Rob Herring wrote: > On Mon, Sep 14, 2020 at 07:26:57PM +0800, Chuanjia Liu wrote: > > Add new method to get shared pcie-cfg base and pcie irq for > > new dts format. > > > > Signed-off-by: Chuanjia Liu > > Acked-by: Ryder Lee > > --- > > drivers/pci/controller/pcie-mediatek.c | 23 ++++++++++++++++++++++- > > 1 file changed, 22 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > > index cf4c18f0c25a..5b915eb0cf1e 100644 > > --- a/drivers/pci/controller/pcie-mediatek.c > > +++ b/drivers/pci/controller/pcie-mediatek.c > > @@ -14,6 +14,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -23,6 +24,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > #include "../pci.h" > > @@ -205,6 +207,7 @@ struct mtk_pcie_port { > > * struct mtk_pcie - PCIe host information > > * @dev: pointer to PCIe device > > * @base: IO mapped register base > > + * @cfg: IO mapped register map for PCIe config > > * @free_ck: free-run reference clock > > * @mem: non-prefetchable memory resource > > * @ports: pointer to PCIe port information > > @@ -213,6 +216,7 @@ struct mtk_pcie_port { > > struct mtk_pcie { > > struct device *dev; > > void __iomem *base; > > + struct regmap *cfg; > > struct clk *free_ck; > > > > struct list_head ports; > > @@ -648,7 +652,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, > > return err; > > } > > > > - port->irq = platform_get_irq(pdev, port->slot); > > + if (of_find_property(dev->of_node, "interrupt-names", NULL)) > > + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); > > Not really any point in having a name with a single interrupt. > > > + else > > + port->irq = platform_get_irq(pdev, port->slot); > > With the new binding, slot is always 0, right? Then you don't need any > change here. In the new binding, PCIe1 slot number is 1. Because some setting in the driver is based on slot number to determine offset, this is to reduce driver changes and be compatible with new and old DTS format. > > > + > > if (port->irq < 0) > > return port->irq; > > > > @@ -680,6 +688,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > > val |= PCIE_CSR_LTSSM_EN(port->slot) | > > PCIE_CSR_ASPM_L1_EN(port->slot); > > writel(val, pcie->base + PCIE_SYS_CFG_V2); > > + } else if (pcie->cfg) { > > + val = PCIE_CSR_LTSSM_EN(port->slot) | > > + PCIE_CSR_ASPM_L1_EN(port->slot); > > + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > > } > > > > /* Assert all reset signals */ > > @@ -983,6 +995,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > > struct device *dev = pcie->dev; > > struct platform_device *pdev = to_platform_device(dev); > > struct resource *regs; > > + struct device_node *cfg_node; > > int err; > > > > /* get shared registers, which are optional */ > > @@ -995,6 +1008,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > > } > > } > > > > + cfg_node = of_find_compatible_node(NULL, NULL, > > + "mediatek,generic-pciecfg"); > > + if (cfg_node) { > > + pcie->cfg = syscon_node_to_regmap(cfg_node); > > + if (IS_ERR(pcie->cfg)) > > + return PTR_ERR(pcie->cfg); > > + } > > + > > pcie->free_ck = devm_clk_get(dev, "free_ck"); > > if (IS_ERR(pcie->free_ck)) { > > if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) > > -- > > 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, 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T24gTW9uLCBTZXAgMTQsIDIwMjAgYXQgMDc6MjY6NTdQTSArMDgwMCwgQ2h1YW5qaWEgTGl1IHdy b3RlOg0KPiA+IEFkZCBuZXcgbWV0aG9kIHRvIGdldCBzaGFyZWQgcGNpZS1jZmcgYmFzZSBhbmQg cGNpZSBpcnEgZm9yDQo+ID4gbmV3IGR0cyBmb3JtYXQuDQo+ID4gDQo+ID4gU2lnbmVkLW9mZi1i eTogQ2h1YW5qaWEgTGl1IDxjaHVhbmppYS5saXVAbWVkaWF0ZWsuY29tPg0KPiA+IEFja2VkLWJ5 OiBSeWRlciBMZWUgPHJ5ZGVyLmxlZUBtZWRpYXRlay5jb20+DQo+ID4gLS0tDQo+ID4gIGRyaXZl cnMvcGNpL2NvbnRyb2xsZXIvcGNpZS1tZWRpYXRlay5jIHwgMjMgKysrKysrKysrKysrKysrKysr KysrKy0NCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDIyIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24o LSkNCj4gPiANCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLW1l ZGlhdGVrLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtbWVkaWF0ZWsuYw0KPiA+IGlu ZGV4IGNmNGMxOGYwYzI1YS4uNWI5MTVlYjBjZjFlIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMv cGNpL2NvbnRyb2xsZXIvcGNpZS1tZWRpYXRlay5jDQo+ID4gKysrIGIvZHJpdmVycy9wY2kvY29u dHJvbGxlci9wY2llLW1lZGlhdGVrLmMNCj4gPiBAQCAtMTQsNiArMTQsNyBAQA0KPiA+ICAjaW5j bHVkZSA8bGludXgvaXJxY2hpcC9jaGFpbmVkX2lycS5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgv aXJxZG9tYWluLmg+DQo+ID4gICNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4NCj4gPiArI2luY2x1 ZGUgPGxpbnV4L21mZC9zeXNjb24uaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4L21zaS5oPg0KPiA+ ICAjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+DQo+ID4gICNpbmNsdWRlIDxsaW51eC9vZl9hZGRy ZXNzLmg+DQo+ID4gQEAgLTIzLDYgKzI0LDcgQEANCj4gPiAgI2luY2x1ZGUgPGxpbnV4L3BoeS9w aHkuaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPg0KPiA+ICAjaW5j bHVkZSA8bGludXgvcG1fcnVudGltZS5oPg0KPiA+ICsjaW5jbHVkZSA8bGludXgvcmVnbWFwLmg+ DQo+ID4gICNpbmNsdWRlIDxsaW51eC9yZXNldC5oPg0KPiA+ICANCj4gPiAgI2luY2x1ZGUgIi4u L3BjaS5oIg0KPiA+IEBAIC0yMDUsNiArMjA3LDcgQEAgc3RydWN0IG10a19wY2llX3BvcnQgew0K PiA+ICAgKiBzdHJ1Y3QgbXRrX3BjaWUgLSBQQ0llIGhvc3QgaW5mb3JtYXRpb24NCj4gPiAgICog QGRldjogcG9pbnRlciB0byBQQ0llIGRldmljZQ0KPiA+ICAgKiBAYmFzZTogSU8gbWFwcGVkIHJl Z2lzdGVyIGJhc2UNCj4gPiArICogQGNmZzogSU8gbWFwcGVkIHJlZ2lzdGVyIG1hcCBmb3IgUENJ ZSBjb25maWcNCj4gPiAgICogQGZyZWVfY2s6IGZyZWUtcnVuIHJlZmVyZW5jZSBjbG9jaw0KPiA+ ICAgKiBAbWVtOiBub24tcHJlZmV0Y2hhYmxlIG1lbW9yeSByZXNvdXJjZQ0KPiA+ICAgKiBAcG9y dHM6IHBvaW50ZXIgdG8gUENJZSBwb3J0IGluZm9ybWF0aW9uDQo+ID4gQEAgLTIxMyw2ICsyMTYs NyBAQCBzdHJ1Y3QgbXRrX3BjaWVfcG9ydCB7DQo+ID4gIHN0cnVjdCBtdGtfcGNpZSB7DQo+ID4g IAlzdHJ1Y3QgZGV2aWNlICpkZXY7DQo+ID4gIAl2b2lkIF9faW9tZW0gKmJhc2U7DQo+ID4gKwlz dHJ1Y3QgcmVnbWFwICpjZmc7DQo+ID4gIAlzdHJ1Y3QgY2xrICpmcmVlX2NrOw0KPiA+ICANCj4g PiAgCXN0cnVjdCBsaXN0X2hlYWQgcG9ydHM7DQo+ID4gQEAgLTY0OCw3ICs2NTIsMTEgQEAgc3Rh dGljIGludCBtdGtfcGNpZV9zZXR1cF9pcnEoc3RydWN0IG10a19wY2llX3BvcnQgKnBvcnQsDQo+ ID4gIAkJcmV0dXJuIGVycjsNCj4gPiAgCX0NCj4gPiAgDQo+ID4gLQlwb3J0LT5pcnEgPSBwbGF0 Zm9ybV9nZXRfaXJxKHBkZXYsIHBvcnQtPnNsb3QpOw0KPiA+ICsJaWYgKG9mX2ZpbmRfcHJvcGVy dHkoZGV2LT5vZl9ub2RlLCAiaW50ZXJydXB0LW5hbWVzIiwgTlVMTCkpDQo+ID4gKwkJcG9ydC0+ aXJxID0gcGxhdGZvcm1fZ2V0X2lycV9ieW5hbWUocGRldiwgInBjaWVfaXJxIik7DQo+IA0KPiBO b3QgcmVhbGx5IGFueSBwb2ludCBpbiBoYXZpbmcgYSBuYW1lIHdpdGggYSBzaW5nbGUgaW50ZXJy dXB0Lg0KPiANCj4gPiArCWVsc2UNCj4gPiArCQlwb3J0LT5pcnEgPSBwbGF0Zm9ybV9nZXRfaXJx KHBkZXYsIHBvcnQtPnNsb3QpOw0KPiANCj4gV2l0aCB0aGUgbmV3IGJpbmRpbmcsIHNsb3QgaXMg YWx3YXlzIDAsIHJpZ2h0PyBUaGVuIHlvdSBkb24ndCBuZWVkIGFueSANCj4gY2hhbmdlIGhlcmUu DQpJbiB0aGUgbmV3IGJpbmRpbmcsIFBDSWUxIHNsb3QgbnVtYmVyIGlzIDEuDQpCZWNhdXNlIHNv bWUgc2V0dGluZyBpbiB0aGUgZHJpdmVyIGlzIGJhc2VkIG9uIHNsb3QgbnVtYmVyIHRvIGRldGVy bWluZQ0Kb2Zmc2V0LCB0aGlzIGlzIHRvIHJlZHVjZSBkcml2ZXIgY2hhbmdlcyBhbmQgYmUgY29t cGF0aWJsZSB3aXRoIG5ldyBhbmQNCm9sZCBEVFMgZm9ybWF0Lg0KPiANCj4gPiArDQo+ID4gIAlp ZiAocG9ydC0+aXJxIDwgMCkNCj4gPiAgCQlyZXR1cm4gcG9ydC0+aXJxOw0KPiA+ICANCj4gPiBA QCAtNjgwLDYgKzY4OCwxMCBAQCBzdGF0aWMgaW50IG10a19wY2llX3N0YXJ0dXBfcG9ydF92Mihz dHJ1Y3QgbXRrX3BjaWVfcG9ydCAqcG9ydCkNCj4gPiAgCQl2YWwgfD0gUENJRV9DU1JfTFRTU01f RU4ocG9ydC0+c2xvdCkgfA0KPiA+ICAJCSAgICAgICBQQ0lFX0NTUl9BU1BNX0wxX0VOKHBvcnQt PnNsb3QpOw0KPiA+ICAJCXdyaXRlbCh2YWwsIHBjaWUtPmJhc2UgKyBQQ0lFX1NZU19DRkdfVjIp Ow0KPiA+ICsJfSBlbHNlIGlmIChwY2llLT5jZmcpIHsNCj4gPiArCQl2YWwgPSBQQ0lFX0NTUl9M VFNTTV9FTihwb3J0LT5zbG90KSB8DQo+ID4gKwkJICAgICAgUENJRV9DU1JfQVNQTV9MMV9FTihw b3J0LT5zbG90KTsNCj4gPiArCQlyZWdtYXBfdXBkYXRlX2JpdHMocGNpZS0+Y2ZnLCBQQ0lFX1NZ U19DRkdfVjIsIHZhbCwgdmFsKTsNCj4gPiAgCX0NCj4gPiAgDQo+ID4gIAkvKiBBc3NlcnQgYWxs IHJlc2V0IHNpZ25hbHMgKi8NCj4gPiBAQCAtOTgzLDYgKzk5NSw3IEBAIHN0YXRpYyBpbnQgbXRr X3BjaWVfc3Vic3lzX3Bvd2VydXAoc3RydWN0IG10a19wY2llICpwY2llKQ0KPiA+ICAJc3RydWN0 IGRldmljZSAqZGV2ID0gcGNpZS0+ZGV2Ow0KPiA+ICAJc3RydWN0IHBsYXRmb3JtX2RldmljZSAq cGRldiA9IHRvX3BsYXRmb3JtX2RldmljZShkZXYpOw0KPiA+ICAJc3RydWN0IHJlc291cmNlICpy ZWdzOw0KPiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpjZmdfbm9kZTsNCj4gPiAgCWludCBlcnI7 DQo+ID4gIA0KPiA+ICAJLyogZ2V0IHNoYXJlZCByZWdpc3RlcnMsIHdoaWNoIGFyZSBvcHRpb25h bCAqLw0KPiA+IEBAIC05OTUsNiArMTAwOCwxNCBAQCBzdGF0aWMgaW50IG10a19wY2llX3N1YnN5 c19wb3dlcnVwKHN0cnVjdCBtdGtfcGNpZSAqcGNpZSkNCj4gPiAgCQl9DQo+ID4gIAl9DQo+ID4g IA0KPiA+ICsJY2ZnX25vZGUgPSBvZl9maW5kX2NvbXBhdGlibGVfbm9kZShOVUxMLCBOVUxMLA0K PiA+ICsJCQkJCSAgICJtZWRpYXRlayxnZW5lcmljLXBjaWVjZmciKTsNCj4gPiArCWlmIChjZmdf bm9kZSkgew0KPiA+ICsJCXBjaWUtPmNmZyA9IHN5c2Nvbl9ub2RlX3RvX3JlZ21hcChjZmdfbm9k ZSk7DQo+ID4gKwkJaWYgKElTX0VSUihwY2llLT5jZmcpKQ0KPiA+ICsJCQlyZXR1cm4gUFRSX0VS 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88409e3afb77450096cb1f61cb9ad234-20201009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=T0Q1hS1atV6ZgjZZgJ8HAejic+x9fuXgQyfpLTiToJ0=; b=udTpYlCAxRu1ZXH9avMz0tCdhfuip4oF76AtWAWYp3Uy1VX7wq2/e1QBIMoswzmEI+0yUhH732CdaukDapLTuLCl7OwmevUgEnVrz5eyVaoSo0Gf77BAM7OUV0NCmS17HI+9RBi9jHJz1mOc41KZexaS7LGv3HyqAERPDND9qmk=; X-UUID: 88409e3afb77450096cb1f61cb9ad234-20201009 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1518434297; Fri, 09 Oct 2020 05:01:18 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Oct 2020 05:53:08 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Oct 2020 20:53:04 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Oct 2020 20:53:04 +0800 Message-ID: <1602247986.31946.7.camel@mhfsdcap03> Subject: Re: [PATCH v6 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base and irq From: Chuanjia Liu To: Rob Herring Date: Fri, 9 Oct 2020 20:53:06 +0800 In-Reply-To: <20200930152317.GA2891120@bogus> References: <20200914112659.7091-1-chuanjia.liu@mediatek.com> <20200914112659.7091-3-chuanjia.liu@mediatek.com> <20200930152317.GA2891120@bogus> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3F21F7E52E8679CF364EFB6F4570F032D594BEA8EFFEA4739B3B03C72BF09E392000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201009_090131_739452_B031908A X-CRM114-Status: GOOD ( 26.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lorenzo Pieralisi , Frank Wunderlich , linux-pci@vger.kernel.org, Matthias Brugger , Ryder Lee , linux-mediatek@lists.infradead.org, yong.wu@mediatek.com, Bjorn Helgaas , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-09-30 at 10:23 -0500, Rob Herring wrote: > On Mon, Sep 14, 2020 at 07:26:57PM +0800, Chuanjia Liu wrote: > > Add new method to get shared pcie-cfg base and pcie irq for > > new dts format. > > > > Signed-off-by: Chuanjia Liu > > Acked-by: Ryder Lee > > --- > > drivers/pci/controller/pcie-mediatek.c | 23 ++++++++++++++++++++++- > > 1 file changed, 22 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > > index cf4c18f0c25a..5b915eb0cf1e 100644 > > --- a/drivers/pci/controller/pcie-mediatek.c > > +++ b/drivers/pci/controller/pcie-mediatek.c > > @@ -14,6 +14,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -23,6 +24,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > #include "../pci.h" > > @@ -205,6 +207,7 @@ struct mtk_pcie_port { > > * struct mtk_pcie - PCIe host information > > * @dev: pointer to PCIe device > > * @base: IO mapped register base > > + * @cfg: IO mapped register map for PCIe config > > * @free_ck: free-run reference clock > > * @mem: non-prefetchable memory resource > > * @ports: pointer to PCIe port information > > @@ -213,6 +216,7 @@ struct mtk_pcie_port { > > struct mtk_pcie { > > struct device *dev; > > void __iomem *base; > > + struct regmap *cfg; > > struct clk *free_ck; > > > > struct list_head ports; > > @@ -648,7 +652,11 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, > > return err; > > } > > > > - port->irq = platform_get_irq(pdev, port->slot); > > + if (of_find_property(dev->of_node, "interrupt-names", NULL)) > > + port->irq = platform_get_irq_byname(pdev, "pcie_irq"); > > Not really any point in having a name with a single interrupt. > > > + else > > + port->irq = platform_get_irq(pdev, port->slot); > > With the new binding, slot is always 0, right? Then you don't need any > change here. In the new binding, PCIe1 slot number is 1. Because some setting in the driver is based on slot number to determine offset, this is to reduce driver changes and be compatible with new and old DTS format. > > > + > > if (port->irq < 0) > > return port->irq; > > > > @@ -680,6 +688,10 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > > val |= PCIE_CSR_LTSSM_EN(port->slot) | > > PCIE_CSR_ASPM_L1_EN(port->slot); > > writel(val, pcie->base + PCIE_SYS_CFG_V2); > > + } else if (pcie->cfg) { > > + val = PCIE_CSR_LTSSM_EN(port->slot) | > > + PCIE_CSR_ASPM_L1_EN(port->slot); > > + regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > > } > > > > /* Assert all reset signals */ > > @@ -983,6 +995,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > > struct device *dev = pcie->dev; > > struct platform_device *pdev = to_platform_device(dev); > > struct resource *regs; > > + struct device_node *cfg_node; > > int err; > > > > /* get shared registers, which are optional */ > > @@ -995,6 +1008,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) > > } > > } > > > > + cfg_node = of_find_compatible_node(NULL, NULL, > > + "mediatek,generic-pciecfg"); > > + if (cfg_node) { > > + pcie->cfg = syscon_node_to_regmap(cfg_node); > > + if (IS_ERR(pcie->cfg)) > > + return PTR_ERR(pcie->cfg); > > + } > > + > > pcie->free_ck = devm_clk_get(dev, "free_ck"); > > if (IS_ERR(pcie->free_ck)) { > > if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) > > -- > > 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel