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Tue, 13 Oct 2020 20:44:34 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Oct 2020 21:44:31 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 12:44:30 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 12:44:30 +0800 Message-ID: <1602650671.27998.2.camel@mtksdaap41> Subject: Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema From: CK Hu To: Chunfeng Yun Date: Wed, 14 Oct 2020 12:44:31 +0800 In-Reply-To: <20201013085207.17749-4-chunfeng.yun@mediatek.com> References: <20201013085207.17749-1-chunfeng.yun@mediatek.com> <20201013085207.17749-4-chunfeng.yun@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201014_004543_388841_7023FBA8 X-CRM114-Status: GOOD ( 21.81 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , Philipp Zabel , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Mauro Carvalho Chehab , Vinod Koul , Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Chunfeng: On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote: > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > Signed-off-by: Chunfeng Yun > --- > v2: fix binding check warning of reg in example > --- > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+), 16 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > index 7b124242b0c5..edac18951a75 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > @@ -50,22 +50,7 @@ Required properties: > > HDMI PHY > ======== > - > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > -output and drives the HDMI pads. > - > -Required properties: > -- compatible: "mediatek,-hdmi-phy" > -- reg: Physical base address and length of the module's registers > -- clocks: PLL reference clock > -- clock-names: must contain "pll_ref" > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 > -- #phy-cells: must be <0> > -- #clock-cells: must be <0> > - > -Optional properties: > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > +See phy/mediatek,hdmi-phy.yaml > > Example: > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > new file mode 100644 > index 000000000000..77df50204606 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding > + > +maintainers: > + - CK Hu I think you should remove "CK Hu " and add latest mediatek drm maintainer: DRM DRIVERS FOR MEDIATEK M: Chun-Kuang Hu M: Philipp Zabel L: dri-devel@lists.freedesktop.org S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ Regards, CK > + - Chunfeng Yun > + > +description: | > + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > + output and drives the HDMI pads. > + > +properties: > + $nodename: > + pattern: "^hdmi-phy@[0-9a-f]+$" > + > + compatible: > + enum: > + - mediatek,mt2701-hdmi-phy > + - mediatek,mt8173-hdmi-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PLL reference clock > + > + clock-names: > + items: > + - const: pll_ref > + > + clock-output-names: > + items: > + - const: hdmitx_dig_cts > + > + "#phy-cells": > + const: 0 > + > + "#clock-cells": > + const: 0 > + > + mediatek,ibias: > + description: > + TX DRV bias current for < 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0xa > + > + mediatek,ibias_up: > + description: > + TX DRV bias current for >= 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0x1c > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names > + - "#phy-cells" > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + hdmi_phy: hdmi-phy@10209100 { > + compatible = "mediatek,mt8173-hdmi-phy"; > + reg = <0x10209100 0x24>; > + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; > + clock-names = "pll_ref"; > + clock-output-names = "hdmitx_dig_cts"; > + mediatek,ibias = <0xa>; > + mediatek,ibias_up = <0x1c>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + }; > + > +... _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31F78C43457 for ; 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X-UUID: 18ebda2e8bf74f3095a7a10152753375-20201014 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 262329850; Wed, 14 Oct 2020 12:44:32 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 12:44:30 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 12:44:30 +0800 Message-ID: <1602650671.27998.2.camel@mtksdaap41> Subject: Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema From: CK Hu To: Chunfeng Yun CC: Rob Herring , Chun-Kuang Hu , Philipp Zabel , "David Airlie" , Daniel Vetter , "Kishon Vijay Abraham I" , Vinod Koul , Matthias Brugger , Greg Kroah-Hartman , Mauro Carvalho Chehab , "David S . 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Message-ID: <1602650671.27998.2.camel@mtksdaap41> Subject: Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema From: CK Hu To: Chunfeng Yun Date: Wed, 14 Oct 2020 12:44:31 +0800 In-Reply-To: <20201013085207.17749-4-chunfeng.yun@mediatek.com> References: <20201013085207.17749-1-chunfeng.yun@mediatek.com> <20201013085207.17749-4-chunfeng.yun@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201014_004543_388841_7023FBA8 X-CRM114-Status: GOOD ( 21.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , Philipp Zabel , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Mauro Carvalho Chehab , Vinod Koul , Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Chunfeng: On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote: > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > Signed-off-by: Chunfeng Yun > --- > v2: fix binding check warning of reg in example > --- > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+), 16 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > index 7b124242b0c5..edac18951a75 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > @@ -50,22 +50,7 @@ Required properties: > > HDMI PHY > ======== > - > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > -output and drives the HDMI pads. > - > -Required properties: > -- compatible: "mediatek,-hdmi-phy" > -- reg: Physical base address and length of the module's registers > -- clocks: PLL reference clock > -- clock-names: must contain "pll_ref" > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 > -- #phy-cells: must be <0> > -- #clock-cells: must be <0> > - > -Optional properties: > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > +See phy/mediatek,hdmi-phy.yaml > > Example: > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > new file mode 100644 > index 000000000000..77df50204606 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding > + > +maintainers: > + - CK Hu I think you should remove "CK Hu " and add latest mediatek drm maintainer: DRM DRIVERS FOR MEDIATEK M: Chun-Kuang Hu M: Philipp Zabel L: dri-devel@lists.freedesktop.org S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ Regards, CK > + - Chunfeng Yun > + > +description: | > + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > + output and drives the HDMI pads. > + > +properties: > + $nodename: > + pattern: "^hdmi-phy@[0-9a-f]+$" > + > + compatible: > + enum: > + - mediatek,mt2701-hdmi-phy > + - mediatek,mt8173-hdmi-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PLL reference clock > + > + clock-names: > + items: > + - const: pll_ref > + > + clock-output-names: > + items: > + - const: hdmitx_dig_cts > + > + "#phy-cells": > + const: 0 > + > + "#clock-cells": > + const: 0 > + > + mediatek,ibias: > + description: > + TX DRV bias current for < 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0xa > + > + mediatek,ibias_up: > + description: > + TX DRV bias current for >= 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0x1c > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names > + - "#phy-cells" > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + hdmi_phy: hdmi-phy@10209100 { > + compatible = "mediatek,mt8173-hdmi-phy"; > + reg = <0x10209100 0x24>; > + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; > + clock-names = "pll_ref"; > + clock-output-names = "hdmitx_dig_cts"; > + mediatek,ibias = <0xa>; > + mediatek,ibias_up = <0x1c>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + }; > + > +... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA3FDC433DF for ; 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Wed, 14 Oct 2020 12:44:30 +0800 Message-ID: <1602650671.27998.2.camel@mtksdaap41> Subject: Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema From: CK Hu To: Chunfeng Yun Date: Wed, 14 Oct 2020 12:44:31 +0800 In-Reply-To: <20201013085207.17749-4-chunfeng.yun@mediatek.com> References: <20201013085207.17749-1-chunfeng.yun@mediatek.com> <20201013085207.17749-4-chunfeng.yun@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , Min Guo , devicetree@vger.kernel.org, David Airlie , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Mauro Carvalho Chehab , Vinod Koul , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Stanley Chu , "David S . Miller" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Chunfeng: On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote: > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml > > Signed-off-by: Chunfeng Yun > --- > v2: fix binding check warning of reg in example > --- > .../display/mediatek/mediatek,hdmi.txt | 17 +--- > .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+), 16 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > index 7b124242b0c5..edac18951a75 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt > @@ -50,22 +50,7 @@ Required properties: > > HDMI PHY > ======== > - > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > -output and drives the HDMI pads. > - > -Required properties: > -- compatible: "mediatek,-hdmi-phy" > -- reg: Physical base address and length of the module's registers > -- clocks: PLL reference clock > -- clock-names: must contain "pll_ref" > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 > -- #phy-cells: must be <0> > -- #clock-cells: must be <0> > - > -Optional properties: > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c > +See phy/mediatek,hdmi-phy.yaml > > Example: > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > new file mode 100644 > index 000000000000..77df50204606 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding > + > +maintainers: > + - CK Hu I think you should remove "CK Hu " and add latest mediatek drm maintainer: DRM DRIVERS FOR MEDIATEK M: Chun-Kuang Hu M: Philipp Zabel L: dri-devel@lists.freedesktop.org S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ Regards, CK > + - Chunfeng Yun > + > +description: | > + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel > + output and drives the HDMI pads. > + > +properties: > + $nodename: > + pattern: "^hdmi-phy@[0-9a-f]+$" > + > + compatible: > + enum: > + - mediatek,mt2701-hdmi-phy > + - mediatek,mt8173-hdmi-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PLL reference clock > + > + clock-names: > + items: > + - const: pll_ref > + > + clock-output-names: > + items: > + - const: hdmitx_dig_cts > + > + "#phy-cells": > + const: 0 > + > + "#clock-cells": > + const: 0 > + > + mediatek,ibias: > + description: > + TX DRV bias current for < 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0xa > + > + mediatek,ibias_up: > + description: > + TX DRV bias current for >= 1.65Gbps > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 63 > + default: 0x1c > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - clock-output-names > + - "#phy-cells" > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + hdmi_phy: hdmi-phy@10209100 { > + compatible = "mediatek,mt8173-hdmi-phy"; > + reg = <0x10209100 0x24>; > + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; > + clock-names = "pll_ref"; > + clock-output-names = "hdmitx_dig_cts"; > + mediatek,ibias = <0xa>; > + mediatek,ibias_up = <0x1c>; > + #clock-cells = <0>; > + #phy-cells = <0>; > + }; > + > +... _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel