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Mon, 02 Nov 2020 21:53:00 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 2 Nov 2020 21:44:13 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Nov 2020 13:44:03 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Nov 2020 13:44:02 +0800 Message-ID: <1604382242.2521.62.camel@mhfsdcap03> Subject: Re: [v3,2/3] PCI: mediatek: Add new generation controller support From: Jianjun Wang To: Philipp Zabel Date: Tue, 3 Nov 2020 13:44:02 +0800 In-Reply-To: References: <20200927074555.4155-1-jianjun.wang@mediatek.com> <20200927074555.4155-3-jianjun.wang@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 9C6198D0BAC2FA8D8B8BDDFFBAC2EDB7EF6F48FF231ECF7E375D29328861266A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201103_005918_454993_3F806804 X-CRM114-Status: GOOD ( 30.92 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , qizhong.cheng@mediatek.com, chuanjia.liu@mediatek.com, Mauro Carvalho Chehab , linux-pci@vger.kernel.org, Ryder Lee , linux-kernel@vger.kernel.org, Matthias Brugger , Sj Huang , Rob Herring , linux-mediatek@lists.infradead.org, Bjorn Helgaas , sin_jieyang@mediatek.com, davem@davemloft.net, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2020-09-28 at 10:32 +0200, Philipp Zabel wrote: > Hi Jianjun, > > On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote: > > MediaTek's PCIe host controller has three generation HWs, the new > > generation HW is an individual bridge, it supoorts Gen3 speed and > > up to 256 MSI interrupt numbers for multi-function devices. > > > > Add support for new Gen3 controller which can be found on MT8192. > > > > Signed-off-by: Jianjun Wang > > Acked-by: Ryder Lee > > --- > > drivers/pci/controller/Kconfig | 14 + > > drivers/pci/controller/Makefile | 1 + > > drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++++++++++++++++++ > > 3 files changed, 1039 insertions(+) > > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > > [...] > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > > new file mode 100644 > > index 000000000000..ad69c789b24d > > --- /dev/null > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -0,0 +1,1024 @@ > [...] > > +static int mtk_pcie_power_up(struct mtk_pcie_port *port) > > +{ > > + struct device *dev = port->dev; > > + int err; > > + > > + port->phy_reset = devm_reset_control_get_optional_exclusive(dev, > > + "phy-rst"); > > + if (IS_ERR(port->phy_reset)) > > + return PTR_ERR(port->phy_reset); > > + > > + reset_control_deassert(port->phy_reset); > > In general, it is better to request all required resources before > starting to activate the hardware. > > > + > > + /* PHY power on and enable pipe clock */ > > + port->phy = devm_phy_optional_get(dev, "pcie-phy"); > > + if (IS_ERR(port->phy)) > > + return PTR_ERR(port->phy); > > For example, if the PHY driver is not loaded yet and this returns > -EPROBE_DEFER, it was not useful to take the PHY out of reset above. > Also, phy-rst is kept deasserted if this fails. > > > + > > + err = phy_init(port->phy); > > + if (err) { > > + dev_notice(dev, "failed to initialize pcie phy\n"); > > + return err; > > phy-rst is kept deasserted if this fails. > > > + } > > + > > + err = phy_power_on(port->phy); > > + if (err) { > > + dev_notice(dev, "failed to power on pcie phy\n"); > > + goto err_phy_on; > > + } > > + > > + port->mac_reset = devm_reset_control_get_optional_exclusive(dev, > > + "mac-rst"); > > + if (IS_ERR(port->mac_reset)) > > + return PTR_ERR(port->mac_reset); > > The PHY is not powered down if this fails. > > > + > > + reset_control_deassert(port->mac_reset); > > + > > + /* MAC power on and enable transaction layer clocks */ > > + pm_runtime_enable(dev); > > + pm_runtime_get_sync(dev); > > + > > + err = mtk_pcie_clk_init(port); > > + if (err) { > > + dev_notice(dev, "clock init failed\n"); > > + goto err_clk_init; > > + } > > + > > + return 0; > > + > > +err_clk_init: > > + pm_runtime_put_sync(dev); > > + pm_runtime_disable(dev); > > + reset_control_assert(port->mac_reset); > > + phy_power_off(port->phy); > > +err_phy_on: > > + phy_exit(port->phy); > > + reset_control_assert(port->phy_reset); > > + > > + return -EBUSY; > > +} > > + > > +static void mtk_pcie_power_down(struct mtk_pcie_port *port) > > +{ > > + phy_power_off(port->phy); > > + phy_exit(port->phy); > > + > > + clk_bulk_disable_unprepare(port->num_clks, port->clks); > > In the power-up sequence clocks are enabled last, but here they are not > disabled before the PHY is powered off. Is this on purpose? > > > + > > + pm_runtime_put_sync(port->dev); > > + pm_runtime_disable(port->dev); > > In the power-up error path, PHY and controller resets are asserted > again, but here they are kept deasserted. Should they be asserted here > as well? > > regards > Philipp Hi Philipp, Sorry for the late responding and thanks for your review, I will fix it in the next version. Thanks. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01E7EC388F2 for ; Tue, 3 Nov 2020 05:44:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B4F8A222B9 for ; Tue, 3 Nov 2020 05:44:24 +0000 (UTC) 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Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2109648111; Tue, 03 Nov 2020 13:44:13 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Nov 2020 13:44:03 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Nov 2020 13:44:02 +0800 Message-ID: <1604382242.2521.62.camel@mhfsdcap03> Subject: Re: [v3,2/3] PCI: mediatek: Add new generation controller support From: Jianjun Wang To: Philipp Zabel CC: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee , Matthias Brugger , "Mauro Carvalho Chehab" , , , , , , , Sj Huang , , , , Date: Tue, 3 Nov 2020 13:44:02 +0800 In-Reply-To: References: <20200927074555.4155-1-jianjun.wang@mediatek.com> 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<1604382242.2521.62.camel@mhfsdcap03> Subject: Re: [v3,2/3] PCI: mediatek: Add new generation controller support From: Jianjun Wang To: Philipp Zabel Date: Tue, 3 Nov 2020 13:44:02 +0800 In-Reply-To: References: <20200927074555.4155-1-jianjun.wang@mediatek.com> <20200927074555.4155-3-jianjun.wang@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 9C6198D0BAC2FA8D8B8BDDFFBAC2EDB7EF6F48FF231ECF7E375D29328861266A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201103_005918_454993_3F806804 X-CRM114-Status: GOOD ( 30.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , qizhong.cheng@mediatek.com, chuanjia.liu@mediatek.com, Mauro Carvalho Chehab , linux-pci@vger.kernel.org, Ryder Lee , linux-kernel@vger.kernel.org, Matthias Brugger , Sj Huang , Rob Herring , linux-mediatek@lists.infradead.org, Bjorn Helgaas , sin_jieyang@mediatek.com, davem@davemloft.net, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2020-09-28 at 10:32 +0200, Philipp Zabel wrote: > Hi Jianjun, > > On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote: > > MediaTek's PCIe host controller has three generation HWs, the new > > generation HW is an individual bridge, it supoorts Gen3 speed and > > up to 256 MSI interrupt numbers for multi-function devices. > > > > Add support for new Gen3 controller which can be found on MT8192. > > > > Signed-off-by: Jianjun Wang > > Acked-by: Ryder Lee > > --- > > drivers/pci/controller/Kconfig | 14 + > > drivers/pci/controller/Makefile | 1 + > > drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++++++++++++++++++ > > 3 files changed, 1039 insertions(+) > > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > > [...] > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > > new file mode 100644 > > index 000000000000..ad69c789b24d > > --- /dev/null > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -0,0 +1,1024 @@ > [...] > > +static int mtk_pcie_power_up(struct mtk_pcie_port *port) > > +{ > > + struct device *dev = port->dev; > > + int err; > > + > > + port->phy_reset = devm_reset_control_get_optional_exclusive(dev, > > + "phy-rst"); > > + if (IS_ERR(port->phy_reset)) > > + return PTR_ERR(port->phy_reset); > > + > > + reset_control_deassert(port->phy_reset); > > In general, it is better to request all required resources before > starting to activate the hardware. > > > + > > + /* PHY power on and enable pipe clock */ > > + port->phy = devm_phy_optional_get(dev, "pcie-phy"); > > + if (IS_ERR(port->phy)) > > + return PTR_ERR(port->phy); > > For example, if the PHY driver is not loaded yet and this returns > -EPROBE_DEFER, it was not useful to take the PHY out of reset above. > Also, phy-rst is kept deasserted if this fails. > > > + > > + err = phy_init(port->phy); > > + if (err) { > > + dev_notice(dev, "failed to initialize pcie phy\n"); > > + return err; > > phy-rst is kept deasserted if this fails. > > > + } > > + > > + err = phy_power_on(port->phy); > > + if (err) { > > + dev_notice(dev, "failed to power on pcie phy\n"); > > + goto err_phy_on; > > + } > > + > > + port->mac_reset = devm_reset_control_get_optional_exclusive(dev, > > + "mac-rst"); > > + if (IS_ERR(port->mac_reset)) > > + return PTR_ERR(port->mac_reset); > > The PHY is not powered down if this fails. > > > + > > + reset_control_deassert(port->mac_reset); > > + > > + /* MAC power on and enable transaction layer clocks */ > > + pm_runtime_enable(dev); > > + pm_runtime_get_sync(dev); > > + > > + err = mtk_pcie_clk_init(port); > > + if (err) { > > + dev_notice(dev, "clock init failed\n"); > > + goto err_clk_init; > > + } > > + > > + return 0; > > + > > +err_clk_init: > > + pm_runtime_put_sync(dev); > > + pm_runtime_disable(dev); > > + reset_control_assert(port->mac_reset); > > + phy_power_off(port->phy); > > +err_phy_on: > > + phy_exit(port->phy); > > + reset_control_assert(port->phy_reset); > > + > > + return -EBUSY; > > +} > > + > > +static void mtk_pcie_power_down(struct mtk_pcie_port *port) > > +{ > > + phy_power_off(port->phy); > > + phy_exit(port->phy); > > + > > + clk_bulk_disable_unprepare(port->num_clks, port->clks); > > In the power-up sequence clocks are enabled last, but here they are not > disabled before the PHY is powered off. Is this on purpose? > > > + > > + pm_runtime_put_sync(port->dev); > > + pm_runtime_disable(port->dev); > > In the power-up error path, PHY and controller resets are asserted > again, but here they are kept deasserted. Should they be asserted here > as well? > > regards > Philipp Hi Philipp, Sorry for the late responding and thanks for your review, I will fix it in the next version. Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel