From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:39248 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728208AbeHVPk4 (ORCPT ); Wed, 22 Aug 2018 11:40:56 -0400 From: Laurent Pinchart To: Jacopo Mondi Cc: "open list:DRM DRIVERS FOR RENESAS" , "open list:DRM DRIVERS FOR RENESAS" Subject: Re: [PATCH 2/3] drm: rcar-du: Write ESCR register per channel Date: Wed, 22 Aug 2018 15:17:12 +0300 Message-ID: <1605837.B8ZfZIf33E@avalon> In-Reply-To: <1534922509-15197-3-git-send-email-jacopo+renesas@jmondi.org> References: <1534922509-15197-1-git-send-email-jacopo+renesas@jmondi.org> <1534922509-15197-3-git-send-email-jacopo+renesas@jmondi.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Jacopo, Thank you for the patch. On Wednesday, 22 August 2018 10:21:48 EEST Jacopo Mondi wrote: > The ESCR registers offset definition is confusing, as each channel is > equipped with an ESCR register instance, but the names suggest only ESCR and > ESCR2 are taken into account. > > Rename the offsets to a name that includes the channels they apply to, and > write them to each channel with 'rcar_du_crtc_write()'. > > Cosmetic patch, no functional changes intended. I think patches 2/3 and 3/3 can be squashed together, there's no real reason to keep them separate. I propose updating the commit message to "drm: rcar-du: Write ESCR and OTAR as CRTC registers The ESCR and OTAR registers exist in each DU channel, but at different offsets for odd and even channels. This led to usage of the group register access API to write them, with offsets macros named ESCR/OTAR and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group respectively. The names are confusing as it suggests that the ESCR/OTAR registers for DU0 and DU2 are taken into account, especially with writes performed to the group register access API. Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC register access API to clarify the code. The offsets values are updated accordingly. Cosmetic patch, no functional changes intended." Otherwise the patches look good to me, so Reviewed-by: Laurent Pinchart and applied the squashed version to my tree. > Signed-off-by: Jacopo Mondi > --- > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +-- > drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++-- > 2 files changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 5454884..714c1fc 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > @@ -294,8 +294,7 @@ static void rcar_du_crtc_set_display_timing(struct > rcar_du_crtc *rcrtc) } > } > > - rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR, > - escr); > + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); > rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0); > > /* Signal polarities */ > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h > b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index 9dfd220..ebc4aea 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h > +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h > @@ -492,8 +492,8 @@ > * External Synchronization Control Registers > */ > > -#define ESCR 0x10000 > -#define ESCR2 0x31000 > +#define ESCR02 0x10000 > +#define ESCR13 0x01000 > #define ESCR_DCLKOINV (1 << 25) > #define ESCR_DCLKSEL_DCLKIN (0 << 20) > #define ESCR_DCLKSEL_CLKS (1 << 20) -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 2/3] drm: rcar-du: Write ESCR register per channel Date: Wed, 22 Aug 2018 15:17:12 +0300 Message-ID: <1605837.B8ZfZIf33E@avalon> References: <1534922509-15197-1-git-send-email-jacopo+renesas@jmondi.org> <1534922509-15197-3-git-send-email-jacopo+renesas@jmondi.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F6586E368 for ; Wed, 22 Aug 2018 12:16:15 +0000 (UTC) In-Reply-To: <1534922509-15197-3-git-send-email-jacopo+renesas@jmondi.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jacopo Mondi Cc: "open list:DRM DRIVERS FOR RENESAS" , "open list:DRM DRIVERS FOR RENESAS" List-Id: dri-devel@lists.freedesktop.org SGkgSmFjb3BvLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBXZWRuZXNkYXksIDIyIEF1 Z3VzdCAyMDE4IDEwOjIxOjQ4IEVFU1QgSmFjb3BvIE1vbmRpIHdyb3RlOgo+IFRoZSBFU0NSIHJl Z2lzdGVycyBvZmZzZXQgZGVmaW5pdGlvbiBpcyBjb25mdXNpbmcsIGFzIGVhY2ggY2hhbm5lbCBp cwo+IGVxdWlwcGVkIHdpdGggYW4gRVNDUiByZWdpc3RlciBpbnN0YW5jZSwgYnV0IHRoZSBuYW1l cyBzdWdnZXN0IG9ubHkgRVNDUiBhbmQKPiBFU0NSMiBhcmUgdGFrZW4gaW50byBhY2NvdW50Lgo+ IAo+IFJlbmFtZSB0aGUgb2Zmc2V0cyB0byBhIG5hbWUgdGhhdCBpbmNsdWRlcyB0aGUgY2hhbm5l bHMgdGhleSBhcHBseSB0bywgYW5kCj4gd3JpdGUgdGhlbSB0byBlYWNoIGNoYW5uZWwgd2l0aCAn cmNhcl9kdV9jcnRjX3dyaXRlKCknLgo+IAo+IENvc21ldGljIHBhdGNoLCBubyBmdW5jdGlvbmFs IGNoYW5nZXMgaW50ZW5kZWQuCgpJIHRoaW5rIHBhdGNoZXMgMi8zIGFuZCAzLzMgY2FuIGJlIHNx dWFzaGVkIHRvZ2V0aGVyLCB0aGVyZSdzIG5vIHJlYWwgcmVhc29uIAp0byBrZWVwIHRoZW0gc2Vw YXJhdGUuIEkgcHJvcG9zZSB1cGRhdGluZyB0aGUgY29tbWl0IG1lc3NhZ2UgdG8KCiJkcm06IHJj YXItZHU6IFdyaXRlIEVTQ1IgYW5kIE9UQVIgYXMgQ1JUQyByZWdpc3RlcnMgCiAgClRoZSBFU0NS IGFuZCBPVEFSIHJlZ2lzdGVycyBleGlzdCBpbiBlYWNoIERVIGNoYW5uZWwsIGJ1dCBhdCBkaWZm ZXJlbnQgCm9mZnNldHMgZm9yIG9kZCBhbmQgZXZlbiBjaGFubmVscy4gVGhpcyBsZWQgdG8gdXNh Z2Ugb2YgdGhlIGdyb3VwIApyZWdpc3RlciBhY2Nlc3MgQVBJIHRvIHdyaXRlIHRoZW0sIHdpdGgg b2Zmc2V0cyBtYWNyb3MgbmFtZWQgRVNDUi9PVEFSIAphbmQgRVNDUjIvT1RBUjIgZm9yIHRoZSBm aXJzdCBhbmQgc2Vjb25kIEVTQ1IvT1RBUiByZWdpc3RlciBpbiB0aGUgZ3JvdXAgCnJlc3BlY3Rp dmVseS4KClRoZSBuYW1lcyBhcmUgY29uZnVzaW5nIGFzIGl0IHN1Z2dlc3RzIHRoYXQgdGhlIEVT Q1IvT1RBUiByZWdpc3RlcnMgZm9yIApEVTAgYW5kIERVMiBhcmUgdGFrZW4gaW50byBhY2NvdW50 LCBlc3BlY2lhbGx5IHdpdGggd3JpdGVzIHBlcmZvcm1lZCB0bwp0aGUgZ3JvdXAgcmVnaXN0ZXIg YWNjZXNzIEFQSS4KClJlbmFtZSB0aGUgb2Zmc2V0cyB0byBFU0NSL09UQVIwMiBhbmQgRVNDUi9P VEFSMTMsIGFuZCB1c2UgdGhlIENSVEMgCnJlZ2lzdGVyIGFjY2VzcyBBUEkgdG8gY2xhcmlmeSB0 aGUgY29kZS4gVGhlIG9mZnNldHMgdmFsdWVzIGFyZSB1cGRhdGVkIAphY2NvcmRpbmdseS4KCkNv c21ldGljIHBhdGNoLCBubyBmdW5jdGlvbmFsIGNoYW5nZXMgaW50ZW5kZWQuIgoKT3RoZXJ3aXNl IHRoZSBwYXRjaGVzIGxvb2sgZ29vZCB0byBtZSwgc28KClJldmlld2VkLWJ5OiBMYXVyZW50IFBp bmNoYXJ0IDxsYXVyZW50LnBpbmNoYXJ0QGlkZWFzb25ib2FyZC5jb20+CgphbmQgYXBwbGllZCB0 aGUgc3F1YXNoZWQgdmVyc2lvbiB0byBteSB0cmVlLgoKPiBTaWduZWQtb2ZmLWJ5OiBKYWNvcG8g TW9uZGkgPGphY29wbytyZW5lc2FzQGptb25kaS5vcmc+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2Ry bS9yY2FyLWR1L3JjYXJfZHVfY3J0Yy5jIHwgMyArLS0KPiAgZHJpdmVycy9ncHUvZHJtL3JjYXIt ZHUvcmNhcl9kdV9yZWdzLmggfCA0ICsrLS0KPiAgMiBmaWxlcyBjaGFuZ2VkLCAzIGluc2VydGlv bnMoKyksIDQgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9y Y2FyLWR1L3JjYXJfZHVfY3J0Yy5jCj4gYi9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1 X2NydGMuYyBpbmRleCA1NDU0ODg0Li43MTRjMWZjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9yY2FyLWR1L3JjYXJfZHVfY3J0Yy5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JjYXIt ZHUvcmNhcl9kdV9jcnRjLmMKPiBAQCAtMjk0LDggKzI5NCw3IEBAIHN0YXRpYyB2b2lkIHJjYXJf ZHVfY3J0Y19zZXRfZGlzcGxheV90aW1pbmcoc3RydWN0Cj4gcmNhcl9kdV9jcnRjICpyY3J0Yykg fQo+ICAJfQo+IAo+IC0JcmNhcl9kdV9ncm91cF93cml0ZShyY3J0Yy0+Z3JvdXAsIHJjcnRjLT5p bmRleCAlIDIgPyBFU0NSMiA6IEVTQ1IsCj4gLQkJCSAgICBlc2NyKTsKPiArCXJjYXJfZHVfY3J0 Y193cml0ZShyY3J0YywgcmNydGMtPmluZGV4ICUgMiA/IEVTQ1IxMyA6IEVTQ1IwMiwgZXNjcik7 Cj4gIAlyY2FyX2R1X2dyb3VwX3dyaXRlKHJjcnRjLT5ncm91cCwgcmNydGMtPmluZGV4ICUgMiA/ IE9UQVIyIDogT1RBUiwgMCk7Cj4gCj4gIAkvKiBTaWduYWwgcG9sYXJpdGllcyAqLwo+IGRpZmYg LS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X3JlZ3MuaAo+IGIvZHJpdmVy cy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9yZWdzLmggaW5kZXggOWRmZDIyMC4uZWJjNGFlYSAx MDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X3JlZ3MuaAo+ICsr KyBiL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfcmVncy5oCj4gQEAgLTQ5Miw4ICs0 OTIsOCBAQAo+ICAgKiBFeHRlcm5hbCBTeW5jaHJvbml6YXRpb24gQ29udHJvbCBSZWdpc3RlcnMK PiAgICovCj4gCj4gLSNkZWZpbmUgRVNDUgkJCTB4MTAwMDAKPiAtI2RlZmluZSBFU0NSMgkJCTB4 MzEwMDAKPiArI2RlZmluZSBFU0NSMDIJCQkweDEwMDAwCj4gKyNkZWZpbmUgRVNDUjEzCQkJMHgw MTAwMAo+ICAjZGVmaW5lIEVTQ1JfRENMS09JTlYJCSgxIDw8IDI1KQo+ICAjZGVmaW5lIEVTQ1Jf RENMS1NFTF9EQ0xLSU4JKDAgPDwgMjApCj4gICNkZWZpbmUgRVNDUl9EQ0xLU0VMX0NMS1MJKDEg PDwgMjApCgotLSAKUmVnYXJkcywKCkxhdXJlbnQgUGluY2hhcnQKCgoKX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApk cmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Au b3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==