From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from galahad.ideasonboard.com ([185.26.127.97]:35056 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754965AbeDFNrZ (ORCPT ); Fri, 6 Apr 2018 09:47:25 -0400 From: Laurent Pinchart To: Jacopo Mondi Cc: horms@verge.net.au, magnus.damm@gmail.com, geert@linux-m68k.org, niklas.soderlund@ragnatech.se, sergei.shtylyov@cogentembedded.com, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/7] arm64: dts: renesas: eagle: Enable DU Date: Fri, 06 Apr 2018 16:47:23 +0300 Message-ID: <1607257.kzKzzg5gBe@avalon> In-Reply-To: <35431593.B1LTs037XF@avalon> References: <1523020092-25540-1-git-send-email-jacopo+renesas@jmondi.org> <1523020092-25540-6-git-send-email-jacopo+renesas@jmondi.org> <35431593.B1LTs037XF@avalon> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi again, On Friday, 6 April 2018 16:45:16 EEST Laurent Pinchart wrote: > On Friday, 6 April 2018 16:08:10 EEST Jacopo Mondi wrote: > > Enable DU for Renesas R-Car V3M Eagle board. > > > > Signed-off-by: Jacopo Mondi > > --- > > > > arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > > b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 3c5f598..144b847 > > 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > > +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts > > @@ -76,6 +76,11 @@ > > > > function = "i2c0"; > > > > }; > > > > + du_pins: du { > > + groups = "du_rgb666", "du_sync", "du_oddf", "du_clk_out"; > > + function = "du"; > > + }; > > As far as I can tell the DU parallel output isn't used on the Eagle board, > but is used on the Eagle expansion board. I would move this to patch 7/7 in > this series. My bad, patch 7/7 describes the on-board HDMI encoder, not the one on the expansion board. I would thus drop pinmux completely for now until we add support for the expansion board. > > scif0_pins: scif0 { > > > > groups = "scif0_data"; > > function = "scif0"; > > > > @@ -93,3 +98,9 @@ > > > > status = "okay"; > > > > }; > > > > + > > +&du { > > + pinctrl-0 = <&du_pins>; > > + pinctrl-names = "default"; > > These two properties should be moved to patch 7/7 too. So this should be removed. > > + status = "okay"; > > +}; > > There's little use for enabling the DU in DT if you have no output port > described. I'd move this to patch 6/7. And I'd merge the status attribute and patches 6/7 and 7/7 all together. -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH 5/7] arm64: dts: renesas: eagle: Enable DU Date: Fri, 06 Apr 2018 16:47:23 +0300 Message-ID: <1607257.kzKzzg5gBe@avalon> References: <1523020092-25540-1-git-send-email-jacopo+renesas@jmondi.org> <1523020092-25540-6-git-send-email-jacopo+renesas@jmondi.org> <35431593.B1LTs037XF@avalon> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <35431593.B1LTs037XF@avalon> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jacopo Mondi Cc: devicetree@vger.kernel.org, sergei.shtylyov@cogentembedded.com, magnus.damm@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, horms@verge.net.au, geert@linux-m68k.org, niklas.soderlund@ragnatech.se List-Id: devicetree@vger.kernel.org SGkgYWdhaW4sCgpPbiBGcmlkYXksIDYgQXByaWwgMjAxOCAxNjo0NToxNiBFRVNUIExhdXJlbnQg UGluY2hhcnQgd3JvdGU6Cj4gT24gRnJpZGF5LCA2IEFwcmlsIDIwMTggMTY6MDg6MTAgRUVTVCBK YWNvcG8gTW9uZGkgd3JvdGU6Cj4gPiBFbmFibGUgRFUgZm9yIFJlbmVzYXMgUi1DYXIgVjNNIEVh Z2xlIGJvYXJkLgo+ID4gCj4gPiBTaWduZWQtb2ZmLWJ5OiBKYWNvcG8gTW9uZGkgPGphY29wbyty ZW5lc2FzQGptb25kaS5vcmc+Cj4gPiAtLS0KPiA+IAo+ID4gIGFyY2gvYXJtNjQvYm9vdC9kdHMv cmVuZXNhcy9yOGE3Nzk3MC1lYWdsZS5kdHMgfCAxMSArKysrKysrKysrKwo+ID4gIDEgZmlsZSBj aGFuZ2VkLCAxMSBpbnNlcnRpb25zKCspCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0 L2Jvb3QvZHRzL3JlbmVzYXMvcjhhNzc5NzAtZWFnbGUuZHRzCj4gPiBiL2FyY2gvYXJtNjQvYm9v dC9kdHMvcmVuZXNhcy9yOGE3Nzk3MC1lYWdsZS5kdHMgaW5kZXggM2M1ZjU5OC4uMTQ0Yjg0Nwo+ ID4gMTAwNjQ0Cj4gPiAtLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL3JlbmVzYXMvcjhhNzc5NzAt ZWFnbGUuZHRzCj4gPiArKysgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL3JlbmVzYXMvcjhhNzc5NzAt ZWFnbGUuZHRzCj4gPiBAQCAtNzYsNiArNzYsMTEgQEAKPiA+IAo+ID4gIAkJZnVuY3Rpb24gPSAi aTJjMCI7Cj4gPiAgCQo+ID4gIAl9Owo+ID4gCj4gPiArCWR1X3BpbnM6IGR1IHsKPiA+ICsJCWdy b3VwcyA9ICJkdV9yZ2I2NjYiLCAiZHVfc3luYyIsICJkdV9vZGRmIiwgImR1X2Nsa19vdXQiOwo+ ID4gKwkJZnVuY3Rpb24gPSAiZHUiOwo+ID4gKwl9Owo+IAo+IEFzIGZhciBhcyBJIGNhbiB0ZWxs IHRoZSBEVSBwYXJhbGxlbCBvdXRwdXQgaXNuJ3QgdXNlZCBvbiB0aGUgRWFnbGUgYm9hcmQsCj4g YnV0IGlzIHVzZWQgb24gdGhlIEVhZ2xlIGV4cGFuc2lvbiBib2FyZC4gSSB3b3VsZCBtb3ZlIHRo aXMgdG8gcGF0Y2ggNy83IGluCj4gdGhpcyBzZXJpZXMuCgpNeSBiYWQsIHBhdGNoIDcvNyBkZXNj cmliZXMgdGhlIG9uLWJvYXJkIEhETUkgZW5jb2Rlciwgbm90IHRoZSBvbmUgb24gdGhlIApleHBh bnNpb24gYm9hcmQuIEkgd291bGQgdGh1cyBkcm9wIHBpbm11eCBjb21wbGV0ZWx5IGZvciBub3cg dW50aWwgd2UgYWRkIApzdXBwb3J0IGZvciB0aGUgZXhwYW5zaW9uIGJvYXJkLgoKPiA+ICAJc2Np ZjBfcGluczogc2NpZjAgewo+ID4gIAkKPiA+ICAJCWdyb3VwcyA9ICJzY2lmMF9kYXRhIjsKPiA+ ICAJCWZ1bmN0aW9uID0gInNjaWYwIjsKPiA+IAo+ID4gQEAgLTkzLDMgKzk4LDkgQEAKPiA+IAo+ ID4gIAlzdGF0dXMgPSAib2theSI7Cj4gPiAgCj4gPiAgfTsKPiA+IAo+ID4gKwo+ID4gKyZkdSB7 Cj4gPiArCXBpbmN0cmwtMCA9IDwmZHVfcGlucz47Cj4gPiArCXBpbmN0cmwtbmFtZXMgPSAiZGVm YXVsdCI7Cj4gCj4gVGhlc2UgdHdvIHByb3BlcnRpZXMgc2hvdWxkIGJlIG1vdmVkIHRvIHBhdGNo IDcvNyB0b28uCgpTbyB0aGlzIHNob3VsZCBiZSByZW1vdmVkLgoKPiA+ICsJc3RhdHVzID0gIm9r YXkiOwo+ID4gK307Cj4gCj4gVGhlcmUncyBsaXR0bGUgdXNlIGZvciBlbmFibGluZyB0aGUgRFUg aW4gRFQgaWYgeW91IGhhdmUgbm8gb3V0cHV0IHBvcnQKPiBkZXNjcmliZWQuIEknZCBtb3ZlIHRo aXMgdG8gcGF0Y2ggNi83LgoKQW5kIEknZCBtZXJnZSB0aGUgc3RhdHVzIGF0dHJpYnV0ZSBhbmQg cGF0Y2hlcyA2LzcgYW5kIDcvNyBhbGwgdG9nZXRoZXIuCgotLSAKUmVnYXJkcywKCkxhdXJlbnQg UGluY2hhcnQKCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVs Cg==