diff for duplicates of <1608479.lxyeMomFsd@diego> diff --git a/a/1.txt b/N1/1.txt index 73ce96a..dcbfe93 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,10 +1,8 @@ -Am Samstag, 26. M=E4rz 2016, 14:37:53 schrieb Xing Zheng: -> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPL= -L, -> there is incorrect to select bit_0 and bit_1 as the main and alternat= -e +Am Samstag, 26. März 2016, 14:37:53 schrieb Xing Zheng: +> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL, +> there is incorrect to select bit_0 and bit_1 as the main and alternate > parents for LPLL/BPLL. They should be configurable. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> I've folded this fix into the original patch [0] @@ -14,6 +12,4 @@ Thanks Heiko -[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g= -it/commit/?h=3Dv4.7-clk/next&id=3D268aebaa2410152bf91ea1ede6b284ff81388= -22d +[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d diff --git a/a/content_digest b/N1/content_digest index a68b8ee..1f2c52a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -16,13 +16,11 @@ " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" - "Am Samstag, 26. M=E4rz 2016, 14:37:53 schrieb Xing Zheng:\n" - "> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPL=\n" - "L,\n" - "> there is incorrect to select bit_0 and bit_1 as the main and alternat=\n" - "e\n" + "Am Samstag, 26. M\303\244rz 2016, 14:37:53 schrieb Xing Zheng:\n" + "> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,\n" + "> there is incorrect to select bit_0 and bit_1 as the main and alternate\n" "> parents for LPLL/BPLL. They should be configurable.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" "I've folded this fix into the original patch [0]\n" @@ -32,8 +30,6 @@ "Heiko\n" "\n" "\n" - "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g=\n" - "it/commit/?h=3Dv4.7-clk/next&id=3D268aebaa2410152bf91ea1ede6b284ff81388=\n" - 22d + [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d -b8dfd2375b91337aeefe2f20ec5a0d26c931f89e191d40742186e0a613580d88 +e5333650a97e68711a975d41809d5591f8e3a45c239150aa95250371ff5abe3d
diff --git a/a/1.txt b/N2/1.txt index 73ce96a..a2b9afd 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,10 +1,8 @@ -Am Samstag, 26. M=E4rz 2016, 14:37:53 schrieb Xing Zheng: -> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPL= -L, -> there is incorrect to select bit_0 and bit_1 as the main and alternat= -e +Am Samstag, 26. M?rz 2016, 14:37:53 schrieb Xing Zheng: +> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL, +> there is incorrect to select bit_0 and bit_1 as the main and alternate > parents for LPLL/BPLL. They should be configurable. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> I've folded this fix into the original patch [0] @@ -14,6 +12,4 @@ Thanks Heiko -[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g= -it/commit/?h=3Dv4.7-clk/next&id=3D268aebaa2410152bf91ea1ede6b284ff81388= -22d +[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d diff --git a/a/content_digest b/N2/content_digest index a68b8ee..22dc943 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,28 +1,16 @@ "ref\01458974276-10325-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01458974276-10325-2-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed\0" "Date\0Sun, 27 Mar 2016 23:26:52 +0200\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - dianders@chromium.org - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "Am Samstag, 26. M=E4rz 2016, 14:37:53 schrieb Xing Zheng:\n" - "> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPL=\n" - "L,\n" - "> there is incorrect to select bit_0 and bit_1 as the main and alternat=\n" - "e\n" + "Am Samstag, 26. M?rz 2016, 14:37:53 schrieb Xing Zheng:\n" + "> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,\n" + "> there is incorrect to select bit_0 and bit_1 as the main and alternate\n" "> parents for LPLL/BPLL. They should be configurable.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" "I've folded this fix into the original patch [0]\n" @@ -32,8 +20,6 @@ "Heiko\n" "\n" "\n" - "[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.g=\n" - "it/commit/?h=3Dv4.7-clk/next&id=3D268aebaa2410152bf91ea1ede6b284ff81388=\n" - 22d + [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d -b8dfd2375b91337aeefe2f20ec5a0d26c931f89e191d40742186e0a613580d88 +4bb17066565da3f33a3f1bd074fef8ffa0f41625661834c3649c904cf905d187
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