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[193.116.97.30]) by smtp.gmail.com with ESMTPSA id m15sm30666412pfa.72.2020.12.26.00.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Dec 2020 00:19:10 -0800 (PST) Date: Sat, 26 Dec 2020 18:19:04 +1000 From: Nicholas Piggin Subject: Re: [PATCH v3 03/19] powerpc: bad_page_fault, do_break get registers from regs To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20201128144114.944000-1-npiggin@gmail.com> <20201128144114.944000-4-npiggin@gmail.com> <312d3d14-329c-a0c9-89c4-e21d1f9e616d@csgroup.eu> In-Reply-To: <312d3d14-329c-a0c9-89c4-e21d1f9e616d@csgroup.eu> MIME-Version: 1.0 Message-Id: <1608970380.delquel806.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of December 23, 2020 12:42 am: >=20 >=20 > Le 28/11/2020 =C3=A0 15:40, Nicholas Piggin a =C3=A9crit=C2=A0: >> Similar to the previous patch this makes interrupt handler function >> types more regular so they can be wrapped with the next patch. >>=20 >> bad_page_fault and do_break are not performance critical. >=20 > I partly took your changes into one of my series, in different order thou= gh. >=20 > Please have a look at https://patchwork.ozlabs.org/project/linuxppc-dev/l= ist/?series=3D221656 patches=20 > 4 to 7 Thanks, I had a look. Seems like the result is basically the same as my=20 series, so that's good if you like the end result now :) > I think some of the changes are missing in your series, especially the ch= anges in entry_32.S from=20 > patch 7. Okay I could take them in. In your patch 7/15, why do you leave this=20 load of DSISR? diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/hea= d_book3s_32.S index 15e6003fd3b8..0133a02d1d47 100644 --- a/arch/powerpc/kernel/head_book3s_32.S +++ b/arch/powerpc/kernel/head_book3s_32.S @@ -369,9 +369,9 @@ BEGIN_MMU_FTR_SECTION END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE) #endif #endif /* CONFIG_VMAP_STACK */ -1: mr r4,r12 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ - stw r4, _DAR(r11) + stw r12, _DAR(r11) + stw r5, _DSISR(r11) EXC_XFER_LITE(0x400, handle_page_fault) =20 /* External interrupt */ @@ -693,7 +693,6 @@ handle_page_fault_tramp_1: #ifdef CONFIG_VMAP_STACK EXCEPTION_PROLOG_2 handle_dar_dsisr=3D1 #endif - lwz r4, _DAR(r11) lwz r5, _DSISR(r11) ^^^^^^^^^^^^^^^^^^^^^^ /* fall through */ handle_page_fault_tramp_2: ? > Will see how our two series make their way into mainline, yours needs reb= ase anyway. I have it rebased, just waiting for a bit after merge window to repost. Would be good if mine can go first so I don't have to redo the 64s page=20 fault to C conversion again. AFAIKS after that you can just drop 4-7, no=20 conflicts? (after bugs are fixed) Thanks, Nick