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Tue, 12 Jan 2021 00:46:49 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 00:41:31 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 16:41:29 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Jan 2021 16:41:29 +0800 Message-ID: <1610440889.1140.9.camel@mtksdaap41> Subject: Re: [PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU From: Nick Fan To: Steven Price Date: Tue, 12 Jan 2021 16:41:29 +0800 In-Reply-To: <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> References: <20210105053632.5476-1-Nick.Fan@mediatek.com> <20210105053632.5476-2-Nick.Fan@mediatek.com> <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210112_034652_274773_9D26560E X-CRM114-Status: GOOD ( 21.49 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Fri, 2021-01-08 at 15:58 +0000, Steven Price wrote: > On 05/01/2021 05:36, Nick Fan wrote: > > Add a basic GPU node for mt8192. > > > > Signed-off-by: Nick Fan > > --- > > This patch depends on Mediatek power and regulator support. > > > > Listed as following. > > > > [1]https://lore.kernel.org/patchwork/patch/1336293/ > > [2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013 > > [3]https://lore.kernel.org/patchwork/patch/1356037/ > > [4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777 > > [5]https://lore.kernel.org/patchwork/patch/1356175/ > > [6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.wang@mediatek.com/ > > [7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.wang@mediatek.com/ > > --- > > --- > > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 176 ++++++++++++++++++++ > > 2 files changed, 183 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > index 6c1e2b3e8a60..48c0e240dd92 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > @@ -5,6 +5,7 @@ > > */ > > /dts-v1/; > > #include "mt8192.dtsi" > > +#include "mt6359.dtsi" > > > > / { > > model = "MediaTek MT8192 evaluation board"; > > @@ -70,6 +71,12 @@ > > }; > > }; > > > > +&gpu { > > + supply-names = "mali","sram"; > > + mali-supply = <&mt6315_7_vbuck1>; > > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > > +}; > > + > > &uart0 { > > status = "okay"; > > }; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index d6a4ad242a33..de166ea750af 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -822,6 +822,182 @@ > > #clock-cells = <1>; > > }; > > > > + gpu: mali@13000000 { > > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > > + reg = <0 0x13000000 0 0x4000>; > > + interrupts = > > + , > > + , > > + , > > + , > > + ; > > + interrupt-names = > > + "GPU", > > + "MMU", > > + "JOB", > > + "EVENT", > > + "PWR"; > > These interrupt names don't match the binding you've posted (GPU, MMU, > JOB are upper case here, lower case in the binding). Also EVENT and PWR > are not mentioned in the binding - should they be? > > I know there are differences here between kbase's requirements and the > existing upstream bindings (case specifically), but I haven't seen a > binding containing EVENT and PWR before. > > Steve > Thanks for your comment. Yes, the EVENT and PWR should be removed. And the rest of interrupt names are corrected to lower case. Please check my updated version 4 for this. https://lore.kernel.org/patchwork/patch/1363862/ Nick Fan > > + > > + clocks = > > + <&apmixedsys CLK_APMIXED_MFGPLL>, > > + <&topckgen CLK_TOP_MFG_PLL_SEL>, > > + <&topckgen CLK_TOP_MFG_REF_SEL>, > > + <&mfgcfg CLK_MFG_BG3D>; > > + clock-names = > > + "clk_main_parent", > > + "clk_mux", > > + "clk_sub_parent", > > + "subsys_mfg_cg"; > > + > > + power-domains = > > + <&scpsys MT8192_POWER_DOMAIN_MFG2>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG3>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG4>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG5>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG6>; > > + power-domain-names = "core0", > > + "core1", > > + "core2", > > + "core3", > > + "core4"; > > + > > + operating-points-v2 = <&gpu_opp_table>; > > + #cooling-cells = <2>; > > + }; > > + > > + gpu_opp_table: opp_table0 { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-358000000 { > > + opp-hz = /bits/ 64 <358000000>; > > + opp-hz-real = /bits/ 64 <358000000>, > > + /bits/ 64 <358000000>; > > + opp-microvolt = <606250>, > > + <750000>; > > + }; > > + > > + opp-399000000 { > > + opp-hz = /bits/ 64 <399000000>; > > + opp-hz-real = /bits/ 64 <399000000>, > > + /bits/ 64 <399000000>; > > + opp-microvolt = <618750>, > > + <750000>; > > + }; > > + > > + opp-440000000 { > > + opp-hz = /bits/ 64 <440000000>; > > + opp-hz-real = /bits/ 64 <440000000>, > > + /bits/ 64 <440000000>; > > + opp-microvolt = <631250>, > > + <750000>; > > + }; > > + > > + opp-482000000 { > > + opp-hz = /bits/ 64 <482000000>; > > + opp-hz-real = /bits/ 64 <482000000>, > > + /bits/ 64 <482000000>; > > + opp-microvolt = <643750>, > > + <750000>; > > + }; > > + > > + opp-523000000 { > > + opp-hz = /bits/ 64 <523000000>; > > + opp-hz-real = /bits/ 64 <523000000>, > > + /bits/ 64 <523000000>; > > + opp-microvolt = <656250>, > > + <750000>; > > + }; > > + > > + opp-564000000 { > > + opp-hz = /bits/ 64 <564000000>; > > + opp-hz-real = /bits/ 64 <564000000>, > > + /bits/ 64 <564000000>; > > + opp-microvolt = <668750>, > > + <750000>; > > + }; > > + > > + opp-605000000 { > > + opp-hz = /bits/ 64 <605000000>; > > + opp-hz-real = /bits/ 64 <605000000>, > > + /bits/ 64 <605000000>; > > + opp-microvolt = <681250>, > > + <750000>; > > + }; > > + > > + opp-647000000 { > > + opp-hz = /bits/ 64 <647000000>; > > + opp-hz-real = /bits/ 64 <647000000>, > > + /bits/ 64 <647000000>; > > + opp-microvolt = <693750>, > > + <750000>; > > + }; > > + > > + opp-688000000 { > > + opp-hz = /bits/ 64 <688000000>; > > + opp-hz-real = /bits/ 64 <688000000>, > > + /bits/ 64 <688000000>; > > + opp-microvolt = <706250>, > > + <750000>; > > + }; > > + > > + opp-724000000 { > > + opp-hz = /bits/ 64 <724000000>; > > + opp-hz-real = /bits/ 64 <724000000>, > > + /bits/ 64 <724000000>; > > + opp-microvolt = <725000>, > > + <750000>; > > + }; > > + > > + opp-760000000 { > > + opp-hz = /bits/ 64 <760000000>; > > + opp-hz-real = /bits/ 64 <760000000>, > > + /bits/ 64 <760000000>; > > + opp-microvolt = <743750>, > > + <750000>; > > + }; > > + > > + opp-795000000 { > > + opp-hz = /bits/ 64 <795000000>; > > + opp-hz-real = /bits/ 64 <795000000>, > > + /bits/ 64 <795000000>; > > + opp-microvolt = <762500>, > > + <762500>; > > + }; > > + > > + opp-831000000 { > > + opp-hz = /bits/ 64 <831000000>; > > + opp-hz-real = /bits/ 64 <831000000>, > > + /bits/ 64 <831000000>; > > + opp-microvolt = <781250>, > > + <781250>; > > + }; > > + > > + opp-855000000 { > > + opp-hz = /bits/ 64 <855000000>; > > + opp-hz-real = /bits/ 64 <855000000>, > > + /bits/ 64 <855000000>; > > + opp-microvolt = <793750>, > > + <793750>; > > + }; > > + > > + opp-902000000 { > > + opp-hz = /bits/ 64 <902000000>; > > + opp-hz-real = /bits/ 64 <902000000>, > > + /bits/ 64 <902000000>; > > + opp-microvolt = <818750>, > > + <818750>; > > + }; > > + > > + opp-950000000 { > > + opp-hz = /bits/ 64 <950000000>; > > + opp-hz-real = /bits/ 64 <950000000>, > > + /bits/ 64 <950000000>; > > + opp-microvolt = <843750>, > > + <843750>; > > + }; > > + }; > > + > > mfgcfg: syscon@13fbf000 { > > compatible = "mediatek,mt8192-mfgcfg", "syscon"; > > reg = <0 0x13fbf000 0 0x1000>; > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6233C433E0 for ; Tue, 12 Jan 2021 08:48:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 539A522D58 for ; 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Tue, 12 Jan 2021 00:46:49 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 00:41:31 -0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 16:41:29 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Jan 2021 16:41:29 +0800 Message-ID: <1610440889.1140.9.camel@mtksdaap41> Subject: Re: [PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU From: Nick Fan To: Steven Price Date: Tue, 12 Jan 2021 16:41:29 +0800 In-Reply-To: <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> References: <20210105053632.5476-1-Nick.Fan@mediatek.com> <20210105053632.5476-2-Nick.Fan@mediatek.com> <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210112_034652_274773_9D26560E X-CRM114-Status: GOOD ( 21.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2021-01-08 at 15:58 +0000, Steven Price wrote: > On 05/01/2021 05:36, Nick Fan wrote: > > Add a basic GPU node for mt8192. > > > > Signed-off-by: Nick Fan > > --- > > This patch depends on Mediatek power and regulator support. > > > > Listed as following. > > > > [1]https://lore.kernel.org/patchwork/patch/1336293/ > > [2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013 > > [3]https://lore.kernel.org/patchwork/patch/1356037/ > > [4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777 > > [5]https://lore.kernel.org/patchwork/patch/1356175/ > > [6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.wang@mediatek.com/ > > [7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.wang@mediatek.com/ > > --- > > --- > > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 176 ++++++++++++++++++++ > > 2 files changed, 183 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > index 6c1e2b3e8a60..48c0e240dd92 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > @@ -5,6 +5,7 @@ > > */ > > /dts-v1/; > > #include "mt8192.dtsi" > > +#include "mt6359.dtsi" > > > > / { > > model = "MediaTek MT8192 evaluation board"; > > @@ -70,6 +71,12 @@ > > }; > > }; > > > > +&gpu { > > + supply-names = "mali","sram"; > > + mali-supply = <&mt6315_7_vbuck1>; > > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > > +}; > > + > > &uart0 { > > status = "okay"; > > }; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index d6a4ad242a33..de166ea750af 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -822,6 +822,182 @@ > > #clock-cells = <1>; > > }; > > > > + gpu: mali@13000000 { > > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > > + reg = <0 0x13000000 0 0x4000>; > > + interrupts = > > + , > > + , > > + , > > + , > > + ; > > + interrupt-names = > > + "GPU", > > + "MMU", > > + "JOB", > > + "EVENT", > > + "PWR"; > > These interrupt names don't match the binding you've posted (GPU, MMU, > JOB are upper case here, lower case in the binding). Also EVENT and PWR > are not mentioned in the binding - should they be? > > I know there are differences here between kbase's requirements and the > existing upstream bindings (case specifically), but I haven't seen a > binding containing EVENT and PWR before. > > Steve > Thanks for your comment. Yes, the EVENT and PWR should be removed. And the rest of interrupt names are corrected to lower case. Please check my updated version 4 for this. https://lore.kernel.org/patchwork/patch/1363862/ Nick Fan > > + > > + clocks = > > + <&apmixedsys CLK_APMIXED_MFGPLL>, > > + <&topckgen CLK_TOP_MFG_PLL_SEL>, > > + <&topckgen CLK_TOP_MFG_REF_SEL>, > > + <&mfgcfg CLK_MFG_BG3D>; > > + clock-names = > > + "clk_main_parent", > > + "clk_mux", > > + "clk_sub_parent", > > + "subsys_mfg_cg"; > > + > > + power-domains = > > + <&scpsys MT8192_POWER_DOMAIN_MFG2>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG3>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG4>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG5>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG6>; > > + power-domain-names = "core0", > > + "core1", > > + "core2", > > + "core3", > > + "core4"; > > + > > + operating-points-v2 = <&gpu_opp_table>; > > + #cooling-cells = <2>; > > + }; > > + > > + gpu_opp_table: opp_table0 { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-358000000 { > > + opp-hz = /bits/ 64 <358000000>; > > + opp-hz-real = /bits/ 64 <358000000>, > > + /bits/ 64 <358000000>; > > + opp-microvolt = <606250>, > > + <750000>; > > + }; > > + > > + opp-399000000 { > > + opp-hz = /bits/ 64 <399000000>; > > + opp-hz-real = /bits/ 64 <399000000>, > > + /bits/ 64 <399000000>; > > + opp-microvolt = <618750>, > > + <750000>; > > + }; > > + > > + opp-440000000 { > > + opp-hz = /bits/ 64 <440000000>; > > + opp-hz-real = /bits/ 64 <440000000>, > > + /bits/ 64 <440000000>; > > + opp-microvolt = <631250>, > > + <750000>; > > + }; > > + > > + opp-482000000 { > > + opp-hz = /bits/ 64 <482000000>; > > + opp-hz-real = /bits/ 64 <482000000>, > > + /bits/ 64 <482000000>; > > + opp-microvolt = <643750>, > > + <750000>; > > + }; > > + > > + opp-523000000 { > > + opp-hz = /bits/ 64 <523000000>; > > + opp-hz-real = /bits/ 64 <523000000>, > > + /bits/ 64 <523000000>; > > + opp-microvolt = <656250>, > > + <750000>; > > + }; > > + > > + opp-564000000 { > > + opp-hz = /bits/ 64 <564000000>; > > + opp-hz-real = /bits/ 64 <564000000>, > > + /bits/ 64 <564000000>; > > + opp-microvolt = <668750>, > > + <750000>; > > + }; > > + > > + opp-605000000 { > > + opp-hz = /bits/ 64 <605000000>; > > + opp-hz-real = /bits/ 64 <605000000>, > > + /bits/ 64 <605000000>; > > + opp-microvolt = <681250>, > > + <750000>; > > + }; > > + > > + opp-647000000 { > > + opp-hz = /bits/ 64 <647000000>; > > + opp-hz-real = /bits/ 64 <647000000>, > > + /bits/ 64 <647000000>; > > + opp-microvolt = <693750>, > > + <750000>; > > + }; > > + > > + opp-688000000 { > > + opp-hz = /bits/ 64 <688000000>; > > + opp-hz-real = /bits/ 64 <688000000>, > > + /bits/ 64 <688000000>; > > + opp-microvolt = <706250>, > > + <750000>; > > + }; > > + > > + opp-724000000 { > > + opp-hz = /bits/ 64 <724000000>; > > + opp-hz-real = /bits/ 64 <724000000>, > > + /bits/ 64 <724000000>; > > + opp-microvolt = <725000>, > > + <750000>; > > + }; > > + > > + opp-760000000 { > > + opp-hz = /bits/ 64 <760000000>; > > + opp-hz-real = /bits/ 64 <760000000>, > > + /bits/ 64 <760000000>; > > + opp-microvolt = <743750>, > > + <750000>; > > + }; > > + > > + opp-795000000 { > > + opp-hz = /bits/ 64 <795000000>; > > + opp-hz-real = /bits/ 64 <795000000>, > > + /bits/ 64 <795000000>; > > + opp-microvolt = <762500>, > > + <762500>; > > + }; > > + > > + opp-831000000 { > > + opp-hz = /bits/ 64 <831000000>; > > + opp-hz-real = /bits/ 64 <831000000>, > > + /bits/ 64 <831000000>; > > + opp-microvolt = <781250>, > > + <781250>; > > + }; > > + > > + opp-855000000 { > > + opp-hz = /bits/ 64 <855000000>; > > + opp-hz-real = /bits/ 64 <855000000>, > > + /bits/ 64 <855000000>; > > + opp-microvolt = <793750>, > > + <793750>; > > + }; > > + > > + opp-902000000 { > > + opp-hz = /bits/ 64 <902000000>; > > + opp-hz-real = /bits/ 64 <902000000>, > > + /bits/ 64 <902000000>; > > + opp-microvolt = <818750>, > > + <818750>; > > + }; > > + > > + opp-950000000 { > > + opp-hz = /bits/ 64 <950000000>; > > + opp-hz-real = /bits/ 64 <950000000>, > > + /bits/ 64 <950000000>; > > + opp-microvolt = <843750>, > > + <843750>; > > + }; > > + }; > > + > > mfgcfg: syscon@13fbf000 { > > compatible = "mediatek,mt8192-mfgcfg", "syscon"; > > reg = <0 0x13fbf000 0 0x1000>; > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BBCEC433E6 for ; Tue, 12 Jan 2021 08:42:27 +0000 (UTC) Received: from vger.kernel.org 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Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1553792856; Tue, 12 Jan 2021 16:41:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 16:41:29 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Jan 2021 16:41:29 +0800 Message-ID: <1610440889.1140.9.camel@mtksdaap41> Subject: Re: [PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU From: Nick Fan To: Steven Price CC: Rob Herring , Matthias Brugger , , , David Airlie , , , , , Date: Tue, 12 Jan 2021 16:41:29 +0800 In-Reply-To: <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> References: <20210105053632.5476-1-Nick.Fan@mediatek.com> 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L3BhdGNod29yay5rZXJuZWwub3JnL3Byb2plY3QvbGludXgtbWVkaWF0ZWsvbGlzdC8/c2VyaWVz PTQwNTc3Nw0KPiA+IFs1XWh0dHBzOi8vbG9yZS5rZXJuZWwub3JnL3BhdGNod29yay9wYXRjaC8x MzU2MTc1Lw0KPiA+IFs2XWh0dHBzOi8vcGF0Y2h3b3JrLmtlcm5lbC5vcmcvcHJvamVjdC9saW51 eC1tZWRpYXRlay9wYXRjaC8xNjA1NzAwODk0LTMyNjk5LTYtZ2l0LXNlbmQtZW1haWwtaHNpbi1o c2l1bmcud2FuZ0BtZWRpYXRlay5jb20vDQo+ID4gWzddaHR0cHM6Ly9wYXRjaHdvcmsua2VybmVs Lm9yZy9wcm9qZWN0L2xpbnV4LW1lZGlhdGVrL3BhdGNoLzE2MDgxMDQ4MjctNzkzNy0xMC1naXQt c2VuZC1lbWFpbC1oc2luLWhzaXVuZy53YW5nQG1lZGlhdGVrLmNvbS8NCj4gPiAtLS0NCj4gPiAt LS0NCj4gPiAgIGFyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ4MTkyLWV2Yi5kdHMgfCAg IDcgKw0KPiA+ICAgYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgxOTIuZHRzaSAgICB8 IDE3NiArKysrKysrKysrKysrKysrKysrKw0KPiA+ICAgMiBmaWxlcyBjaGFuZ2VkLCAxODMgaW5z ZXJ0aW9ucygrKQ0KPiA+IA0KPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0L2Jvb3QvZHRzL21l ZGlhdGVrL210ODE5Mi1ldmIuZHRzIGIvYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgx OTItZXZiLmR0cw0KPiA+IGluZGV4IDZjMWUyYjNlOGE2MC4uNDhjMGUyNDBkZDkyIDEwMDY0NA0K PiA+IC0tLSBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ4MTkyLWV2Yi5kdHMNCj4g PiArKysgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210ODE5Mi1ldmIuZHRzDQo+ID4g QEAgLTUsNiArNSw3IEBADQo+ID4gICAgKi8NCj4gPiAgIC9kdHMtdjEvOw0KPiA+ICAgI2luY2x1 ZGUgIm10ODE5Mi5kdHNpIg0KPiA+ICsjaW5jbHVkZSAibXQ2MzU5LmR0c2kiDQo+ID4gICANCj4g PiAgIC8gew0KPiA+ICAgCW1vZGVsID0gIk1lZGlhVGVrIE1UODE5MiBldmFsdWF0aW9uIGJvYXJk IjsNCj4gPiBAQCAtNzAsNiArNzEsMTIgQEANCj4gPiAgIAl9Ow0KPiA+ICAgfTsNCj4gPiAgIA0K PiA+ICsmZ3B1IHsNCj4gPiArCXN1cHBseS1uYW1lcyA9ICJtYWxpIiwic3JhbSI7DQo+ID4gKwlt YWxpLXN1cHBseSA9IDwmbXQ2MzE1XzdfdmJ1Y2sxPjsNCj4gPiArCXNyYW0tc3VwcGx5ID0gPCZt dDYzNTlfdnNyYW1fb3RoZXJzX2xkb19yZWc+Ow0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAgICZ1YXJ0 MCB7DQo+ID4gICAJc3RhdHVzID0gIm9rYXkiOw0KPiA+ICAgfTsNCj4gPiBkaWZmIC0tZ2l0IGEv YXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgxOTIuZHRzaSBiL2FyY2gvYXJtNjQvYm9v dC9kdHMvbWVkaWF0ZWsvbXQ4MTkyLmR0c2kNCj4gPiBpbmRleCBkNmE0YWQyNDJhMzMuLmRlMTY2 ZWE3NTBhZiAxMDA2NDQNCj4gPiAtLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210 ODE5Mi5kdHNpDQo+ID4gKysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgxOTIu ZHRzaQ0KPiA+IEBAIC04MjIsNiArODIyLDE4MiBAQA0KPiA+ICAgCQkJI2Nsb2NrLWNlbGxzID0g PDE+Ow0KPiA+ICAgCQl9Ow0KPiA+ICAgDQo+ID4gKwkJZ3B1OiBtYWxpQDEzMDAwMDAwIHsNCj4g PiArCQkJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxOTItbWFsaSIsICJhcm0sbWFsaS12YWxo YWxsIjsNCj4gPiArCQkJcmVnID0gPDAgMHgxMzAwMDAwMCAwIDB4NDAwMD47DQo+ID4gKwkJCWlu dGVycnVwdHMgPQ0KPiA+ICsJCQkJPEdJQ19TUEkgMzYzIElSUV9UWVBFX0xFVkVMX0hJR0ggMD4s DQo+ID4gKwkJCQk8R0lDX1NQSSAzNjQgSVJRX1RZUEVfTEVWRUxfSElHSCAwPiwNCj4gPiArCQkJ CTxHSUNfU1BJIDM2NSBJUlFfVFlQRV9MRVZFTF9ISUdIIDA+LA0KPiA+ICsJCQkJPEdJQ19TUEkg MzY2IElSUV9UWVBFX0xFVkVMX0hJR0ggMD4sDQo+ID4gKwkJCQk8R0lDX1NQSSAzNjcgSVJRX1RZ UEVfTEVWRUxfSElHSCAwPjsNCj4gPiArCQkJaW50ZXJydXB0LW5hbWVzID0NCj4gPiArCQkJCSJH UFUiLA0KPiA+ICsJCQkJIk1NVSIsDQo+ID4gKwkJCQkiSk9CIiwNCj4gPiArCQkJCSJFVkVOVCIs DQo+ID4gKwkJCQkiUFdSIjsNCj4gDQo+IFRoZXNlIGludGVycnVwdCBuYW1lcyBkb24ndCBtYXRj aCB0aGUgYmluZGluZyB5b3UndmUgcG9zdGVkIChHUFUsIE1NVSwgDQo+IEpPQiBhcmUgdXBwZXIg Y2FzZSBoZXJlLCBsb3dlciBjYXNlIGluIHRoZSBiaW5kaW5nKS4gQWxzbyBFVkVOVCBhbmQgUFdS IA0KPiBhcmUgbm90IG1lbnRpb25lZCBpbiB0aGUgYmluZGluZyAtIHNob3VsZCB0aGV5IGJlPw0K PiANCj4gSSBrbm93IHRoZXJlIGFyZSBkaWZmZXJlbmNlcyBoZXJlIGJldHdlZW4ga2Jhc2UncyBy ZXF1aXJlbWVudHMgYW5kIHRoZSANCj4gZXhpc3RpbmcgdXBzdHJlYW0gYmluZGluZ3MgKGNhc2Ug c3BlY2lmaWNhbGx5KSwgYnV0IEkgaGF2ZW4ndCBzZWVuIGEgDQo+IGJpbmRpbmcgY29udGFpbmlu ZyBFVkVOVCBhbmQgUFdSIGJlZm9yZS4NCj4gDQo+IFN0ZXZlDQo+IA0KVGhhbmtzIGZvciB5b3Vy IGNvbW1lbnQuDQpZZXMsIHRoZSBFVkVOVCBhbmQgUFdSIHNob3VsZCBiZSByZW1vdmVkLg0KQW5k IHRoZSByZXN0IG9mIGludGVycnVwdCBuYW1lcyBhcmUgY29ycmVjdGVkIHRvIGxvd2VyIGNhc2Uu DQoNClBsZWFzZSBjaGVjayBteSB1cGRhdGVkIHZlcnNpb24gNCBmb3IgdGhpcy4NCmh0dHBzOi8v bG9yZS5rZXJuZWwub3JnL3BhdGNod29yay9wYXRjaC8xMzYzODYyLw0KDQpOaWNrIEZhbg0KDQo+ ID4gKw0KPiA+ICsJCQljbG9ja3MgPQ0KPiA+ICsJCQkJPCZhcG1peGVkc3lzIENMS19BUE1JWEVE X01GR1BMTD4sDQo+ID4gKwkJCQk8JnRvcGNrZ2VuIENMS19UT1BfTUZHX1BMTF9TRUw+LA0KPiA+ ICsJCQkJPCZ0b3Bja2dlbiBDTEtfVE9QX01GR19SRUZfU0VMPiwNCj4gPiArCQkJCTwmbWZnY2Zn IENMS19NRkdfQkczRD47DQo+ID4gKwkJCWNsb2NrLW5hbWVzID0NCj4gPiArCQkJCSJjbGtfbWFp bl9wYXJlbnQiLA0KPiA+ICsJCQkJImNsa19tdXgiLA0KPiA+ICsJCQkJImNsa19zdWJfcGFyZW50 IiwNCj4gPiArCQkJCSJzdWJzeXNfbWZnX2NnIjsNCj4gPiArDQo+ID4gKwkJCXBvd2VyLWRvbWFp bnMgPQ0KPiA+ICsJCQkJPCZzY3BzeXMgTVQ4MTkyX1BPV0VSX0RPTUFJTl9NRkcyPiwNCj4gPiAr CQkJCTwmc2Nwc3lzIE1UODE5Ml9QT1dFUl9ET01BSU5fTUZHMz4sDQo+ID4gKwkJCQk8JnNjcHN5 cyBNVDgxOTJfUE9XRVJfRE9NQUlOX01GRzQ+LA0KPiA+ICsJCQkJPCZzY3BzeXMgTVQ4MTkyX1BP V0VSX0RPTUFJTl9NRkc1PiwNCj4gPiArCQkJCTwmc2Nwc3lzIE1UODE5Ml9QT1dFUl9ET01BSU5f TUZHNj47DQo+ID4gKwkJCXBvd2VyLWRvbWFpbi1uYW1lcyA9ICJjb3JlMCIsDQo+ID4gKwkJCQkJ ICAgICAiY29yZTEiLA0KPiA+ICsJCQkJCSAgICAgImNvcmUyIiwNCj4gPiArCQkJCQkgICAgICJj b3JlMyIsDQo+ID4gKwkJCQkJICAgICAiY29yZTQiOw0KPiA+ICsNCj4gPiArCQkJb3BlcmF0aW5n LXBvaW50cy12MiA9IDwmZ3B1X29wcF90YWJsZT47DQo+ID4gKwkJCSNjb29saW5nLWNlbGxzID0g PDI+Ow0KPiA+ICsJCX07DQo+ID4gKw0KPiA+ICsJCWdwdV9vcHBfdGFibGU6IG9wcF90YWJsZTAg ew0KPiA+ICsJCQljb21wYXRpYmxlID0gIm9wZXJhdGluZy1wb2ludHMtdjIiOw0KPiA+ICsJCQlv cHAtc2hhcmVkOw0KPiA+ICsNCj4gPiArCQkJb3BwLTM1ODAwMDAwMCB7DQo+ID4gKwkJCQlvcHAt aHogPSAvYml0cy8gNjQgPDM1ODAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRz LyA2NCA8MzU4MDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDM1ODAwMDAwMD47 DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDYwNjI1MD4sDQo+ID4gKwkJCQkJCTw3NTAwMDA+ Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTM5OTAwMDAwMCB7DQo+ID4gKwkJCQlv cHAtaHogPSAvYml0cy8gNjQgPDM5OTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9i aXRzLyA2NCA8Mzk5MDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDM5OTAwMDAw MD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDYxODc1MD4sDQo+ID4gKwkJCQkJCTw3NTAw MDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTQ0MDAwMDAwMCB7DQo+ID4gKwkJ CQlvcHAtaHogPSAvYml0cy8gNjQgPDQ0MDAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9 IC9iaXRzLyA2NCA8NDQwMDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDQ0MDAw MDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDYzMTI1MD4sDQo+ID4gKwkJCQkJCTw3 NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTQ4MjAwMDAwMCB7DQo+ID4g KwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDQ4MjAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVh bCA9IC9iaXRzLyA2NCA8NDgyMDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDQ4 MjAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDY0Mzc1MD4sDQo+ID4gKwkJCQkJ CTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTUyMzAwMDAwMCB7DQo+ ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDUyMzAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHot cmVhbCA9IC9iaXRzLyA2NCA8NTIzMDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQg PDUyMzAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDY1NjI1MD4sDQo+ID4gKwkJ CQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTU2NDAwMDAwMCB7 DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDU2NDAwMDAwMD47DQo+ID4gKwkJCQlvcHAt aHotcmVhbCA9IC9iaXRzLyA2NCA8NTY0MDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8g NjQgPDU2NDAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDY2ODc1MD4sDQo+ID4g KwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTYwNTAwMDAw MCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDYwNTAwMDAwMD47DQo+ID4gKwkJCQlv cHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8NjA1MDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0 cy8gNjQgPDYwNTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDY4MTI1MD4sDQo+ ID4gKwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTY0NzAw MDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDY0NzAwMDAwMD47DQo+ID4gKwkJ CQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8NjQ3MDAwMDAwPiwNCj4gPiArCQkJCQkgICAgICAv Yml0cy8gNjQgPDY0NzAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDY5Mzc1MD4s DQo+ID4gKwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3BwLTY4 ODAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDY4ODAwMDAwMD47DQo+ID4g KwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8Njg4MDAwMDAwPiwNCj4gPiArCQkJCQkgICAg ICAvYml0cy8gNjQgPDY4ODAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDcwNjI1 MD4sDQo+ID4gKwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJb3Bw LTcyNDAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDcyNDAwMDAwMD47DQo+ ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8NzI0MDAwMDAwPiwNCj4gPiArCQkJCQkg ICAgICAvYml0cy8gNjQgPDcyNDAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0gPDcy NTAwMD4sDQo+ID4gKwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJ b3BwLTc2MDAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDc2MDAwMDAwMD47 DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8NzYwMDAwMDAwPiwNCj4gPiArCQkJ CQkgICAgICAvYml0cy8gNjQgPDc2MDAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0ID0g PDc0Mzc1MD4sDQo+ID4gKwkJCQkJCTw3NTAwMDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiAr CQkJb3BwLTc5NTAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDc5NTAwMDAw MD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8Nzk1MDAwMDAwPiwNCj4gPiAr CQkJCQkgICAgICAvYml0cy8gNjQgPDc5NTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92b2x0 ID0gPDc2MjUwMD4sDQo+ID4gKwkJCQkJCTw3NjI1MDA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4g PiArCQkJb3BwLTgzMTAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDgzMTAw MDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8ODMxMDAwMDAwPiwNCj4g PiArCQkJCQkgICAgICAvYml0cy8gNjQgPDgzMTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWljcm92 b2x0ID0gPDc4MTI1MD4sDQo+ID4gKwkJCQkJCTw3ODEyNTA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsN Cj4gPiArCQkJb3BwLTg1NTAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQgPDg1 NTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8ODU1MDAwMDAwPiwN Cj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDg1NTAwMDAwMD47DQo+ID4gKwkJCQlvcHAtbWlj cm92b2x0ID0gPDc5Mzc1MD4sDQo+ID4gKwkJCQkJCTw3OTM3NTA+Ow0KPiA+ICsJCQl9Ow0KPiA+ ICsNCj4gPiArCQkJb3BwLTkwMjAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8gNjQg PDkwMjAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8OTAyMDAwMDAw PiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDkwMjAwMDAwMD47DQo+ID4gKwkJCQlvcHAt bWljcm92b2x0ID0gPDgxODc1MD4sDQo+ID4gKwkJCQkJCTw4MTg3NTA+Ow0KPiA+ICsJCQl9Ow0K PiA+ICsNCj4gPiArCQkJb3BwLTk1MDAwMDAwMCB7DQo+ID4gKwkJCQlvcHAtaHogPSAvYml0cy8g NjQgPDk1MDAwMDAwMD47DQo+ID4gKwkJCQlvcHAtaHotcmVhbCA9IC9iaXRzLyA2NCA8OTUwMDAw MDAwPiwNCj4gPiArCQkJCQkgICAgICAvYml0cy8gNjQgPDk1MDAwMDAwMD47DQo+ID4gKwkJCQlv cHAtbWljcm92b2x0ID0gPDg0Mzc1MD4sDQo+ID4gKwkJCQkJCTw4NDM3NTA+Ow0KPiA+ICsJCQl9 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bh=VBTKGTT0+mSnrPTP8B0PzlHyEFPhZjWk4u8GPBambi8=; b=cFXg4jCN+sAigMXN/uu5sH/C8HVT3NuhcDWT1LLTvrHH2KunH74NoAWfUiW2OPFKPxWBfC7OohAZHHE8rWPXGV1oGviqF+rs0LMM+v8w8ywTGYBJeIC8sG1mMN6uipJh9bH1qnUDW4oMcpfALubytn82Es3iPvayUDEjQBh2iME=; X-UUID: 205d9bc5ae484039b5bc8029a7d7d10f-20210112 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1553792856; Tue, 12 Jan 2021 16:41:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Jan 2021 16:41:29 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Jan 2021 16:41:29 +0800 Message-ID: <1610440889.1140.9.camel@mtksdaap41> Subject: Re: [PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU From: Nick Fan To: Steven Price Date: Tue, 12 Jan 2021 16:41:29 +0800 In-Reply-To: <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> References: <20210105053632.5476-1-Nick.Fan@mediatek.com> <20210105053632.5476-2-Nick.Fan@mediatek.com> <3d3bf91a-92b0-385c-b7c1-35af7732f05f@arm.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Wed, 13 Jan 2021 08:21:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, 2021-01-08 at 15:58 +0000, Steven Price wrote: > On 05/01/2021 05:36, Nick Fan wrote: > > Add a basic GPU node for mt8192. > > > > Signed-off-by: Nick Fan > > --- > > This patch depends on Mediatek power and regulator support. > > > > Listed as following. > > > > [1]https://lore.kernel.org/patchwork/patch/1336293/ > > [2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013 > > [3]https://lore.kernel.org/patchwork/patch/1356037/ > > [4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777 > > [5]https://lore.kernel.org/patchwork/patch/1356175/ > > [6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.wang@mediatek.com/ > > [7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.wang@mediatek.com/ > > --- > > --- > > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 176 ++++++++++++++++++++ > > 2 files changed, 183 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > index 6c1e2b3e8a60..48c0e240dd92 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts > > @@ -5,6 +5,7 @@ > > */ > > /dts-v1/; > > #include "mt8192.dtsi" > > +#include "mt6359.dtsi" > > > > / { > > model = "MediaTek MT8192 evaluation board"; > > @@ -70,6 +71,12 @@ > > }; > > }; > > > > +&gpu { > > + supply-names = "mali","sram"; > > + mali-supply = <&mt6315_7_vbuck1>; > > + sram-supply = <&mt6359_vsram_others_ldo_reg>; > > +}; > > + > > &uart0 { > > status = "okay"; > > }; > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index d6a4ad242a33..de166ea750af 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -822,6 +822,182 @@ > > #clock-cells = <1>; > > }; > > > > + gpu: mali@13000000 { > > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; > > + reg = <0 0x13000000 0 0x4000>; > > + interrupts = > > + , > > + , > > + , > > + , > > + ; > > + interrupt-names = > > + "GPU", > > + "MMU", > > + "JOB", > > + "EVENT", > > + "PWR"; > > These interrupt names don't match the binding you've posted (GPU, MMU, > JOB are upper case here, lower case in the binding). Also EVENT and PWR > are not mentioned in the binding - should they be? > > I know there are differences here between kbase's requirements and the > existing upstream bindings (case specifically), but I haven't seen a > binding containing EVENT and PWR before. > > Steve > Thanks for your comment. Yes, the EVENT and PWR should be removed. And the rest of interrupt names are corrected to lower case. Please check my updated version 4 for this. https://lore.kernel.org/patchwork/patch/1363862/ Nick Fan > > + > > + clocks = > > + <&apmixedsys CLK_APMIXED_MFGPLL>, > > + <&topckgen CLK_TOP_MFG_PLL_SEL>, > > + <&topckgen CLK_TOP_MFG_REF_SEL>, > > + <&mfgcfg CLK_MFG_BG3D>; > > + clock-names = > > + "clk_main_parent", > > + "clk_mux", > > + "clk_sub_parent", > > + "subsys_mfg_cg"; > > + > > + power-domains = > > + <&scpsys MT8192_POWER_DOMAIN_MFG2>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG3>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG4>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG5>, > > + <&scpsys MT8192_POWER_DOMAIN_MFG6>; > > + power-domain-names = "core0", > > + "core1", > > + "core2", > > + "core3", > > + "core4"; > > + > > + operating-points-v2 = <&gpu_opp_table>; > > + #cooling-cells = <2>; > > + }; > > + > > + gpu_opp_table: opp_table0 { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-358000000 { > > + opp-hz = /bits/ 64 <358000000>; > > + opp-hz-real = /bits/ 64 <358000000>, > > + /bits/ 64 <358000000>; > > + opp-microvolt = <606250>, > > + <750000>; > > + }; > > + > > + opp-399000000 { > > + opp-hz = /bits/ 64 <399000000>; > > + opp-hz-real = /bits/ 64 <399000000>, > > + /bits/ 64 <399000000>; > > + opp-microvolt = <618750>, > > + <750000>; > > + }; > > + > > + opp-440000000 { > > + opp-hz = /bits/ 64 <440000000>; > > + opp-hz-real = /bits/ 64 <440000000>, > > + /bits/ 64 <440000000>; > > + opp-microvolt = <631250>, > > + <750000>; > > + }; > > + > > + opp-482000000 { > > + opp-hz = /bits/ 64 <482000000>; > > + opp-hz-real = /bits/ 64 <482000000>, > > + /bits/ 64 <482000000>; > > + opp-microvolt = <643750>, > > + <750000>; > > + }; > > + > > + opp-523000000 { > > + opp-hz = /bits/ 64 <523000000>; > > + opp-hz-real = /bits/ 64 <523000000>, > > + /bits/ 64 <523000000>; > > + opp-microvolt = <656250>, > > + <750000>; > > + }; > > + > > + opp-564000000 { > > + opp-hz = /bits/ 64 <564000000>; > > + opp-hz-real = /bits/ 64 <564000000>, > > + /bits/ 64 <564000000>; > > + opp-microvolt = <668750>, > > + <750000>; > > + }; > > + > > + opp-605000000 { > > + opp-hz = /bits/ 64 <605000000>; > > + opp-hz-real = /bits/ 64 <605000000>, > > + /bits/ 64 <605000000>; > > + opp-microvolt = <681250>, > > + <750000>; > > + }; > > + > > + opp-647000000 { > > + opp-hz = /bits/ 64 <647000000>; > > + opp-hz-real = /bits/ 64 <647000000>, > > + /bits/ 64 <647000000>; > > + opp-microvolt = <693750>, > > + <750000>; > > + }; > > + > > + opp-688000000 { > > + opp-hz = /bits/ 64 <688000000>; > > + opp-hz-real = /bits/ 64 <688000000>, > > + /bits/ 64 <688000000>; > > + opp-microvolt = <706250>, > > + <750000>; > > + }; > > + > > + opp-724000000 { > > + opp-hz = /bits/ 64 <724000000>; > > + opp-hz-real = /bits/ 64 <724000000>, > > + /bits/ 64 <724000000>; > > + opp-microvolt = <725000>, > > + <750000>; > > + }; > > + > > + opp-760000000 { > > + opp-hz = /bits/ 64 <760000000>; > > + opp-hz-real = /bits/ 64 <760000000>, > > + /bits/ 64 <760000000>; > > + opp-microvolt = <743750>, > > + <750000>; > > + }; > > + > > + opp-795000000 { > > + opp-hz = /bits/ 64 <795000000>; > > + opp-hz-real = /bits/ 64 <795000000>, > > + /bits/ 64 <795000000>; > > + opp-microvolt = <762500>, > > + <762500>; > > + }; > > + > > + opp-831000000 { > > + opp-hz = /bits/ 64 <831000000>; > > + opp-hz-real = /bits/ 64 <831000000>, > > + /bits/ 64 <831000000>; > > + opp-microvolt = <781250>, > > + <781250>; > > + }; > > + > > + opp-855000000 { > > + opp-hz = /bits/ 64 <855000000>; > > + opp-hz-real = /bits/ 64 <855000000>, > > + /bits/ 64 <855000000>; > > + opp-microvolt = <793750>, > > + <793750>; > > + }; > > + > > + opp-902000000 { > > + opp-hz = /bits/ 64 <902000000>; > > + opp-hz-real = /bits/ 64 <902000000>, > > + /bits/ 64 <902000000>; > > + opp-microvolt = <818750>, > > + <818750>; > > + }; > > + > > + opp-950000000 { > > + opp-hz = /bits/ 64 <950000000>; > > + opp-hz-real = /bits/ 64 <950000000>, > > + /bits/ 64 <950000000>; > > + opp-microvolt = <843750>, > > + <843750>; > > + }; > > + }; > > + > > mfgcfg: syscon@13fbf000 { > > compatible = "mediatek,mt8192-mfgcfg", "syscon"; > > reg = <0 0x13fbf000 0 0x1000>; > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel