From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F596C433E0 for ; Thu, 28 Jan 2021 06:20:12 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A39266146D for ; Thu, 28 Jan 2021 06:20:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A39266146D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Q9feQZB5KAihw/kREQ40hfolHs4O+TeKSTtb7Fw9VaU=; b=N2pVWmUJ3WXPY3OSb1/bjbkZs PnvrwyOs2plKuOyOWVSRNv5a0GhQURLAMPi5JOWekZvP14j0hrftMtadAIr2V2bCIE0cb47EMqUg5 m1nh87BoC5o2liz37XOAfmBY/qGKJQaFik1OzLVgz4c9fSLmlA7eLEqcV7tkzBChqW2haKvdXsAxZ uevYJ7PInvWwMYBgzyC/jMCdFOCjmBlbT0SZBMq/AC1gI7iTHQfgx3Sjn1Ev36+T4t6DYaZGK8pmg gEbjVFHGGpLG56l6hG5yWbwMdxkJE4G1rQ36n27HZktxxpguUYsocv8sPcdrn5htIxH6Dprx6aW+k yX3XjXK1A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l50ew-0002jx-4p; Thu, 28 Jan 2021 06:20:02 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l50et-0002j1-KM; Thu, 28 Jan 2021 06:20:00 +0000 X-UUID: 1be82dc253374de7900db615a50760fe-20210127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=9l/3qxAZieqX345ryvbLhbIWYhgxrPRb06fzhqIsH4I=; b=d7v5tLSxniZ5xBAoXnZJQv8bRx0TJIQBoyfXzNGUDXFsg6J8Jaqv0Avr/h8yiLqMy6XUOuVZG6bE1LVb80xeKxrXsOmS1v6xECZkv+b42I+C5kdJ4lMaFV6mji8NhwuyHyScDjFput8Euf/1dXzIeRik2+8VbJTio6e0eQrCWTw=; X-UUID: 1be82dc253374de7900db615a50760fe-20210127 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 161931991; Wed, 27 Jan 2021 22:19:56 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 22:19:55 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 14:19:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 14:19:52 +0800 Message-ID: <1611814791.28312.12.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 14:19:51 +0800 In-Reply-To: <1611814421.28312.9.camel@mtksdaap41> References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 6B1B6152A535CF41E1E99F1F5C98B01A2969156BDD91B00DC1A7E800C4434FCC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_011959_857504_539FF68B X-CRM114-Status: GOOD ( 22.57 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote: > Hi, Hsin-Yi: > > Modify the title's prefix to 'soc: mediatek:' Modify more, the title should be 'soc: mediatek: add mtk mutex support for MT8183' > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > From: Yongqiang Niu > > > > Add DDP support for MT8183 SoC. > > > > Signed-off-by: Yongqiang Niu > > Signed-off-by: Hsin-Yi Wang > > --- > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > 1 file changed, 50 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > index f531b119da7a9..f64e9c33e85ad 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -14,6 +14,8 @@ > > > > #define MT2701_MUTEX0_MOD0 0x2c > > #define MT2701_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -37,6 +39,18 @@ > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -87,6 +101,12 @@ > > #define MT2712_MUTEX_SOF_DSI3 6 > > #define MT8167_MUTEX_SOF_DPI0 2 > > #define MT8167_MUTEX_SOF_DPI1 3 > > +#define MT8183_MUTEX_SOF_DSI0 1 > > +#define MT8183_MUTEX_SOF_DPI0 2 > > + > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > struct mtk_mutex { > > int id; > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > }; > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > According to discussion in [1], add comment for the odd EOF setting. > > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > Regards, > CK. > > > > +}; > > + > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > + .no_clk = true, > > +}; > > + > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > { > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > .data = &mt8167_mutex_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_mutex_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_mutex_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07E5DC433E0 for ; Thu, 28 Jan 2021 06:21:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70C1D64DD6 for ; Thu, 28 Jan 2021 06:21:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70C1D64DD6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vsHoY7uP1BxFEoMaX6R15sX8X39dwje5JzjpW5poL+4=; b=hJ03AHAkxtUSIiza7JqZ5zwnI l/HZkplsuXdBXgFkFQXqF65QmYxNKcI7BODfKkAhMwPYyKd6H/1S5rHcqipi9KE+c0CMuvQMqP7xm EhsK/3XJnbGgbAr799yX7SYwE0OQ5McEfSW5TLc4aQRPcnSxUOow6t2z98A28rTndFySj93kCBsao SNihVdH7anvnFIQV2NNk0v1aAezx/bYRxQhxgyE//rkgdmMryIpEiVBzo1pRN0gF+6sVr3Z5LuRTy SghyMrxqQbv4r/G5UGILbRPXpacTmU5XObONf+BqJ6WJCMkSna4YW0TsQE2zM/U6YwAOJ3fMDVMSb 37mVzQvzg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l50ex-0002k8-2y; Thu, 28 Jan 2021 06:20:03 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l50et-0002j1-KM; Thu, 28 Jan 2021 06:20:00 +0000 X-UUID: 1be82dc253374de7900db615a50760fe-20210127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=9l/3qxAZieqX345ryvbLhbIWYhgxrPRb06fzhqIsH4I=; b=d7v5tLSxniZ5xBAoXnZJQv8bRx0TJIQBoyfXzNGUDXFsg6J8Jaqv0Avr/h8yiLqMy6XUOuVZG6bE1LVb80xeKxrXsOmS1v6xECZkv+b42I+C5kdJ4lMaFV6mji8NhwuyHyScDjFput8Euf/1dXzIeRik2+8VbJTio6e0eQrCWTw=; X-UUID: 1be82dc253374de7900db615a50760fe-20210127 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 161931991; Wed, 27 Jan 2021 22:19:56 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 22:19:55 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 14:19:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 14:19:52 +0800 Message-ID: <1611814791.28312.12.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 14:19:51 +0800 In-Reply-To: <1611814421.28312.9.camel@mtksdaap41> References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 6B1B6152A535CF41E1E99F1F5C98B01A2969156BDD91B00DC1A7E800C4434FCC2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_011959_857504_539FF68B X-CRM114-Status: GOOD ( 22.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote: > Hi, Hsin-Yi: > > Modify the title's prefix to 'soc: mediatek:' Modify more, the title should be 'soc: mediatek: add mtk mutex support for MT8183' > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > From: Yongqiang Niu > > > > Add DDP support for MT8183 SoC. > > > > Signed-off-by: Yongqiang Niu > > Signed-off-by: Hsin-Yi Wang > > --- > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > 1 file changed, 50 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > index f531b119da7a9..f64e9c33e85ad 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -14,6 +14,8 @@ > > > > #define MT2701_MUTEX0_MOD0 0x2c > > #define MT2701_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -37,6 +39,18 @@ > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -87,6 +101,12 @@ > > #define MT2712_MUTEX_SOF_DSI3 6 > > #define MT8167_MUTEX_SOF_DPI0 2 > > #define MT8167_MUTEX_SOF_DPI1 3 > > +#define MT8183_MUTEX_SOF_DSI0 1 > > +#define MT8183_MUTEX_SOF_DPI0 2 > > + > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > struct mtk_mutex { > > int id; > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > }; > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > According to discussion in [1], add comment for the odd EOF setting. > > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > Regards, > CK. > > > > +}; > > + > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > + .no_clk = true, > > +}; > > + > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > { > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > .data = &mt8167_mutex_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_mutex_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_mutex_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FD32C433DB for ; Thu, 28 Jan 2021 06:20:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5DE064DD6 for ; Thu, 28 Jan 2021 06:20:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229513AbhA1GUy (ORCPT ); Thu, 28 Jan 2021 01:20:54 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:57824 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229791AbhA1GUx (ORCPT ); Thu, 28 Jan 2021 01:20:53 -0500 X-UUID: 71f90608ce97483dad8d04b71034504f-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=9l/3qxAZieqX345ryvbLhbIWYhgxrPRb06fzhqIsH4I=; b=d7v5tLSxniZ5xBAoXnZJQv8bRx0TJIQBoyfXzNGUDXFsg6J8Jaqv0Avr/h8yiLqMy6XUOuVZG6bE1LVb80xeKxrXsOmS1v6xECZkv+b42I+C5kdJ4lMaFV6mji8NhwuyHyScDjFput8Euf/1dXzIeRik2+8VbJTio6e0eQrCWTw=; X-UUID: 71f90608ce97483dad8d04b71034504f-20210128 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1227452633; Thu, 28 Jan 2021 14:19:54 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 14:19:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 14:19:52 +0800 Message-ID: <1611814791.28312.12.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang CC: Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , , , , , , , Yongqiang Niu Date: Thu, 28 Jan 2021 14:19:51 +0800 In-Reply-To: <1611814421.28312.9.camel@mtksdaap41> References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 6B1B6152A535CF41E1E99F1F5C98B01A2969156BDD91B00DC1A7E800C4434FCC2000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gVGh1LCAyMDIxLTAxLTI4IGF0IDE0OjEzICswODAwLCBDSyBIdSB3cm90ZToNCj4gSGksIEhz aW4tWWk6DQo+IA0KPiBNb2RpZnkgdGhlIHRpdGxlJ3MgcHJlZml4IHRvICdzb2M6IG1lZGlhdGVr OicNCg0KTW9kaWZ5IG1vcmUsIHRoZSB0aXRsZSBzaG91bGQgYmUgJ3NvYzogbWVkaWF0ZWs6IGFk ZCBtdGsgbXV0ZXggc3VwcG9ydA0KZm9yIE1UODE4MycNCg0KPiANCj4gT24gV2VkLCAyMDIxLTAx LTI3IGF0IDEyOjU0ICswODAwLCBIc2luLVlpIFdhbmcgd3JvdGU6DQo+ID4gRnJvbTogWW9uZ3Fp YW5nIE5pdSA8eW9uZ3FpYW5nLm5pdUBtZWRpYXRlay5jb20+DQo+ID4gDQo+ID4gQWRkIEREUCBz dXBwb3J0IGZvciBNVDgxODMgU29DLg0KPiA+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IFlvbmdxaWFu ZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiA+IFNpZ25lZC1vZmYtYnk6IEhz aW4tWWkgV2FuZyA8aHNpbnlpQGNocm9taXVtLm9yZz4NCj4gPiAtLS0NCj4gPiAgZHJpdmVycy9z b2MvbWVkaWF0ZWsvbXRrLW11dGV4LmMgfCA1MCArKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKw0KPiA+ICAxIGZpbGUgY2hhbmdlZCwgNTAgaW5zZXJ0aW9ucygrKQ0KPiA+IA0KPiA+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstbXV0ZXguYyBiL2RyaXZlcnMvc29j L21lZGlhdGVrL210ay1tdXRleC5jDQo+ID4gaW5kZXggZjUzMWIxMTlkYTdhOS4uZjY0ZTljMzNl ODVhZCAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstbXV0ZXguYw0K PiA+ICsrKyBiL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1tdXRleC5jDQo+ID4gQEAgLTE0LDYg KzE0LDggQEANCj4gPiAgDQo+ID4gICNkZWZpbmUgTVQyNzAxX01VVEVYMF9NT0QwCQkJMHgyYw0K PiA+ICAjZGVmaW5lIE1UMjcwMV9NVVRFWDBfU09GMAkJCTB4MzANCj4gPiArI2RlZmluZSBNVDgx ODNfRElTUF9NVVRFWDBfTU9EMAkJCTB4MzANCj4gPiArI2RlZmluZSBNVDgxODNfRElTUF9NVVRF WDBfU09GMAkJCTB4MmMNCj4gDQo+IE1vZGlmeSAnRElTUF9NVVRFWCcgdG8gJ01VVEVYJw0KPiAN Cj4gPiAgDQo+ID4gICNkZWZpbmUgRElTUF9SRUdfTVVURVhfRU4obikJCQkoMHgyMCArIDB4MjAg KiAobikpDQo+ID4gICNkZWZpbmUgRElTUF9SRUdfTVVURVgobikJCQkoMHgyNCArIDB4MjAgKiAo bikpDQo+ID4gQEAgLTM3LDYgKzM5LDE4IEBADQo+ID4gICNkZWZpbmUgTVQ4MTY3X01VVEVYX01P RF9ESVNQX0RJVEhFUgkJMTUNCj4gPiAgI2RlZmluZSBNVDgxNjdfTVVURVhfTU9EX0RJU1BfVUZP RQkJMTYNCj4gPiAgDQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX01PRF9ESVNQX1JETUEwCQkw DQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX01PRF9ESVNQX1JETUExCQkxDQo+ID4gKyNkZWZp bmUgTVQ4MTgzX01VVEVYX01PRF9ESVNQX09WTDAJCTkNCj4gPiArI2RlZmluZSBNVDgxODNfTVVU RVhfTU9EX0RJU1BfT1ZMMF8yTAkJMTANCj4gPiArI2RlZmluZSBNVDgxODNfTVVURVhfTU9EX0RJ U1BfT1ZMMV8yTAkJMTENCj4gPiArI2RlZmluZSBNVDgxODNfTVVURVhfTU9EX0RJU1BfV0RNQTAJ CTEyDQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX01PRF9ESVNQX0NPTE9SMAkJMTMNCj4gPiAr I2RlZmluZSBNVDgxODNfTVVURVhfTU9EX0RJU1BfQ0NPUlIwCQkxNA0KPiA+ICsjZGVmaW5lIE1U ODE4M19NVVRFWF9NT0RfRElTUF9BQUwwCQkxNQ0KPiA+ICsjZGVmaW5lIE1UODE4M19NVVRFWF9N T0RfRElTUF9HQU1NQTAJCTE2DQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX01PRF9ESVNQX0RJ VEhFUjAJCTE3DQo+ID4gKw0KPiA+ICAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9PVkww CQkxMQ0KPiA+ICAjZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9PVkwxCQkxMg0KPiA+ICAj ZGVmaW5lIE1UODE3M19NVVRFWF9NT0RfRElTUF9SRE1BMAkJMTMNCj4gPiBAQCAtODcsNiArMTAx LDEyIEBADQo+ID4gICNkZWZpbmUgTVQyNzEyX01VVEVYX1NPRl9EU0kzCQkJNg0KPiA+ICAjZGVm aW5lIE1UODE2N19NVVRFWF9TT0ZfRFBJMAkJCTINCj4gPiAgI2RlZmluZSBNVDgxNjdfTVVURVhf U09GX0RQSTEJCQkzDQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX1NPRl9EU0kwCQkJMQ0KPiA+ ICsjZGVmaW5lIE1UODE4M19NVVRFWF9TT0ZfRFBJMAkJCTINCj4gPiArDQo+ID4gKy8qIEFkZCBF T0Ygc2V0dGluZyBzbyBvdmVybGF5IGhhcmR3YXJlIGNhbiByZWNlaXZlIGZyYW1lIGRvbmUgaXJx ICovDQo+ID4gKyNkZWZpbmUgTVQ4MTgzX01VVEVYX0VPRl9EU0kwCQkJKE1UODE4M19NVVRFWF9T T0ZfRFNJMCA8PCA2KQ0KPiA+ICsjZGVmaW5lIE1UODE4M19NVVRFWF9FT0ZfRFBJMAkJCShNVDgx ODNfTVVURVhfU09GX0RQSTAgPDwgNikNCj4gPiAgDQo+ID4gIHN0cnVjdCBtdGtfbXV0ZXggew0K PiA+ICAJaW50IGlkOw0KPiA+IEBAIC0xODEsNiArMjAxLDIwIEBAIHN0YXRpYyBjb25zdCB1bnNp Z25lZCBpbnQgbXQ4MTczX211dGV4X21vZFtERFBfQ09NUE9ORU5UX0lEX01BWF0gPSB7DQo+ID4g IAlbRERQX0NPTVBPTkVOVF9XRE1BMV0gPSBNVDgxNzNfTVVURVhfTU9EX0RJU1BfV0RNQTEsDQo+ ID4gIH07DQo+ID4gIA0KPiA+ICtzdGF0aWMgY29uc3QgdW5zaWduZWQgaW50IG10ODE4M19tdXRl eF9tb2RbRERQX0NPTVBPTkVOVF9JRF9NQVhdID0gew0KPiA+ICsJW0REUF9DT01QT05FTlRfQUFM MF0gPSBNVDgxODNfTVVURVhfTU9EX0RJU1BfQUFMMCwNCj4gPiArCVtERFBfQ09NUE9ORU5UX0ND T1JSXSA9IE1UODE4M19NVVRFWF9NT0RfRElTUF9DQ09SUjAsDQo+ID4gKwlbRERQX0NPTVBPTkVO VF9DT0xPUjBdID0gTVQ4MTgzX01VVEVYX01PRF9ESVNQX0NPTE9SMCwNCj4gPiArCVtERFBfQ09N UE9ORU5UX0RJVEhFUl0gPSBNVDgxODNfTVVURVhfTU9EX0RJU1BfRElUSEVSMCwNCj4gPiArCVtE RFBfQ09NUE9ORU5UX0dBTU1BXSA9IE1UODE4M19NVVRFWF9NT0RfRElTUF9HQU1NQTAsDQo+ID4g KwlbRERQX0NPTVBPTkVOVF9PVkwwXSA9IE1UODE4M19NVVRFWF9NT0RfRElTUF9PVkwwLA0KPiA+ ICsJW0REUF9DT01QT05FTlRfT1ZMXzJMMF0gPSBNVDgxODNfTVVURVhfTU9EX0RJU1BfT1ZMMF8y TCwNCj4gPiArCVtERFBfQ09NUE9ORU5UX09WTF8yTDFdID0gTVQ4MTgzX01VVEVYX01PRF9ESVNQ X09WTDFfMkwsDQo+ID4gKwlbRERQX0NPTVBPTkVOVF9SRE1BMF0gPSBNVDgxODNfTVVURVhfTU9E X0RJU1BfUkRNQTAsDQo+ID4gKwlbRERQX0NPTVBPTkVOVF9SRE1BMV0gPSBNVDgxODNfTVVURVhf TU9EX0RJU1BfUkRNQTEsDQo+ID4gKwlbRERQX0NPTVBPTkVOVF9XRE1BMF0gPSBNVDgxODNfTVVU RVhfTU9EX0RJU1BfV0RNQTAsDQo+ID4gK307DQo+ID4gKw0KPiA+ICBzdGF0aWMgY29uc3QgdW5z aWduZWQgaW50IG10MjcxMl9tdXRleF9zb2ZbTVVURVhfU09GX0RTSTMgKyAxXSA9IHsNCj4gPiAg CVtNVVRFWF9TT0ZfU0lOR0xFX01PREVdID0gTVVURVhfU09GX1NJTkdMRV9NT0RFLA0KPiA+ICAJ W01VVEVYX1NPRl9EU0kwXSA9IE1VVEVYX1NPRl9EU0kwLA0KPiA+IEBAIC0xOTgsNiArMjMyLDEy IEBAIHN0YXRpYyBjb25zdCB1bnNpZ25lZCBpbnQgbXQ4MTY3X211dGV4X3NvZltNVVRFWF9TT0Zf RFNJMyArIDFdID0gew0KPiA+ICAJW01VVEVYX1NPRl9EUEkxXSA9IE1UODE2N19NVVRFWF9TT0Zf RFBJMSwNCj4gPiAgfTsNCj4gPiAgDQo+ID4gK3N0YXRpYyBjb25zdCB1bnNpZ25lZCBpbnQgbXQ4 MTgzX211dGV4X3NvZltNVVRFWF9TT0ZfRFNJMyArIDFdID0gew0KPiA+ICsJW01VVEVYX1NPRl9T SU5HTEVfTU9ERV0gPSBNVVRFWF9TT0ZfU0lOR0xFX01PREUsDQo+ID4gKwlbTVVURVhfU09GX0RT STBdID0gTVVURVhfU09GX0RTSTAgfCBNVDgxODNfTVVURVhfRU9GX0RTSTAsDQo+ID4gKwlbTVVU RVhfU09GX0RQSTBdID0gTVQ4MTgzX01VVEVYX1NPRl9EUEkwIHwgTVQ4MTgzX01VVEVYX0VPRl9E UEkwLA0KPiANCj4gQWNjb3JkaW5nIHRvIGRpc2N1c3Npb24gaW4gWzFdLCBhZGQgY29tbWVudCBm b3IgdGhlIG9kZCBFT0Ygc2V0dGluZy4NCj4gDQo+IFsxXQ0KPiBodHRwczovL3BhdGNod29yay5r ZXJuZWwub3JnL3Byb2plY3QvbGludXgtbWVkaWF0ZWsvcGF0Y2gvMTU5NTQ2OTc5OC0zODI0LTgt Z2l0LXNlbmQtZW1haWwteW9uZ3FpYW5nLm5pdUBtZWRpYXRlay5jb20vDQo+IA0KPiBSZWdhcmRz LA0KPiBDSy4NCj4gDQo+IA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAgc3RhdGljIGNvbnN0IHN0cnVj dCBtdGtfbXV0ZXhfZGF0YSBtdDI3MDFfbXV0ZXhfZHJpdmVyX2RhdGEgPSB7DQo+ID4gIAkubXV0 ZXhfbW9kID0gbXQyNzAxX211dGV4X21vZCwNCj4gPiAgCS5tdXRleF9zb2YgPSBtdDI3MTJfbXV0 ZXhfc29mLA0KPiA+IEBAIC0yMjcsNiArMjY3LDE0IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRr X211dGV4X2RhdGEgbXQ4MTczX211dGV4X2RyaXZlcl9kYXRhID0gew0KPiA+ICAJLm11dGV4X3Nv Zl9yZWcgPSBNVDI3MDFfTVVURVgwX1NPRjAsDQo+ID4gIH07DQo+ID4gIA0KPiA+ICtzdGF0aWMg Y29uc3Qgc3RydWN0IG10a19tdXRleF9kYXRhIG10ODE4M19tdXRleF9kcml2ZXJfZGF0YSA9IHsN Cj4gPiArCS5tdXRleF9tb2QgPSBtdDgxODNfbXV0ZXhfbW9kLA0KPiA+ICsJLm11dGV4X3NvZiA9 IG10ODE4M19tdXRleF9zb2YsDQo+ID4gKwkubXV0ZXhfbW9kX3JlZyA9IE1UODE4M19ESVNQX01V VEVYMF9NT0QwLA0KPiA+ICsJLm11dGV4X3NvZl9yZWcgPSBNVDgxODNfRElTUF9NVVRFWDBfU09G MCwNCj4gPiArCS5ub19jbGsgPSB0cnVlLA0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAgc3RydWN0IG10 a19tdXRleCAqbXRrX211dGV4X2dldChzdHJ1Y3QgZGV2aWNlICpkZXYpDQo+ID4gIHsNCj4gPiAg CXN0cnVjdCBtdGtfbXV0ZXhfY3R4ICptdHggPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gPiBA QCAtNDU3LDYgKzUwNSw4IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIG11dGV4 X2RyaXZlcl9kdF9tYXRjaFtdID0gew0KPiA+ICAJICAuZGF0YSA9ICZtdDgxNjdfbXV0ZXhfZHJp dmVyX2RhdGF9LA0KPiA+ICAJeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGlzcC1t dXRleCIsDQo+ID4gIAkgIC5kYXRhID0gJm10ODE3M19tdXRleF9kcml2ZXJfZGF0YX0sDQo+ID4g Kwl7IC5jb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE4My1kaXNwLW11dGV4IiwNCj4gPiArCSAg LmRhdGEgPSAmbXQ4MTgzX211dGV4X2RyaXZlcl9kYXRhfSwNCj4gPiAgCXt9LA0KPiA+ICB9Ow0K PiA+ICBNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBtdXRleF9kcml2ZXJfZHRfbWF0Y2gpOw0KPiAN Cg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8B0AC433DB for ; Thu, 28 Jan 2021 06:20:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6564A64DC4 for ; Thu, 28 Jan 2021 06:20:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6564A64DC4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 702FA6E8DB; Thu, 28 Jan 2021 06:20:01 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 85ADA6E8DB for ; Thu, 28 Jan 2021 06:19:57 +0000 (UTC) X-UUID: 71f90608ce97483dad8d04b71034504f-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=9l/3qxAZieqX345ryvbLhbIWYhgxrPRb06fzhqIsH4I=; b=d7v5tLSxniZ5xBAoXnZJQv8bRx0TJIQBoyfXzNGUDXFsg6J8Jaqv0Avr/h8yiLqMy6XUOuVZG6bE1LVb80xeKxrXsOmS1v6xECZkv+b42I+C5kdJ4lMaFV6mji8NhwuyHyScDjFput8Euf/1dXzIeRik2+8VbJTio6e0eQrCWTw=; X-UUID: 71f90608ce97483dad8d04b71034504f-20210128 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1227452633; Thu, 28 Jan 2021 14:19:54 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 14:19:51 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 14:19:52 +0800 Message-ID: <1611814791.28312.12.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 14:19:51 +0800 In-Reply-To: <1611814421.28312.9.camel@mtksdaap41> References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 6B1B6152A535CF41E1E99F1F5C98B01A2969156BDD91B00DC1A7E800C4434FCC2000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote: > Hi, Hsin-Yi: > > Modify the title's prefix to 'soc: mediatek:' Modify more, the title should be 'soc: mediatek: add mtk mutex support for MT8183' > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > From: Yongqiang Niu > > > > Add DDP support for MT8183 SoC. > > > > Signed-off-by: Yongqiang Niu > > Signed-off-by: Hsin-Yi Wang > > --- > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > 1 file changed, 50 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > index f531b119da7a9..f64e9c33e85ad 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -14,6 +14,8 @@ > > > > #define MT2701_MUTEX0_MOD0 0x2c > > #define MT2701_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -37,6 +39,18 @@ > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -87,6 +101,12 @@ > > #define MT2712_MUTEX_SOF_DSI3 6 > > #define MT8167_MUTEX_SOF_DPI0 2 > > #define MT8167_MUTEX_SOF_DPI1 3 > > +#define MT8183_MUTEX_SOF_DSI0 1 > > +#define MT8183_MUTEX_SOF_DPI0 2 > > + > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > struct mtk_mutex { > > int id; > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > }; > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > According to discussion in [1], add comment for the odd EOF setting. > > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > Regards, > CK. > > > > +}; > > + > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > + .no_clk = true, > > +}; > > + > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > { > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > .data = &mt8167_mutex_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_mutex_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_mutex_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel