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Wed, 27 Jan 2021 23:00:41 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Jan 2021 23:00:18 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 15:00:11 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 15:00:11 +0800 Message-ID: <1611817211.8417.0.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 15:00:11 +0800 In-Reply-To: References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1028BAB7B3EECBBFEEF43CD5A0BE256A2A8A797E056769F2B56E920121122C782000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_020043_752293_74751D09 X-CRM114-Status: GOOD ( 23.88 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > Modify the title's prefix to 'soc: mediatek:' > > > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > Add DDP support for MT8183 SoC. > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > > 1 file changed, 50 insertions(+) > > > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > > index f531b119da7a9..f64e9c33e85ad 100644 > > > --- a/drivers/soc/mediatek/mtk-mutex.c > > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > > @@ -14,6 +14,8 @@ > > > > > > #define MT2701_MUTEX0_MOD0 0x2c > > > #define MT2701_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -37,6 +39,18 @@ > > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -87,6 +101,12 @@ > > > #define MT2712_MUTEX_SOF_DSI3 6 > > > #define MT8167_MUTEX_SOF_DPI0 2 > > > #define MT8167_MUTEX_SOF_DPI1 3 > > > +#define MT8183_MUTEX_SOF_DSI0 1 > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > + > > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > > Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred. I prefer to move comment to mt8183_mutex_sof. > > > > struct mtk_mutex { > > > int id; > > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > According to discussion in [1], add comment for the odd EOF setting. > > > > [1] > > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > > > Regards, > > CK. > > > > > > > +}; > > > + > > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > > }; > > > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > > + .mutex_mod = mt8183_mutex_mod, > > > + .mutex_sof = mt8183_mutex_sof, > > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > > + .no_clk = true, > > > +}; > > > + > > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > > { > > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > > .data = &mt8167_mutex_driver_data}, > > > { .compatible = "mediatek,mt8173-disp-mutex", > > > .data = &mt8173_mutex_driver_data}, > > > + { .compatible = "mediatek,mt8183-disp-mutex", > > > + .data = &mt8183_mutex_driver_data}, > > > {}, > > > }; > > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BB38C433E0 for ; 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Thu, 28 Jan 2021 15:00:11 +0800 Message-ID: <1611817211.8417.0.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 15:00:11 +0800 In-Reply-To: References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1028BAB7B3EECBBFEEF43CD5A0BE256A2A8A797E056769F2B56E920121122C782000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_020043_752293_74751D09 X-CRM114-Status: GOOD ( 23.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > Modify the title's prefix to 'soc: mediatek:' > > > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > Add DDP support for MT8183 SoC. > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > > 1 file changed, 50 insertions(+) > > > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > > index f531b119da7a9..f64e9c33e85ad 100644 > > > --- a/drivers/soc/mediatek/mtk-mutex.c > > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > > @@ -14,6 +14,8 @@ > > > > > > #define MT2701_MUTEX0_MOD0 0x2c > > > #define MT2701_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -37,6 +39,18 @@ > > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -87,6 +101,12 @@ > > > #define MT2712_MUTEX_SOF_DSI3 6 > > > #define MT8167_MUTEX_SOF_DPI0 2 > > > #define MT8167_MUTEX_SOF_DPI1 3 > > > +#define MT8183_MUTEX_SOF_DSI0 1 > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > + > > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > > Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred. I prefer to move comment to mt8183_mutex_sof. > > > > struct mtk_mutex { > > > int id; > > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > According to discussion in [1], add comment for the odd EOF setting. > > > > [1] > > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > > > Regards, > > CK. > > > > > > > +}; > > > + > > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > > }; > > > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > > + .mutex_mod = mt8183_mutex_mod, > > > + .mutex_sof = mt8183_mutex_sof, > > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > > + .no_clk = true, > > > +}; > > > + > > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > > { > > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > > .data = &mt8167_mutex_driver_data}, > > > { .compatible = "mediatek,mt8173-disp-mutex", > > > .data = &mt8173_mutex_driver_data}, > > > + { .compatible = "mediatek,mt8183-disp-mutex", > > > + .data = &mt8183_mutex_driver_data}, > > > {}, > > > }; > > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84ADFC4332B for ; Thu, 28 Jan 2021 07:01:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4450764D9D for ; Thu, 28 Jan 2021 07:01:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231299AbhA1HBR (ORCPT ); Thu, 28 Jan 2021 02:01:17 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:45603 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229652AbhA1HBF (ORCPT ); Thu, 28 Jan 2021 02:01:05 -0500 X-UUID: 53c6337884164a9c8e76455b57b23b75-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=iLD0cfC7OI5fd6re8bU20Diab017K7ENUU4aiw1sTXE=; b=Cf/lO6wX9eBaBUz9PiqMHChc/toAHxwkQh4DE5aS7NNfYoK4F/lmvQnJN3sFWSTyuNK+YVQ33Tlj5sKhneO+CIIKKyCCsKK+2uVMIGMRorh+iuLpFTv/YAW3qk3hfdAqmZXol22+bz1QqbQ0ECPmpkK8VJ2OhpyfjfPQVGdf2Xw=; X-UUID: 53c6337884164a9c8e76455b57b23b75-20210128 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1797207214; Thu, 28 Jan 2021 15:00:14 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 15:00:11 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 15:00:11 +0800 Message-ID: <1611817211.8417.0.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang CC: Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , dri-devel , Devicetree List , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" , , Yongqiang Niu Date: Thu, 28 Jan 2021 15:00:11 +0800 In-Reply-To: References: <20210127045422.2418917-1-hsinyi@chromium.org> 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(mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1797207214; Thu, 28 Jan 2021 15:00:14 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 15:00:11 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 15:00:11 +0800 Message-ID: <1611817211.8417.0.camel@mtksdaap41> Subject: Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183 From: CK Hu To: Hsin-Yi Wang Date: Thu, 28 Jan 2021 15:00:11 +0800 In-Reply-To: References: <20210127045422.2418917-1-hsinyi@chromium.org> <20210127045422.2418917-9-hsinyi@chromium.org> <1611814421.28312.9.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1028BAB7B3EECBBFEEF43CD5A0BE256A2A8A797E056769F2B56E920121122C782000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Devicetree List , David Airlie , lkml , dri-devel , Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, "moderated list:ARM/Mediatek SoC support" , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote: > On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote: > > > > Hi, Hsin-Yi: > > > > Modify the title's prefix to 'soc: mediatek:' > > > > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > Add DDP support for MT8183 SoC. > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++ > > > 1 file changed, 50 insertions(+) > > > > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > > > index f531b119da7a9..f64e9c33e85ad 100644 > > > --- a/drivers/soc/mediatek/mtk-mutex.c > > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > > @@ -14,6 +14,8 @@ > > > > > > #define MT2701_MUTEX0_MOD0 0x2c > > > #define MT2701_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > Modify 'DISP_MUTEX' to 'MUTEX' > > > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -37,6 +39,18 @@ > > > #define MT8167_MUTEX_MOD_DISP_DITHER 15 > > > #define MT8167_MUTEX_MOD_DISP_UFOE 16 > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -87,6 +101,12 @@ > > > #define MT2712_MUTEX_SOF_DSI3 6 > > > #define MT8167_MUTEX_SOF_DPI0 2 > > > #define MT8167_MUTEX_SOF_DPI1 3 > > > +#define MT8183_MUTEX_SOF_DSI0 1 > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > + > > > +/* Add EOF setting so overlay hardware can receive frame done irq */ > > > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > > > Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred. I prefer to move comment to mt8183_mutex_sof. > > > > struct mtk_mutex { > > > int id; > > > @@ -181,6 +201,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -198,6 +232,12 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > According to discussion in [1], add comment for the odd EOF setting. > > > > [1] > > https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang.niu@mediatek.com/ > > > > Regards, > > CK. > > > > > > > +}; > > > + > > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { > > > .mutex_sof_reg = MT2701_MUTEX0_SOF0, > > > }; > > > > > > +static const struct mtk_mutex_data mt8183_mutex_driver_data = { > > > + .mutex_mod = mt8183_mutex_mod, > > > + .mutex_sof = mt8183_mutex_sof, > > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > > + .no_clk = true, > > > +}; > > > + > > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > > { > > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > > @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > > > .data = &mt8167_mutex_driver_data}, > > > { .compatible = "mediatek,mt8173-disp-mutex", > > > .data = &mt8173_mutex_driver_data}, > > > + { .compatible = "mediatek,mt8183-disp-mutex", > > > + .data = &mt8183_mutex_driver_data}, > > > {}, > > > }; > > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel