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Thu, 28 Jan 2021 00:07:19 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:07:18 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:07:13 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:07:13 +0800 Message-ID: <1611821233.18369.4.camel@mtksdaap41> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: CK Hu To: Yongqiang Niu Date: Thu, 28 Jan 2021 16:07:13 +0800 In-Reply-To: <1611820770.1947.8.camel@mhfsdcap03> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 7125373E3B05CDB4A4B87CA844441DE521C7CB8D09FF63D4F85D2EC32626AA782000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_030835_276273_8652CCD3 X-CRM114-Status: GOOD ( 26.38 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > Hi, Hsin-Yi: > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > to improve the display quality > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > index 8173f709272be..e85625704d611 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > @@ -53,7 +53,9 @@ > > > #define DITHER_EN BIT(0) > > > #define DISP_DITHER_CFG 0x0020 > > > #define DITHER_RELAY_MODE BIT(0) > > > +#define DITHER_ENGINE_EN BIT(1) > > > #define DISP_DITHER_SIZE 0x0030 > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > { > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > + bool enable = false; > > > + > > > + /* default value for dither reg 5 to 14 */ > > > + const u32 dither_setting[] = { > > > + 0x00000000, /* 5 */ > > > + 0x00003002, /* 6 */ > > > + 0x00000000, /* 7 */ > > > + 0x00000000, /* 8 */ > > > + 0x00000000, /* 9 */ > > > + 0x00000000, /* 10 */ > > > + 0x00000000, /* 11 */ > > > + 0x00000011, /* 12 */ > > > + 0x00000000, /* 13 */ > > > + 0x00000000, /* 14 */ > > > > Could you explain what is this? > > this is dither 5 to dither 14 setting > this will be useless, we just need set dither 5 and dither 7 like > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > other value is same with hardware default value. > > > > > > > + }; > > > + > > > + if (bpc == 5 || bpc == 6) { > > > + enable = true; > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_NEW_BIT_MODE, > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > version is correct and previous version is incorrect? > > the new version set r g b 3 channel same, seams more reasonable > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here. Regards, CK > > > > Regards, > > CK > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > + } > > > + > > > + > > > + if (enable) { > > > + u32 idx; > > > + > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > + DITHER_REG(idx + 5)); > > > + } > > > + > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > } > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BED4C433E0 for ; Thu, 28 Jan 2021 08:10:14 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4AA064DA1 for ; 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Thu, 28 Jan 2021 00:07:19 -0800 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:07:18 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:07:13 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:07:13 +0800 Message-ID: <1611821233.18369.4.camel@mtksdaap41> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: CK Hu To: Yongqiang Niu Date: Thu, 28 Jan 2021 16:07:13 +0800 In-Reply-To: <1611820770.1947.8.camel@mhfsdcap03> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 7125373E3B05CDB4A4B87CA844441DE521C7CB8D09FF63D4F85D2EC32626AA782000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_030835_276273_8652CCD3 X-CRM114-Status: GOOD ( 26.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > Hi, Hsin-Yi: > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > to improve the display quality > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > index 8173f709272be..e85625704d611 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > @@ -53,7 +53,9 @@ > > > #define DITHER_EN BIT(0) > > > #define DISP_DITHER_CFG 0x0020 > > > #define DITHER_RELAY_MODE BIT(0) > > > +#define DITHER_ENGINE_EN BIT(1) > > > #define DISP_DITHER_SIZE 0x0030 > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > { > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > + bool enable = false; > > > + > > > + /* default value for dither reg 5 to 14 */ > > > + const u32 dither_setting[] = { > > > + 0x00000000, /* 5 */ > > > + 0x00003002, /* 6 */ > > > + 0x00000000, /* 7 */ > > > + 0x00000000, /* 8 */ > > > + 0x00000000, /* 9 */ > > > + 0x00000000, /* 10 */ > > > + 0x00000000, /* 11 */ > > > + 0x00000011, /* 12 */ > > > + 0x00000000, /* 13 */ > > > + 0x00000000, /* 14 */ > > > > Could you explain what is this? > > this is dither 5 to dither 14 setting > this will be useless, we just need set dither 5 and dither 7 like > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > other value is same with hardware default value. > > > > > > > + }; > > > + > > > + if (bpc == 5 || bpc == 6) { > > > + enable = true; > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_NEW_BIT_MODE, > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > version is correct and previous version is incorrect? > > the new version set r g b 3 channel same, seams more reasonable > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here. Regards, CK > > > > Regards, > > CK > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > + } > > > + > > > + > > > + if (enable) { > > > + u32 idx; > > > + > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > + DITHER_REG(idx + 5)); > > > + } > > > + > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > } > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4442C433DB for ; Thu, 28 Jan 2021 08:14:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FB1064DA1 for ; Thu, 28 Jan 2021 08:14:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbhA1INr (ORCPT ); Thu, 28 Jan 2021 03:13:47 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:10159 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231267AbhA1II6 (ORCPT ); Thu, 28 Jan 2021 03:08:58 -0500 X-UUID: 172936644968457cb39b00e4a6b166fc-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=6CR30uPgSC0vGefHc+o3hW4Gm8WLXb0k3nn8teLGDfM=; b=LEzwaOyZpy1TvRWG8yNnKKQwg5KHPXYEOwgrTg5OKvbpN/Ln5HwyEvZGf/WqWIZQhnexubvY7J25qILnnQHwxkd592dX2D/S9wcD1LKU2HsChN2uuS/rQjV4yt7100/62pg0gYCTtRZxp/p/bS5//TwOGKsMT99tDKVrT9igGXA=; X-UUID: 172936644968457cb39b00e4a6b166fc-20210128 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1695815952; Thu, 28 Jan 2021 16:07:17 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:07:13 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:07:13 +0800 Message-ID: <1611821233.18369.4.camel@mtksdaap41> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: CK Hu To: Yongqiang Niu CC: Hsin-Yi Wang , Philipp Zabel , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Thu, 28 Jan 2021 16:07:13 +0800 In-Reply-To: <1611820770.1947.8.camel@mhfsdcap03> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 7125373E3B05CDB4A4B87CA844441DE521C7CB8D09FF63D4F85D2EC32626AA782000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gVGh1LCAyMDIxLTAxLTI4IGF0IDE1OjU5ICswODAwLCBZb25ncWlhbmcgTml1IHdyb3RlOg0K PiBPbiBUaHUsIDIwMjEtMDEtMjggYXQgMTU6NDIgKzA4MDAsIENLIEh1IHdyb3RlOg0KPiA+IEhp LCBIc2luLVlpOg0KPiA+IA0KPiA+IE9uIFRodSwgMjAyMS0wMS0yOCBhdCAxNToyOCArMDgwMCwg SHNpbi1ZaSBXYW5nIHdyb3RlOg0KPiA+ID4gRnJvbTogWW9uZ3FpYW5nIE5pdSA8eW9uZ3FpYW5n Lm5pdUBtZWRpYXRlay5jb20+DQo+ID4gPiANCj4gPiA+IGZvciA1IG9yIDYgYnBjIHBhbmVsLCB3 ZSBuZWVkIGVuYWJsZSBkaXRoZXIgZnVuY3Rpb24NCj4gPiA+IHRvIGltcHJvdmUgdGhlIGRpc3Bs YXkgcXVhbGl0eQ0KPiA+ID4gDQo+ID4gPiBTaWduZWQtb2ZmLWJ5OiBZb25ncWlhbmcgTml1IDx5 b25ncWlhbmcubml1QG1lZGlhdGVrLmNvbT4NCj4gPiA+IFNpZ25lZC1vZmYtYnk6IEhzaW4tWWkg V2FuZyA8aHNpbnlpQGNocm9taXVtLm9yZz4NCj4gPiA+IC0tLQ0KPiA+ID4gIGRyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMgfCA0NCArKysrKysrKysrKysrKysrKysr Ky0NCj4gPiA+ICAxIGZpbGUgY2hhbmdlZCwgNDMgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigt KQ0KPiA+ID4gDQo+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kcm1fZGRwX2NvbXAuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9j b21wLmMNCj4gPiA+IGluZGV4IDgxNzNmNzA5MjcyYmUuLmU4NTYyNTcwNGQ2MTEgMTAwNjQ0DQo+ ID4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ ID4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ ID4gPiBAQCAtNTMsNyArNTMsOSBAQA0KPiA+ID4gICNkZWZpbmUgRElUSEVSX0VOCQkJCUJJVCgw KQ0KPiA+ID4gICNkZWZpbmUgRElTUF9ESVRIRVJfQ0ZHCQkJCTB4MDAyMA0KPiA+ID4gICNkZWZp bmUgRElUSEVSX1JFTEFZX01PREUJCQlCSVQoMCkNCj4gPiA+ICsjZGVmaW5lIERJVEhFUl9FTkdJ TkVfRU4JCQlCSVQoMSkNCj4gPiA+ICAjZGVmaW5lIERJU1BfRElUSEVSX1NJWkUJCQkweDAwMzAN Cj4gPiA+ICsjZGVmaW5lIERJVEhFUl9SRUcoaWR4KQkJCQkoMHgxMDAgKyAoaWR4KSAqIDQpDQo+ ID4gPiAgDQo+ID4gPiAgI2RlZmluZSBMVVRfMTBCSVRfTUFTSwkJCQkweDAzZmYNCj4gPiA+ICAN Cj4gPiA+IEBAIC0zMTMsOCArMzE1LDQ4IEBAIHN0YXRpYyB2b2lkIG10a19kaXRoZXJfY29uZmln KHN0cnVjdCBkZXZpY2UgKmRldiwgdW5zaWduZWQgaW50IHcsDQo+ID4gPiAgew0KPiA+ID4gIAlz dHJ1Y3QgbXRrX2RkcF9jb21wX2RldiAqcHJpdiA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiA+ ID4gIA0KPiA+ID4gKwlib29sIGVuYWJsZSA9IGZhbHNlOw0KPiA+ID4gKw0KPiA+ID4gKwkvKiBk ZWZhdWx0IHZhbHVlIGZvciBkaXRoZXIgcmVnIDUgdG8gMTQgKi8NCj4gPiA+ICsJY29uc3QgdTMy IGRpdGhlcl9zZXR0aW5nW10gPSB7DQo+ID4gPiArCQkweDAwMDAwMDAwLCAvKiA1ICovDQo+ID4g PiArCQkweDAwMDAzMDAyLCAvKiA2ICovDQo+ID4gPiArCQkweDAwMDAwMDAwLCAvKiA3ICovDQo+ ID4gPiArCQkweDAwMDAwMDAwLCAvKiA4ICovDQo+ID4gPiArCQkweDAwMDAwMDAwLCAvKiA5ICov DQo+ID4gPiArCQkweDAwMDAwMDAwLCAvKiAxMCAqLw0KPiA+ID4gKwkJMHgwMDAwMDAwMCwgLyog MTEgKi8NCj4gPiA+ICsJCTB4MDAwMDAwMTEsIC8qIDEyICovDQo+ID4gPiArCQkweDAwMDAwMDAw LCAvKiAxMyAqLw0KPiA+ID4gKwkJMHgwMDAwMDAwMCwgLyogMTQgKi8NCj4gPiANCj4gPiBDb3Vs ZCB5b3UgZXhwbGFpbiB3aGF0IGlzIHRoaXM/DQo+IA0KPiB0aGlzIGlzIGRpdGhlciA1IHRvIGRp dGhlciAxNCBzZXR0aW5nDQo+IHRoaXMgd2lsbCBiZSB1c2VsZXNzLCB3ZSBqdXN0IG5lZWQgc2V0 IGRpdGhlciA1IGFuZCBkaXRoZXIgNyBsaWtlIA0KPiBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCAw LCBjb21wLCBESVNQX0RJVEhFUl81KTsNCj4gbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgMCwgY29t cCwgRElTUF9ESVRIRVJfNyk7DQo+IG90aGVyIHZhbHVlIGlzIHNhbWUgd2l0aCBoYXJkd2FyZSBk ZWZhdWx0IHZhbHVlLg0KPiANCj4gDQo+ID4gDQo+ID4gPiArCX07DQo+ID4gPiArDQo+ID4gPiAr CWlmIChicGMgPT0gNSB8fCBicGMgPT0gNikgew0KPiA+ID4gKwkJZW5hYmxlID0gdHJ1ZTsNCj4g PiA+ICsJCW10a19kZHBfd3JpdGUoY21kcV9wa3QsDQo+ID4gPiArCQkJICAgICAgRElUSEVSX0xT Ql9FUlJfU0hJRlRfUihNVEtfTUFYX0JQQyAtIGJwYykgfA0KPiA+ID4gKwkJCSAgICAgIERJVEhF Ul9BRERfTFNISUZUX1IoTVRLX01BWF9CUEMgLSBicGMpIHwNCj4gPiA+ICsJCQkgICAgICBESVRI RVJfTkVXX0JJVF9NT0RFLA0KPiA+ID4gKwkJCSAgICAgICZwcml2LT5jbWRxX3JlZywgcHJpdi0+ cmVncywgRElUSEVSX1JFRygxNSkpOw0KPiA+ID4gKwkJbXRrX2RkcF93cml0ZShjbWRxX3BrdCwN Cj4gPiA+ICsJCQkgICAgICBESVRIRVJfTFNCX0VSUl9TSElGVF9CKE1US19NQVhfQlBDIC0gYnBj KSB8DQo+ID4gPiArCQkJICAgICAgRElUSEVSX0FERF9MU0hJRlRfQihNVEtfTUFYX0JQQyAtIGJw YykgfA0KPiA+ID4gKwkJCSAgICAgIERJVEhFUl9MU0JfRVJSX1NISUZUX0coTVRLX01BWF9CUEMg LSBicGMpIHwNCj4gPiA+ICsJCQkgICAgICBESVRIRVJfQUREX0xTSElGVF9HKE1US19NQVhfQlBD IC0gYnBjKSwNCj4gPiANCj4gPiBUaGlzIHJlc3VsdCBpbiAweDUwNTA1MDUwLCBidXQgcHJldmlv dXMgdmVyc2lvbiBpcyAweDUwNTA0MDQwLCBzbyB0aGlzDQo+ID4gdmVyc2lvbiBpcyBjb3JyZWN0 IGFuZCBwcmV2aW91cyB2ZXJzaW9uIGlzIGluY29ycmVjdD8NCj4gDQo+IHRoZSBuZXcgdmVyc2lv biBzZXQgciBnIGIgMyBjaGFubmVsIHNhbWUsIHNlYW1zIG1vcmUgcmVhc29uYWJsZQ0KPiANCj4g DQoNClNvIGFsbCB0aGUgc2V0dGluZyBvZiBESVNQX0RJVEhFUl81LCBESVNQX0RJVEhFUl83LCBE SVNQX0RJVEhFUl8xNSwNCkRJU1BfRElUSEVSXzE2IGlzIGlkZW50aWNhbCB0byBtdGtfZGl0aGVy X3NldCgpLCBzbyBjYWxsDQptdGtfZGl0aGVyX3NldCgpIGluc3RlYWQgb2YgZHVwbGljYXRpb24g aGVyZS4NCg0KUmVnYXJkcywNCkNLDQo+ID4gDQo+ID4gUmVnYXJkcywNCj4gPiBDSw0KPiA+IA0K PiA+ID4gKwkJCSAgICAgICZwcml2LT5jbWRxX3JlZywgcHJpdi0+cmVncywgRElUSEVSX1JFRygx NikpOw0KPiA+ID4gKwl9DQo+ID4gPiArDQo+ID4gPiArDQo+ID4gPiArCWlmIChlbmFibGUpIHsN Cj4gPiA+ICsJCXUzMiBpZHg7DQo+ID4gPiArDQo+ID4gPiArCQlmb3IgKGlkeCA9IDA7IGlkeCA8 IEFSUkFZX1NJWkUoZGl0aGVyX3NldHRpbmcpOyBpZHgrKykNCj4gPiA+ICsJCQltdGtfZGRwX3dy aXRlKGNtZHFfcGt0LCBkaXRoZXJfc2V0dGluZ1tpZHhdLCAmcHJpdi0+Y21kcV9yZWcsIHByaXYt PnJlZ3MsDQo+ID4gPiArCQkJCSAgICAgIERJVEhFUl9SRUcoaWR4ICsgNSkpOw0KPiA+ID4gKwl9 DQo+ID4gPiArDQo+ID4gPiAgCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGggPDwgMTYgfCB3LCAm cHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfRElUSEVSX1NJWkUpOw0KPiA+ID4gLQlt dGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBESVRIRVJfUkVMQVlfTU9ERSwgJnByaXYtPmNtZHFfcmVn LCBwcml2LT5yZWdzLCBESVNQX0RJVEhFUl9DRkcpOw0KPiA+ID4gKyAgICAgICAgbXRrX2RkcF93 cml0ZShjbWRxX3BrdCwgZW5hYmxlID8gRElUSEVSX0VOR0lORV9FTiA6IERJVEhFUl9SRUxBWV9N T0RFLCAmcHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfRElUSEVSX0NGRyk7DQo+ID4g PiAgfQ0KPiA+ID4gIA0KPiA+ID4gIHN0YXRpYyB2b2lkIG10a19kaXRoZXJfc3RhcnQoc3RydWN0 IGRldmljZSAqZGV2KQ0KPiA+IA0KPiA+IA0KPiANCj4gDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 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mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3058B6E429; Thu, 28 Jan 2021 08:07:25 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B5596E429 for ; Thu, 28 Jan 2021 08:07:20 +0000 (UTC) X-UUID: 172936644968457cb39b00e4a6b166fc-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=6CR30uPgSC0vGefHc+o3hW4Gm8WLXb0k3nn8teLGDfM=; b=LEzwaOyZpy1TvRWG8yNnKKQwg5KHPXYEOwgrTg5OKvbpN/Ln5HwyEvZGf/WqWIZQhnexubvY7J25qILnnQHwxkd592dX2D/S9wcD1LKU2HsChN2uuS/rQjV4yt7100/62pg0gYCTtRZxp/p/bS5//TwOGKsMT99tDKVrT9igGXA=; X-UUID: 172936644968457cb39b00e4a6b166fc-20210128 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1695815952; Thu, 28 Jan 2021 16:07:17 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:07:13 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:07:13 +0800 Message-ID: <1611821233.18369.4.camel@mtksdaap41> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: CK Hu To: Yongqiang Niu Date: Thu, 28 Jan 2021 16:07:13 +0800 In-Reply-To: <1611820770.1947.8.camel@mhfsdcap03> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 7125373E3B05CDB4A4B87CA844441DE521C7CB8D09FF63D4F85D2EC32626AA782000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > Hi, Hsin-Yi: > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > From: Yongqiang Niu > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > to improve the display quality > > > > > > Signed-off-by: Yongqiang Niu > > > Signed-off-by: Hsin-Yi Wang > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > index 8173f709272be..e85625704d611 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > @@ -53,7 +53,9 @@ > > > #define DITHER_EN BIT(0) > > > #define DISP_DITHER_CFG 0x0020 > > > #define DITHER_RELAY_MODE BIT(0) > > > +#define DITHER_ENGINE_EN BIT(1) > > > #define DISP_DITHER_SIZE 0x0030 > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > { > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > + bool enable = false; > > > + > > > + /* default value for dither reg 5 to 14 */ > > > + const u32 dither_setting[] = { > > > + 0x00000000, /* 5 */ > > > + 0x00003002, /* 6 */ > > > + 0x00000000, /* 7 */ > > > + 0x00000000, /* 8 */ > > > + 0x00000000, /* 9 */ > > > + 0x00000000, /* 10 */ > > > + 0x00000000, /* 11 */ > > > + 0x00000011, /* 12 */ > > > + 0x00000000, /* 13 */ > > > + 0x00000000, /* 14 */ > > > > Could you explain what is this? > > this is dither 5 to dither 14 setting > this will be useless, we just need set dither 5 and dither 7 like > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > other value is same with hardware default value. > > > > > > > + }; > > > + > > > + if (bpc == 5 || bpc == 6) { > > > + enable = true; > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > + DITHER_NEW_BIT_MODE, > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > + mtk_ddp_write(cmdq_pkt, > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > version is correct and previous version is incorrect? > > the new version set r g b 3 channel same, seams more reasonable > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here. Regards, CK > > > > Regards, > > CK > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > + } > > > + > > > + > > > + if (enable) { > > > + u32 idx; > > > + > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > + DITHER_REG(idx + 5)); > > > + } > > > + > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > } > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel