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Thu, 28 Jan 2021 00:10:01 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:09:59 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:09:58 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:09:57 +0800 Message-ID: <1611821396.1947.10.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:09:56 +0800 In-Reply-To: <1611821233.18369.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_031007_375596_1338FF36 X-CRM114-Status: GOOD ( 27.94 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > Hi, Hsin-Yi: > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > From: Yongqiang Niu > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > to improve the display quality > > > > > > > > Signed-off-by: Yongqiang Niu > > > > Signed-off-by: Hsin-Yi Wang > > > > --- > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > index 8173f709272be..e85625704d611 100644 > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > @@ -53,7 +53,9 @@ > > > > #define DITHER_EN BIT(0) > > > > #define DISP_DITHER_CFG 0x0020 > > > > #define DITHER_RELAY_MODE BIT(0) > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > #define DISP_DITHER_SIZE 0x0030 > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > { > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > + bool enable = false; > > > > + > > > > + /* default value for dither reg 5 to 14 */ > > > > + const u32 dither_setting[] = { > > > > + 0x00000000, /* 5 */ > > > > + 0x00003002, /* 6 */ > > > > + 0x00000000, /* 7 */ > > > > + 0x00000000, /* 8 */ > > > > + 0x00000000, /* 9 */ > > > > + 0x00000000, /* 10 */ > > > > + 0x00000000, /* 11 */ > > > > + 0x00000011, /* 12 */ > > > > + 0x00000000, /* 13 */ > > > > + 0x00000000, /* 14 */ > > > > > > Could you explain what is this? > > > > this is dither 5 to dither 14 setting > > this will be useless, we just need set dither 5 and dither 7 like > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > other value is same with hardware default value. > > > > > > > > > > > + }; > > > > + > > > > + if (bpc == 5 || bpc == 6) { > > > > + enable = true; > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_NEW_BIT_MODE, > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > version is correct and previous version is incorrect? > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > DISP_DITHER_16 is identical to mtk_dither_set(), so call > mtk_dither_set() instead of duplication here. > dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1 > Regards, > CK > > > > > > Regards, > > > CK > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > + } > > > > + > > > > + > > > > + if (enable) { > > > > + u32 idx; > > > > + > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > + DITHER_REG(idx + 5)); > > > > + } > > > > + > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > } > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE6BC433DB for ; Thu, 28 Jan 2021 08:11:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30AAF60C41 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52NX-0008AH-30; Thu, 28 Jan 2021 08:10:11 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52NS-00088y-3o; Thu, 28 Jan 2021 08:10:09 +0000 X-UUID: 4ef40994f3b141fe93ccbb6266de675b-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=3avhCwfwHncHem81Q76+RbeX5Zom5hg2AKdmxBBvpRI=; b=I7FXhgSs9DXCVcT6lyLI4GxsAlOt/F1GssHQWojcFhi7ngp2wb+8NIrtjq3njP6Q3/P++wePLz+mUOBh6xOi3Tui7SDmpBwvqPaR+Xg1Xy0lgf7ycRsJxVmA9Zl9YdZmndMfe5LaFuaLJSuVMhSWv7zT29vYLx5F3jH+enhdw0I=; X-UUID: 4ef40994f3b141fe93ccbb6266de675b-20210128 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 446076568; Thu, 28 Jan 2021 00:10:01 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:09:59 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:09:58 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:09:57 +0800 Message-ID: <1611821396.1947.10.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:09:56 +0800 In-Reply-To: <1611821233.18369.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_031007_375596_1338FF36 X-CRM114-Status: GOOD ( 27.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > Hi, Hsin-Yi: > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > From: Yongqiang Niu > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > to improve the display quality > > > > > > > > Signed-off-by: Yongqiang Niu > > > > Signed-off-by: Hsin-Yi Wang > > > > --- > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > index 8173f709272be..e85625704d611 100644 > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > @@ -53,7 +53,9 @@ > > > > #define DITHER_EN BIT(0) > > > > #define DISP_DITHER_CFG 0x0020 > > > > #define DITHER_RELAY_MODE BIT(0) > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > #define DISP_DITHER_SIZE 0x0030 > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > { > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > + bool enable = false; > > > > + > > > > + /* default value for dither reg 5 to 14 */ > > > > + const u32 dither_setting[] = { > > > > + 0x00000000, /* 5 */ > > > > + 0x00003002, /* 6 */ > > > > + 0x00000000, /* 7 */ > > > > + 0x00000000, /* 8 */ > > > > + 0x00000000, /* 9 */ > > > > + 0x00000000, /* 10 */ > > > > + 0x00000000, /* 11 */ > > > > + 0x00000011, /* 12 */ > > > > + 0x00000000, /* 13 */ > > > > + 0x00000000, /* 14 */ > > > > > > Could you explain what is this? > > > > this is dither 5 to dither 14 setting > > this will be useless, we just need set dither 5 and dither 7 like > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > other value is same with hardware default value. > > > > > > > > > > > + }; > > > > + > > > > + if (bpc == 5 || bpc == 6) { > > > > + enable = true; > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_NEW_BIT_MODE, > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > version is correct and previous version is incorrect? > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > DISP_DITHER_16 is identical to mtk_dither_set(), so call > mtk_dither_set() instead of duplication here. > dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1 > Regards, > CK > > > > > > Regards, > > > CK > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > + } > > > > + > > > > + > > > > + if (enable) { > > > > + u32 idx; > > > > + > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > + DITHER_REG(idx + 5)); > > > > + } > > > > + > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > } > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EFE7C433E0 for ; Thu, 28 Jan 2021 08:11:48 +0000 (UTC) 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c59e218c88054f03b15ebad6fd6f3928-20210128 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 783501041; Thu, 28 Jan 2021 16:09:59 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:09:58 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:09:57 +0800 Message-ID: <1611821396.1947.10.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu Reply-To: Yongqiang Niu To: CK Hu CC: Hsin-Yi Wang , Philipp Zabel , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Thu, 28 Jan 2021 16:09:56 +0800 In-Reply-To: <1611821233.18369.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gVGh1LCAyMDIxLTAxLTI4IGF0IDE2OjA3ICswODAwLCBDSyBIdSB3cm90ZToNCj4gT24gVGh1 LCAyMDIxLTAxLTI4IGF0IDE1OjU5ICswODAwLCBZb25ncWlhbmcgTml1IHdyb3RlOg0KPiA+IE9u IFRodSwgMjAyMS0wMS0yOCBhdCAxNTo0MiArMDgwMCwgQ0sgSHUgd3JvdGU6DQo+ID4gPiBIaSwg SHNpbi1ZaToNCj4gPiA+IA0KPiA+ID4gT24gVGh1LCAyMDIxLTAxLTI4IGF0IDE1OjI4ICswODAw LCBIc2luLVlpIFdhbmcgd3JvdGU6DQo+ID4gPiA+IEZyb206IFlvbmdxaWFuZyBOaXUgPHlvbmdx aWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiA+ID4gPiANCj4gPiA+ID4gZm9yIDUgb3IgNiBicGMg cGFuZWwsIHdlIG5lZWQgZW5hYmxlIGRpdGhlciBmdW5jdGlvbg0KPiA+ID4gPiB0byBpbXByb3Zl IHRoZSBkaXNwbGF5IHF1YWxpdHkNCj4gPiA+ID4gDQo+ID4gPiA+IFNpZ25lZC1vZmYtYnk6IFlv bmdxaWFuZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiA+ID4gPiBTaWduZWQt b2ZmLWJ5OiBIc2luLVlpIFdhbmcgPGhzaW55aUBjaHJvbWl1bS5vcmc+DQo+ID4gPiA+IC0tLQ0K PiA+ID4gPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYyB8IDQ0 ICsrKysrKysrKysrKysrKysrKysrLQ0KPiA+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDQzIGluc2Vy dGlvbnMoKyksIDEgZGVsZXRpb24oLSkNCj4gPiA+ID4gDQo+ID4gPiA+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jIGIvZHJpdmVycy9ncHUv ZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYw0KPiA+ID4gPiBpbmRleCA4MTczZjcwOTI3 MmJlLi5lODU2MjU3MDRkNjExIDEwMDY0NA0KPiA+ID4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+ID4gPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMNCj4gPiA+ID4gQEAgLTUzLDcgKzUzLDkgQEAN Cj4gPiA+ID4gICNkZWZpbmUgRElUSEVSX0VOCQkJCUJJVCgwKQ0KPiA+ID4gPiAgI2RlZmluZSBE SVNQX0RJVEhFUl9DRkcJCQkJMHgwMDIwDQo+ID4gPiA+ICAjZGVmaW5lIERJVEhFUl9SRUxBWV9N T0RFCQkJQklUKDApDQo+ID4gPiA+ICsjZGVmaW5lIERJVEhFUl9FTkdJTkVfRU4JCQlCSVQoMSkN Cj4gPiA+ID4gICNkZWZpbmUgRElTUF9ESVRIRVJfU0laRQkJCTB4MDAzMA0KPiA+ID4gPiArI2Rl ZmluZSBESVRIRVJfUkVHKGlkeCkJCQkJKDB4MTAwICsgKGlkeCkgKiA0KQ0KPiA+ID4gPiAgDQo+ ID4gPiA+ICAjZGVmaW5lIExVVF8xMEJJVF9NQVNLCQkJCTB4MDNmZg0KPiA+ID4gPiAgDQo+ID4g PiA+IEBAIC0zMTMsOCArMzE1LDQ4IEBAIHN0YXRpYyB2b2lkIG10a19kaXRoZXJfY29uZmlnKHN0 cnVjdCBkZXZpY2UgKmRldiwgdW5zaWduZWQgaW50IHcsDQo+ID4gPiA+ICB7DQo+ID4gPiA+ICAJ c3RydWN0IG10a19kZHBfY29tcF9kZXYgKnByaXYgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4g PiA+ID4gIA0KPiA+ID4gPiArCWJvb2wgZW5hYmxlID0gZmFsc2U7DQo+ID4gPiA+ICsNCj4gPiA+ ID4gKwkvKiBkZWZhdWx0IHZhbHVlIGZvciBkaXRoZXIgcmVnIDUgdG8gMTQgKi8NCj4gPiA+ID4g Kwljb25zdCB1MzIgZGl0aGVyX3NldHRpbmdbXSA9IHsNCj4gPiA+ID4gKwkJMHgwMDAwMDAwMCwg LyogNSAqLw0KPiA+ID4gPiArCQkweDAwMDAzMDAyLCAvKiA2ICovDQo+ID4gPiA+ICsJCTB4MDAw MDAwMDAsIC8qIDcgKi8NCj4gPiA+ID4gKwkJMHgwMDAwMDAwMCwgLyogOCAqLw0KPiA+ID4gPiAr CQkweDAwMDAwMDAwLCAvKiA5ICovDQo+ID4gPiA+ICsJCTB4MDAwMDAwMDAsIC8qIDEwICovDQo+ ID4gPiA+ICsJCTB4MDAwMDAwMDAsIC8qIDExICovDQo+ID4gPiA+ICsJCTB4MDAwMDAwMTEsIC8q IDEyICovDQo+ID4gPiA+ICsJCTB4MDAwMDAwMDAsIC8qIDEzICovDQo+ID4gPiA+ICsJCTB4MDAw MDAwMDAsIC8qIDE0ICovDQo+ID4gPiANCj4gPiA+IENvdWxkIHlvdSBleHBsYWluIHdoYXQgaXMg dGhpcz8NCj4gPiANCj4gPiB0aGlzIGlzIGRpdGhlciA1IHRvIGRpdGhlciAxNCBzZXR0aW5nDQo+ ID4gdGhpcyB3aWxsIGJlIHVzZWxlc3MsIHdlIGp1c3QgbmVlZCBzZXQgZGl0aGVyIDUgYW5kIGRp dGhlciA3IGxpa2UgDQo+ID4gbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgMCwgY29tcCwgRElTUF9E SVRIRVJfNSk7DQo+ID4gbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgMCwgY29tcCwgRElTUF9ESVRI RVJfNyk7DQo+ID4gb3RoZXIgdmFsdWUgaXMgc2FtZSB3aXRoIGhhcmR3YXJlIGRlZmF1bHQgdmFs dWUuDQo+ID4gDQo+ID4gDQo+ID4gPiANCj4gPiA+ID4gKwl9Ow0KPiA+ID4gPiArDQo+ID4gPiA+ ICsJaWYgKGJwYyA9PSA1IHx8IGJwYyA9PSA2KSB7DQo+ID4gPiA+ICsJCWVuYWJsZSA9IHRydWU7 DQo+ID4gPiA+ICsJCW10a19kZHBfd3JpdGUoY21kcV9wa3QsDQo+ID4gPiA+ICsJCQkgICAgICBE SVRIRVJfTFNCX0VSUl9TSElGVF9SKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ICsJCQkg ICAgICBESVRIRVJfQUREX0xTSElGVF9SKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ICsJ CQkgICAgICBESVRIRVJfTkVXX0JJVF9NT0RFLA0KPiA+ID4gPiArCQkJICAgICAgJnByaXYtPmNt ZHFfcmVnLCBwcml2LT5yZWdzLCBESVRIRVJfUkVHKDE1KSk7DQo+ID4gPiA+ICsJCW10a19kZHBf d3JpdGUoY21kcV9wa3QsDQo+ID4gPiA+ICsJCQkgICAgICBESVRIRVJfTFNCX0VSUl9TSElGVF9C KE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ICsJCQkgICAgICBESVRIRVJfQUREX0xTSElG VF9CKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ICsJCQkgICAgICBESVRIRVJfTFNCX0VS Ul9TSElGVF9HKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ICsJCQkgICAgICBESVRIRVJf QUREX0xTSElGVF9HKE1US19NQVhfQlBDIC0gYnBjKSwNCj4gPiA+IA0KPiA+ID4gVGhpcyByZXN1 bHQgaW4gMHg1MDUwNTA1MCwgYnV0IHByZXZpb3VzIHZlcnNpb24gaXMgMHg1MDUwNDA0MCwgc28g dGhpcw0KPiA+ID4gdmVyc2lvbiBpcyBjb3JyZWN0IGFuZCBwcmV2aW91cyB2ZXJzaW9uIGlzIGlu Y29ycmVjdD8NCj4gPiANCj4gPiB0aGUgbmV3IHZlcnNpb24gc2V0IHIgZyBiIDMgY2hhbm5lbCBz YW1lLCBzZWFtcyBtb3JlIHJlYXNvbmFibGUNCj4gPiANCj4gPiANCj4gDQo+IFNvIGFsbCB0aGUg c2V0dGluZyBvZiBESVNQX0RJVEhFUl81LCBESVNQX0RJVEhFUl83LCBESVNQX0RJVEhFUl8xNSwN Cj4gRElTUF9ESVRIRVJfMTYgaXMgaWRlbnRpY2FsIHRvIG10a19kaXRoZXJfc2V0KCksIHNvIGNh bGwNCj4gbXRrX2RpdGhlcl9zZXQoKSBpbnN0ZWFkIG9mIGR1cGxpY2F0aW9uIGhlcmUuDQo+IA0K DQpkaXRoZXIgZW5hYmxlIHNldCBpbiBtdGtfZGl0aGVyX3NldCBpcw0KbXRrX2RkcF93cml0ZShj bWRxX3BrdCwgRElTUF9ESVRIRVJJTkcsIGNvbXAsIENGRyk7DQoNCnRoYXQgaXMgZGlmZmVyZW50 IDgxODMgYW5kIG10ODE5Mi4NCm10ODE3MyBkaXRoZXIgZW5hYmxlIGluIGdhbW1hIGlzIGJpdDIN Cm10ODE4MyBhbmQgbXQ4MTkyIGRpdGhlciBlbmdpbmUgZW5hYmxlIGlzIGJpdCAxDQoNCg0KPiBS ZWdhcmRzLA0KPiBDSw0KPiA+ID4gDQo+ID4gPiBSZWdhcmRzLA0KPiA+ID4gQ0sNCj4gPiA+IA0K PiA+ID4gPiArCQkJICAgICAgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVRIRVJfUkVH KDE2KSk7DQo+ID4gPiA+ICsJfQ0KPiA+ID4gPiArDQo+ID4gPiA+ICsNCj4gPiA+ID4gKwlpZiAo ZW5hYmxlKSB7DQo+ID4gPiA+ICsJCXUzMiBpZHg7DQo+ID4gPiA+ICsNCj4gPiA+ID4gKwkJZm9y IChpZHggPSAwOyBpZHggPCBBUlJBWV9TSVpFKGRpdGhlcl9zZXR0aW5nKTsgaWR4KyspDQo+ID4g PiA+ICsJCQltdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBkaXRoZXJfc2V0dGluZ1tpZHhdLCAmcHJp di0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsDQo+ID4gPiA+ICsJCQkJICAgICAgRElUSEVSX1JFRyhp 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08:16:55 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTP id 54DE26E8F7 for ; Thu, 28 Jan 2021 08:10:01 +0000 (UTC) X-UUID: c59e218c88054f03b15ebad6fd6f3928-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=3avhCwfwHncHem81Q76+RbeX5Zom5hg2AKdmxBBvpRI=; b=I7FXhgSs9DXCVcT6lyLI4GxsAlOt/F1GssHQWojcFhi7ngp2wb+8NIrtjq3njP6Q3/P++wePLz+mUOBh6xOi3Tui7SDmpBwvqPaR+Xg1Xy0lgf7ycRsJxVmA9Zl9YdZmndMfe5LaFuaLJSuVMhSWv7zT29vYLx5F3jH+enhdw0I=; X-UUID: c59e218c88054f03b15ebad6fd6f3928-20210128 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 783501041; Thu, 28 Jan 2021 16:09:59 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:09:58 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:09:57 +0800 Message-ID: <1611821396.1947.10.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:09:56 +0800 In-Reply-To: <1611821233.18369.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Thu, 28 Jan 2021 08:15:36 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > Hi, Hsin-Yi: > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > From: Yongqiang Niu > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > to improve the display quality > > > > > > > > Signed-off-by: Yongqiang Niu > > > > Signed-off-by: Hsin-Yi Wang > > > > --- > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > index 8173f709272be..e85625704d611 100644 > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > @@ -53,7 +53,9 @@ > > > > #define DITHER_EN BIT(0) > > > > #define DISP_DITHER_CFG 0x0020 > > > > #define DITHER_RELAY_MODE BIT(0) > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > #define DISP_DITHER_SIZE 0x0030 > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > { > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > + bool enable = false; > > > > + > > > > + /* default value for dither reg 5 to 14 */ > > > > + const u32 dither_setting[] = { > > > > + 0x00000000, /* 5 */ > > > > + 0x00003002, /* 6 */ > > > > + 0x00000000, /* 7 */ > > > > + 0x00000000, /* 8 */ > > > > + 0x00000000, /* 9 */ > > > > + 0x00000000, /* 10 */ > > > > + 0x00000000, /* 11 */ > > > > + 0x00000011, /* 12 */ > > > > + 0x00000000, /* 13 */ > > > > + 0x00000000, /* 14 */ > > > > > > Could you explain what is this? > > > > this is dither 5 to dither 14 setting > > this will be useless, we just need set dither 5 and dither 7 like > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > other value is same with hardware default value. > > > > > > > > > > > + }; > > > > + > > > > + if (bpc == 5 || bpc == 6) { > > > > + enable = true; > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > + DITHER_NEW_BIT_MODE, > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > + mtk_ddp_write(cmdq_pkt, > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > version is correct and previous version is incorrect? > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > DISP_DITHER_16 is identical to mtk_dither_set(), so call > mtk_dither_set() instead of duplication here. > dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1 > Regards, > CK > > > > > > Regards, > > > CK > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > + } > > > > + > > > > + > > > > + if (enable) { > > > > + u32 idx; > > > > + > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > + DITHER_REG(idx + 5)); > > > > + } > > > > + > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > } > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel