From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A22EC433E0 for ; Thu, 28 Jan 2021 08:32:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F0AE264DCE for ; Thu, 28 Jan 2021 08:32:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F0AE264DCE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:Reply-To:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KCrX5BYBfhmbtTdIEE9+kIp2SPHn1jKrAGzP2KG5yVA=; b=k/DvvZ3ywRIn3UkNH+o5Jxzrb9 PGCkDJcCuy1CGOSf261VqVwJEtOEfExVhfWG4b1gcATAhviyeG+cXPEq9Vs1xeTwDiOQLLQMjia81 IAR3YVv6sH/T0uOTjoK7rla6El5dBRhERC+SJgFeyyMryVImDaERrmDHnth78kGdT/BbZcut/ZeDJ caAeuFidWDl2oMYpS9cbHByajNvkxfDMkH41DuJ9fW4RLcAqgGh4vyL//u5Bu9j+PPsXuXd3WA13c UH7wmmwzSssCtcIbaNTZQ5uZj5Y9v4T4yVB95KEZnGe1XhjwkyQ3eR2MnwELSJWWkBlQex4TkluEd dk/tB1xg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52j0-00036a-NX; Thu, 28 Jan 2021 08:32:22 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52it-00034v-Lk; Thu, 28 Jan 2021 08:32:17 +0000 X-UUID: 9264bfb4337746659b401e5f23ae4833-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=1Sbm2bZx8k7nPtcDPxuTnvVWvjkL3PfNcHBHr0kDrP4=; b=XgOom+NZuSw6GbO1v+oy48NVP6zKz/qGNZGx9JElnks5YNK7LMOm57zCVGGpM0Hkxvws+VGWjA2XxuxzjEY60hFEZTmZXp2WXh9jM3vv6WgdqO6ct0ZYFrjqmWmdq5I2f4obfazqtTyCbzS/DK5Itf4DrKuh7nXCHwANKWBGrjg=; X-UUID: 9264bfb4337746659b401e5f23ae4833-20210128 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 201340565; Thu, 28 Jan 2021 00:32:13 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:32:11 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:32:10 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:32:09 +0800 Message-ID: <1611822729.1947.14.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:32:09 +0800 In-Reply-To: <1611822524.23925.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> <1611822524.23925.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_033215_950053_32D131BE X-CRM114-Status: GOOD ( 34.55 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > > wrote: > > > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > > Hi, Hsin-Yi: > > > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > > From: Yongqiang Niu > > > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > > to improve the display quality > > > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > > --- > > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > @@ -53,7 +53,9 @@ > > > > > > > #define DITHER_EN BIT(0) > > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > > { > > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > > > + bool enable = false; > > > > > > > + > > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > > + const u32 dither_setting[] = { > > > > > > > + 0x00000000, /* 5 */ > > > > > > > + 0x00003002, /* 6 */ > > > > > > > + 0x00000000, /* 7 */ > > > > > > > + 0x00000000, /* 8 */ > > > > > > > + 0x00000000, /* 9 */ > > > > > > > + 0x00000000, /* 10 */ > > > > > > > + 0x00000000, /* 11 */ > > > > > > > + 0x00000011, /* 12 */ > > > > > > > + 0x00000000, /* 13 */ > > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > > > Could you explain what is this? > > > > > > > > > > this is dither 5 to dither 14 setting > > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > > > > > + }; > > > > > > > + > > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > > + enable = true; > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > > version is correct and previous version is incorrect? > > > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > > mtk_dither_set() instead of duplication here. > > > > > > > > > > dither enable set in mtk_dither_set is > > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > > > that is different 8183 and mt8192. > > > mt8173 dither enable in gamma is bit2 > > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > > will be set to bit2, > > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > > will be correct back to bit 1. > > > > Is this reasonable? > > Looks weird. Maybe pass some information into mtk_dither_set() to set > DISP_DITHERING correctly. > > I find one thing need to be fixed. CFG should be lower case. we could modify this like this: void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int cfg, u32 dither_enable, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, dither_enable, comp, cfg); > > Regards, > CK > > > > > > > Regards, > > > > CK > > > > > > > > > > > > Regards, > > > > > > CK > > > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > > + } > > > > > > > + > > > > > > > + > > > > > > > + if (enable) { > > > > > > > + u32 idx; > > > > > > > + > > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > > + DITHER_REG(idx + 5)); > > > > > > > + } > > > > > > > + > > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > } > > > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4616BC433DB for ; Thu, 28 Jan 2021 08:33:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0FC364DBD for ; Thu, 28 Jan 2021 08:33:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0FC364DBD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:Reply-To:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Date:To:From: Subject:Message-ID:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dng5Ezq8r6WSuY50QzVmxUPGEfijjzdypUteXpQy+VE=; b=3MRik5GzPQKJXpiy0kN/Lbs0RT TI6CM4KLrvmQqNN9Yk12/2DgUac2oS099Ad1N7ajou4Z8lMPSP8O1A+mHwSF5C4b7uQnVRXo+/dBO QnBuz0M1al0H4Dz6Or32i4wiN6SMbaLpflcHHkRA3QlQPpQy8/Ex1M0rn1IwxpyDOtoYH29VAIuFy 1sXzI7HvRF8GW6hrP2k54+aGvdpFQ7AiJt8+QVluZQa/il9SEvv8d+YFPkqktzEwiX24NNWkQ78Nc bYrxvS4oRK7tOeioGx+A+xRIcPYaeW1uPwOIRgMbPZu9P5qokWy3pog6a3i0hdVRoOqnxCJzrTXmu 17o6JMQg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52iy-000362-B9; Thu, 28 Jan 2021 08:32:20 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l52it-00034v-Lk; Thu, 28 Jan 2021 08:32:17 +0000 X-UUID: 9264bfb4337746659b401e5f23ae4833-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=1Sbm2bZx8k7nPtcDPxuTnvVWvjkL3PfNcHBHr0kDrP4=; b=XgOom+NZuSw6GbO1v+oy48NVP6zKz/qGNZGx9JElnks5YNK7LMOm57zCVGGpM0Hkxvws+VGWjA2XxuxzjEY60hFEZTmZXp2WXh9jM3vv6WgdqO6ct0ZYFrjqmWmdq5I2f4obfazqtTyCbzS/DK5Itf4DrKuh7nXCHwANKWBGrjg=; X-UUID: 9264bfb4337746659b401e5f23ae4833-20210128 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 201340565; Thu, 28 Jan 2021 00:32:13 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 00:32:11 -0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:32:10 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:32:09 +0800 Message-ID: <1611822729.1947.14.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:32:09 +0800 In-Reply-To: <1611822524.23925.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> <1611822524.23925.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210128_033215_950053_32D131BE X-CRM114-Status: GOOD ( 34.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , Philipp Zabel , David Airlie , lkml , dri-devel , "moderated list:ARM/Mediatek SoC support" , Daniel Vetter , Hsin-Yi Wang , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > > wrote: > > > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > > Hi, Hsin-Yi: > > > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > > From: Yongqiang Niu > > > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > > to improve the display quality > > > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > > --- > > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > @@ -53,7 +53,9 @@ > > > > > > > #define DITHER_EN BIT(0) > > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > > { > > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > > > + bool enable = false; > > > > > > > + > > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > > + const u32 dither_setting[] = { > > > > > > > + 0x00000000, /* 5 */ > > > > > > > + 0x00003002, /* 6 */ > > > > > > > + 0x00000000, /* 7 */ > > > > > > > + 0x00000000, /* 8 */ > > > > > > > + 0x00000000, /* 9 */ > > > > > > > + 0x00000000, /* 10 */ > > > > > > > + 0x00000000, /* 11 */ > > > > > > > + 0x00000011, /* 12 */ > > > > > > > + 0x00000000, /* 13 */ > > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > > > Could you explain what is this? > > > > > > > > > > this is dither 5 to dither 14 setting > > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > > > > > + }; > > > > > > > + > > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > > + enable = true; > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > > version is correct and previous version is incorrect? > > > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > > mtk_dither_set() instead of duplication here. > > > > > > > > > > dither enable set in mtk_dither_set is > > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > > > that is different 8183 and mt8192. > > > mt8173 dither enable in gamma is bit2 > > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > > will be set to bit2, > > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > > will be correct back to bit 1. > > > > Is this reasonable? > > Looks weird. Maybe pass some information into mtk_dither_set() to set > DISP_DITHERING correctly. > > I find one thing need to be fixed. CFG should be lower case. we could modify this like this: void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int cfg, u32 dither_enable, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, dither_enable, comp, cfg); > > Regards, > CK > > > > > > > Regards, > > > > CK > > > > > > > > > > > > Regards, > > > > > > CK > > > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > > + } > > > > > > > + > > > > > > > + > > > > > > > + if (enable) { > > > > > > > + u32 idx; > > > > > > > + > > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > > + DITHER_REG(idx + 5)); > > > > > > > + } > > > > > > > + > > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > } > > > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AFCDC433E6 for ; Thu, 28 Jan 2021 08:33:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 033D864DCE for ; Thu, 28 Jan 2021 08:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231768AbhA1Ic7 (ORCPT ); Thu, 28 Jan 2021 03:32:59 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:53804 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231350AbhA1Ic4 (ORCPT ); Thu, 28 Jan 2021 03:32:56 -0500 X-UUID: fb5a23f0169b43ddbe1bf112a2d12fc9-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=1Sbm2bZx8k7nPtcDPxuTnvVWvjkL3PfNcHBHr0kDrP4=; b=XgOom+NZuSw6GbO1v+oy48NVP6zKz/qGNZGx9JElnks5YNK7LMOm57zCVGGpM0Hkxvws+VGWjA2XxuxzjEY60hFEZTmZXp2WXh9jM3vv6WgdqO6ct0ZYFrjqmWmdq5I2f4obfazqtTyCbzS/DK5Itf4DrKuh7nXCHwANKWBGrjg=; X-UUID: fb5a23f0169b43ddbe1bf112a2d12fc9-20210128 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1102789290; Thu, 28 Jan 2021 16:32:11 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:32:10 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:32:09 +0800 Message-ID: <1611822729.1947.14.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu Reply-To: Yongqiang Niu To: CK Hu CC: Hsin-Yi Wang , Philipp Zabel , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , dri-devel , Devicetree List , lkml , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" Date: Thu, 28 Jan 2021 16:32:09 +0800 In-Reply-To: <1611822524.23925.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> <1611822524.23925.4.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org T24gVGh1LCAyMDIxLTAxLTI4IGF0IDE2OjI4ICswODAwLCBDSyBIdSB3cm90ZToNCj4gT24gVGh1 LCAyMDIxLTAxLTI4IGF0IDE2OjE4ICswODAwLCBIc2luLVlpIFdhbmcgd3JvdGU6DQo+ID4gT24g VGh1LCBKYW4gMjgsIDIwMjEgYXQgNDoxMCBQTSBZb25ncWlhbmcgTml1DQo+ID4gPHlvbmdxaWFu Zy5uaXVAbWVkaWF0ZWsuY29tPiB3cm90ZToNCj4gPiA+DQo+ID4gPiBPbiBUaHUsIDIwMjEtMDEt MjggYXQgMTY6MDcgKzA4MDAsIENLIEh1IHdyb3RlOg0KPiA+ID4gPiBPbiBUaHUsIDIwMjEtMDEt MjggYXQgMTU6NTkgKzA4MDAsIFlvbmdxaWFuZyBOaXUgd3JvdGU6DQo+ID4gPiA+ID4gT24gVGh1 LCAyMDIxLTAxLTI4IGF0IDE1OjQyICswODAwLCBDSyBIdSB3cm90ZToNCj4gPiA+ID4gPiA+IEhp LCBIc2luLVlpOg0KPiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+IE9uIFRodSwgMjAyMS0wMS0yOCBh dCAxNToyOCArMDgwMCwgSHNpbi1ZaSBXYW5nIHdyb3RlOg0KPiA+ID4gPiA+ID4gPiBGcm9tOiBZ b25ncWlhbmcgTml1IDx5b25ncWlhbmcubml1QG1lZGlhdGVrLmNvbT4NCj4gPiA+ID4gPiA+ID4N Cj4gPiA+ID4gPiA+ID4gZm9yIDUgb3IgNiBicGMgcGFuZWwsIHdlIG5lZWQgZW5hYmxlIGRpdGhl ciBmdW5jdGlvbg0KPiA+ID4gPiA+ID4gPiB0byBpbXByb3ZlIHRoZSBkaXNwbGF5IHF1YWxpdHkN Cj4gPiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+ID4gU2lnbmVkLW9mZi1ieTogWW9uZ3FpYW5nIE5p dSA8eW9uZ3FpYW5nLm5pdUBtZWRpYXRlay5jb20+DQo+ID4gPiA+ID4gPiA+IFNpZ25lZC1vZmYt Ynk6IEhzaW4tWWkgV2FuZyA8aHNpbnlpQGNocm9taXVtLm9yZz4NCj4gPiA+ID4gPiA+ID4gLS0t DQo+ID4gPiA+ID4gPiA+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29t cC5jIHwgNDQgKysrKysrKysrKysrKysrKysrKystDQo+ID4gPiA+ID4gPiA+ICAxIGZpbGUgY2hh bmdlZCwgNDMgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQ0KPiA+ID4gPiA+ID4gPg0KPiA+ ID4gPiA+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1f ZGRwX2NvbXAuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMN Cj4gPiA+ID4gPiA+ID4gaW5kZXggODE3M2Y3MDkyNzJiZS4uZTg1NjI1NzA0ZDYxMSAxMDA2NDQN Cj4gPiA+ID4gPiA+ID4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRw X2NvbXAuYw0KPiA+ID4gPiA+ID4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRr X2RybV9kZHBfY29tcC5jDQo+ID4gPiA+ID4gPiA+IEBAIC01Myw3ICs1Myw5IEBADQo+ID4gPiA+ ID4gPiA+ICAjZGVmaW5lIERJVEhFUl9FTiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEJJ VCgwKQ0KPiA+ID4gPiA+ID4gPiAgI2RlZmluZSBESVNQX0RJVEhFUl9DRkcgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIDB4MDAyMA0KPiA+ID4gPiA+ID4gPiAgI2RlZmluZSBESVRIRVJf UkVMQVlfTU9ERSAgICAgICAgICAgICAgICAgICAgICBCSVQoMCkNCj4gPiA+ID4gPiA+ID4gKyNk ZWZpbmUgRElUSEVSX0VOR0lORV9FTiAgICAgICAgICAgICAgICAgICAgICAgQklUKDEpDQo+ID4g PiA+ID4gPiA+ICAjZGVmaW5lIERJU1BfRElUSEVSX1NJWkUgICAgICAgICAgICAgICAgICAgICAg IDB4MDAzMA0KPiA+ID4gPiA+ID4gPiArI2RlZmluZSBESVRIRVJfUkVHKGlkeCkgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICgweDEwMCArIChpZHgpICogNCkNCj4gPiA+ID4gPiA+ID4N Cj4gPiA+ID4gPiA+ID4gICNkZWZpbmUgTFVUXzEwQklUX01BU0sgICAgICAgICAgICAgICAgICAg ICAgICAgMHgwM2ZmDQo+ID4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiA+IEBAIC0zMTMsOCArMzE1 LDQ4IEBAIHN0YXRpYyB2b2lkIG10a19kaXRoZXJfY29uZmlnKHN0cnVjdCBkZXZpY2UgKmRldiwg dW5zaWduZWQgaW50IHcsDQo+ID4gPiA+ID4gPiA+ICB7DQo+ID4gPiA+ID4gPiA+ICAgICAgICAg c3RydWN0IG10a19kZHBfY29tcF9kZXYgKnByaXYgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4g PiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+ID4gKyAgICAgICBib29sIGVuYWJsZSA9IGZhbHNlOw0K PiA+ID4gPiA+ID4gPiArDQo+ID4gPiA+ID4gPiA+ICsgICAgICAgLyogZGVmYXVsdCB2YWx1ZSBm b3IgZGl0aGVyIHJlZyA1IHRvIDE0ICovDQo+ID4gPiA+ID4gPiA+ICsgICAgICAgY29uc3QgdTMy IGRpdGhlcl9zZXR0aW5nW10gPSB7DQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAw MDAwMDAwLCAvKiA1ICovDQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAzMDAy LCAvKiA2ICovDQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiA3 ICovDQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiA4ICovDQo+ ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiA5ICovDQo+ID4gPiA+ ID4gPiA+ICsgICAgICAgICAgICAgICAweDAwMDAwMDAwLCAvKiAxMCAqLw0KPiA+ID4gPiA+ID4g PiArICAgICAgICAgICAgICAgMHgwMDAwMDAwMCwgLyogMTEgKi8NCj4gPiA+ID4gPiA+ID4gKyAg ICAgICAgICAgICAgIDB4MDAwMDAwMTEsIC8qIDEyICovDQo+ID4gPiA+ID4gPiA+ICsgICAgICAg ICAgICAgICAweDAwMDAwMDAwLCAvKiAxMyAqLw0KPiA+ID4gPiA+ID4gPiArICAgICAgICAgICAg ICAgMHgwMDAwMDAwMCwgLyogMTQgKi8NCj4gPiA+ID4gPiA+DQo+ID4gPiA+ID4gPiBDb3VsZCB5 b3UgZXhwbGFpbiB3aGF0IGlzIHRoaXM/DQo+ID4gPiA+ID4NCj4gPiA+ID4gPiB0aGlzIGlzIGRp dGhlciA1IHRvIGRpdGhlciAxNCBzZXR0aW5nDQo+ID4gPiA+ID4gdGhpcyB3aWxsIGJlIHVzZWxl c3MsIHdlIGp1c3QgbmVlZCBzZXQgZGl0aGVyIDUgYW5kIGRpdGhlciA3IGxpa2UNCj4gPiA+ID4g PiBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCAwLCBjb21wLCBESVNQX0RJVEhFUl81KTsNCj4gPiA+ ID4gPiBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCAwLCBjb21wLCBESVNQX0RJVEhFUl83KTsNCj4g PiA+ID4gPiBvdGhlciB2YWx1ZSBpcyBzYW1lIHdpdGggaGFyZHdhcmUgZGVmYXVsdCB2YWx1ZS4N Cj4gPiA+ID4gPg0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4gPiArICAgICAg IH07DQo+ID4gPiA+ID4gPiA+ICsNCj4gPiA+ID4gPiA+ID4gKyAgICAgICBpZiAoYnBjID09IDUg fHwgYnBjID09IDYpIHsNCj4gPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgIGVuYWJsZSA9IHRy dWU7DQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0 LA0KPiA+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICBESVRIRVJfTFNC X0VSUl9TSElGVF9SKE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ID4gPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIERJVEhFUl9BRERfTFNISUZUX1IoTVRLX01BWF9CUEMgLSBi cGMpIHwNCj4gPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgRElUSEVS X05FV19CSVRfTU9ERSwNCj4gPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVRIRVJfUkVHKDE1KSk7DQo+ID4gPiA+ ID4gPiA+ICsgICAgICAgICAgICAgICBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LA0KPiA+ID4gPiA+ ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICBESVRIRVJfTFNCX0VSUl9TSElGVF9C KE1US19NQVhfQlBDIC0gYnBjKSB8DQo+ID4gPiA+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIERJVEhFUl9BRERfTFNISUZUX0IoTVRLX01BWF9CUEMgLSBicGMpIHwNCj4gPiA+ ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgRElUSEVSX0xTQl9FUlJfU0hJ RlRfRyhNVEtfTUFYX0JQQyAtIGJwYykgfA0KPiA+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgICAgICAgICBESVRIRVJfQUREX0xTSElGVF9HKE1US19NQVhfQlBDIC0gYnBjKSwNCj4g PiA+ID4gPiA+DQo+ID4gPiA+ID4gPiBUaGlzIHJlc3VsdCBpbiAweDUwNTA1MDUwLCBidXQgcHJl dmlvdXMgdmVyc2lvbiBpcyAweDUwNTA0MDQwLCBzbyB0aGlzDQo+ID4gPiA+ID4gPiB2ZXJzaW9u IGlzIGNvcnJlY3QgYW5kIHByZXZpb3VzIHZlcnNpb24gaXMgaW5jb3JyZWN0Pw0KPiA+ID4gPiA+ DQo+ID4gPiA+ID4gdGhlIG5ldyB2ZXJzaW9uIHNldCByIGcgYiAzIGNoYW5uZWwgc2FtZSwgc2Vh bXMgbW9yZSByZWFzb25hYmxlDQo+ID4gPiA+ID4NCj4gPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4g PiBTbyBhbGwgdGhlIHNldHRpbmcgb2YgRElTUF9ESVRIRVJfNSwgRElTUF9ESVRIRVJfNywgRElT UF9ESVRIRVJfMTUsDQo+ID4gPiA+IERJU1BfRElUSEVSXzE2IGlzIGlkZW50aWNhbCB0byBtdGtf ZGl0aGVyX3NldCgpLCBzbyBjYWxsDQo+ID4gPiA+IG10a19kaXRoZXJfc2V0KCkgaW5zdGVhZCBv ZiBkdXBsaWNhdGlvbiBoZXJlLg0KPiA+ID4gPg0KPiA+ID4NCj4gPiA+IGRpdGhlciBlbmFibGUg c2V0IGluIG10a19kaXRoZXJfc2V0IGlzDQo+ID4gPiBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBE SVNQX0RJVEhFUklORywgY29tcCwgQ0ZHKTsNCj4gPiA+DQo+ID4gPiB0aGF0IGlzIGRpZmZlcmVu dCA4MTgzIGFuZCBtdDgxOTIuDQo+ID4gPiBtdDgxNzMgZGl0aGVyIGVuYWJsZSBpbiBnYW1tYSBp cyBiaXQyDQo+ID4gPiBtdDgxODMgYW5kIG10ODE5MiBkaXRoZXIgZW5naW5lIGVuYWJsZSBpcyBi aXQgMQ0KPiA+ID4NCj4gPiA+DQo+ID4gDQo+ID4gV2UgY2FuIHN0aWxsIGNhbGwgbXRrX2RpdGhl cl9zZXQoKSBmb3IgYnBjIGlzIDUgb3IgNiBoZXJlLCB0aG91Z2ggaXQNCj4gPiB3aWxsIGJlIHNl dCB0byBiaXQyLA0KPiA+IGJ1dCBsYXRlciBpbiBtdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBlbmFi bGUgPyBESVRIRVJfRU5HSU5FX0VOIDoNCj4gPiBESVRIRVJfUkVMQVlfTU9ERSwgJnByaXYtPmNt ZHFfcmVnLCBwcml2LT5yZWdzLCBESVNQX0RJVEhFUl9DRkcpOyBpdA0KPiA+IHdpbGwgYmUgY29y cmVjdCBiYWNrIHRvIGJpdCAxLg0KPiA+IA0KPiA+IElzIHRoaXMgcmVhc29uYWJsZT8NCj4gDQo+ IExvb2tzIHdlaXJkLiBNYXliZSBwYXNzIHNvbWUgaW5mb3JtYXRpb24gaW50byBtdGtfZGl0aGVy X3NldCgpIHRvIHNldA0KPiBESVNQX0RJVEhFUklORyBjb3JyZWN0bHkuIA0KPiANCj4gSSBmaW5k IG9uZSB0aGluZyBuZWVkIHRvIGJlIGZpeGVkLiBDRkcgc2hvdWxkIGJlIGxvd2VyIGNhc2UuDQoN CndlIGNvdWxkIG1vZGlmeSB0aGlzIGxpa2UgdGhpczoNCg0Kdm9pZCBtdGtfZGl0aGVyX3NldChz dHJ1Y3QgbXRrX2RkcF9jb21wICpjb21wLCB1bnNpZ25lZCBpbnQgYnBjLA0KCQkgICAgdW5zaWdu ZWQgaW50IGNmZywgdTMyIGRpdGhlcl9lbmFibGUsIHN0cnVjdCBjbWRxX3BrdCAqY21kcV9wa3Qp DQoNCgkJbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgZGl0aGVyX2VuYWJsZSwgY29tcCwgY2ZnKTsN Cg0KDQoNCj4gDQo+IFJlZ2FyZHMsDQo+IENLDQo+IA0KPiA+IA0KPiA+ID4gPiBSZWdhcmRzLA0K PiA+ID4gPiBDSw0KPiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+IFJlZ2FyZHMsDQo+ID4gPiA+ID4g PiBDSw0KPiA+ID4gPiA+ID4NCj4gPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVRIRVJfUkVHKDE2KSk7DQo+ID4g PiA+ID4gPiA+ICsgICAgICAgfQ0KPiA+ID4gPiA+ID4gPiArDQo+ID4gPiA+ID4gPiA+ICsNCj4g PiA+ID4gPiA+ID4gKyAgICAgICBpZiAoZW5hYmxlKSB7DQo+ID4gPiA+ID4gPiA+ICsgICAgICAg ICAgICAgICB1MzIgaWR4Ow0KPiA+ID4gPiA+ID4gPiArDQo+ID4gPiA+ID4gPiA+ICsgICAgICAg ICAgICAgICBmb3IgKGlkeCA9IDA7IGlkeCA8IEFSUkFZX1NJWkUoZGl0aGVyX3NldHRpbmcpOyBp ZHgrKykNCj4gPiA+ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgbXRrX2RkcF93cml0 ZShjbWRxX3BrdCwgZGl0aGVyX3NldHRpbmdbaWR4XSwgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5y ZWdzLA0KPiA+ID4gPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IERJVEhFUl9SRUcoaWR4ICsgNSkpOw0KPiA+ID4gPiA+ID4gPiArICAgICAgIH0NCj4gPiA+ID4g PiA+ID4gKw0KPiA+ID4gPiA+ID4gPiAgICAgICAgIG10a19kZHBfd3JpdGUoY21kcV9wa3QsIGgg PDwgMTYgfCB3LCAmcHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfRElUSEVSX1NJWkUp Ow0KPiA+ID4gPiA+ID4gPiAtICAgICAgIG10a19kZHBfd3JpdGUoY21kcV9wa3QsIERJVEhFUl9S RUxBWV9NT0RFLCAmcHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfRElUSEVSX0NGRyk7 DQo+ID4gPiA+ID4gPiA+ICsgICAgICAgIG10a19kZHBfd3JpdGUoY21kcV9wa3QsIGVuYWJsZSA/ IERJVEhFUl9FTkdJTkVfRU4gOiBESVRIRVJfUkVMQVlfTU9ERSwgJnByaXYtPmNtZHFfcmVnLCBw cml2LT5yZWdzLCBESVNQX0RJVEhFUl9DRkcpOw0KPiA+ID4gPiA+ID4gPiAgfQ0KPiA+ID4gPiA+ ID4gPg0KPiA+ID4gPiA+ID4gPiAgc3RhdGljIHZvaWQgbXRrX2RpdGhlcl9zdGFydChzdHJ1Y3Qg ZGV2aWNlICpkZXYpDQo+ID4gPiA+ID4gPg0KPiA+ID4gPiA+ID4NCj4gPiA+ID4gPg0KPiA+ID4g PiA+DQo+ID4gPiA+DQo+ID4gPiA+DQo+ID4gPg0KPiANCj4gDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F23A7C433E6 for ; Thu, 28 Jan 2021 19:44:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E4DB64D99 for ; Thu, 28 Jan 2021 19:44:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E4DB64D99 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A9CB6E9F9; Thu, 28 Jan 2021 19:44:36 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by gabe.freedesktop.org (Postfix) with ESMTP id 854A26E930 for ; Thu, 28 Jan 2021 08:32:16 +0000 (UTC) X-UUID: fb5a23f0169b43ddbe1bf112a2d12fc9-20210128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:Reply-To:From:Subject:Message-ID; bh=1Sbm2bZx8k7nPtcDPxuTnvVWvjkL3PfNcHBHr0kDrP4=; b=XgOom+NZuSw6GbO1v+oy48NVP6zKz/qGNZGx9JElnks5YNK7LMOm57zCVGGpM0Hkxvws+VGWjA2XxuxzjEY60hFEZTmZXp2WXh9jM3vv6WgdqO6ct0ZYFrjqmWmdq5I2f4obfazqtTyCbzS/DK5Itf4DrKuh7nXCHwANKWBGrjg=; X-UUID: fb5a23f0169b43ddbe1bf112a2d12fc9-20210128 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1102789290; Thu, 28 Jan 2021 16:32:11 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Jan 2021 16:32:10 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Jan 2021 16:32:09 +0800 Message-ID: <1611822729.1947.14.camel@mhfsdcap03> Subject: Re: [PATCH v11 7/9] drm/mediatek: enable dither function From: Yongqiang Niu To: CK Hu Date: Thu, 28 Jan 2021 16:32:09 +0800 In-Reply-To: <1611822524.23925.4.camel@mtksdaap41> References: <20210128072802.830971-1-hsinyi@chromium.org> <20210128072802.830971-8-hsinyi@chromium.org> <1611819766.16091.4.camel@mtksdaap41> <1611820770.1947.8.camel@mhfsdcap03> <1611821233.18369.4.camel@mtksdaap41> <1611821396.1947.10.camel@mhfsdcap03> <1611822524.23925.4.camel@mtksdaap41> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Thu, 28 Jan 2021 19:44:35 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Yongqiang Niu Cc: Mark Rutland , Devicetree List , David Airlie , lkml , dri-devel , "moderated list:ARM/Mediatek SoC support" , Hsin-Yi Wang , Matthias Brugger , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote: > On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote: > > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu > > wrote: > > > > > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote: > > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote: > > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote: > > > > > > Hi, Hsin-Yi: > > > > > > > > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote: > > > > > > > From: Yongqiang Niu > > > > > > > > > > > > > > for 5 or 6 bpc panel, we need enable dither function > > > > > > > to improve the display quality > > > > > > > > > > > > > > Signed-off-by: Yongqiang Niu > > > > > > > Signed-off-by: Hsin-Yi Wang > > > > > > > --- > > > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- > > > > > > > 1 file changed, 43 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > index 8173f709272be..e85625704d611 100644 > > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > > > > > > > @@ -53,7 +53,9 @@ > > > > > > > #define DITHER_EN BIT(0) > > > > > > > #define DISP_DITHER_CFG 0x0020 > > > > > > > #define DITHER_RELAY_MODE BIT(0) > > > > > > > +#define DITHER_ENGINE_EN BIT(1) > > > > > > > #define DISP_DITHER_SIZE 0x0030 > > > > > > > +#define DITHER_REG(idx) (0x100 + (idx) * 4) > > > > > > > > > > > > > > #define LUT_10BIT_MASK 0x03ff > > > > > > > > > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > > > > > > > { > > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > > > > > > > > > > > > > + bool enable = false; > > > > > > > + > > > > > > > + /* default value for dither reg 5 to 14 */ > > > > > > > + const u32 dither_setting[] = { > > > > > > > + 0x00000000, /* 5 */ > > > > > > > + 0x00003002, /* 6 */ > > > > > > > + 0x00000000, /* 7 */ > > > > > > > + 0x00000000, /* 8 */ > > > > > > > + 0x00000000, /* 9 */ > > > > > > > + 0x00000000, /* 10 */ > > > > > > > + 0x00000000, /* 11 */ > > > > > > > + 0x00000011, /* 12 */ > > > > > > > + 0x00000000, /* 13 */ > > > > > > > + 0x00000000, /* 14 */ > > > > > > > > > > > > Could you explain what is this? > > > > > > > > > > this is dither 5 to dither 14 setting > > > > > this will be useless, we just need set dither 5 and dither 7 like > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); > > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); > > > > > other value is same with hardware default value. > > > > > > > > > > > > > > > > > > > > > > > + }; > > > > > > > + > > > > > > > + if (bpc == 5 || bpc == 6) { > > > > > > > + enable = true; > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_NEW_BIT_MODE, > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(15)); > > > > > > > + mtk_ddp_write(cmdq_pkt, > > > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > > > > > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > > > > > > > > > > > > This result in 0x50505050, but previous version is 0x50504040, so this > > > > > > version is correct and previous version is incorrect? > > > > > > > > > > the new version set r g b 3 channel same, seams more reasonable > > > > > > > > > > > > > > > > > > So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, > > > > DISP_DITHER_16 is identical to mtk_dither_set(), so call > > > > mtk_dither_set() instead of duplication here. > > > > > > > > > > dither enable set in mtk_dither_set is > > > mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); > > > > > > that is different 8183 and mt8192. > > > mt8173 dither enable in gamma is bit2 > > > mt8183 and mt8192 dither engine enable is bit 1 > > > > > > > > > > We can still call mtk_dither_set() for bpc is 5 or 6 here, though it > > will be set to bit2, > > but later in mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : > > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); it > > will be correct back to bit 1. > > > > Is this reasonable? > > Looks weird. Maybe pass some information into mtk_dither_set() to set > DISP_DITHERING correctly. > > I find one thing need to be fixed. CFG should be lower case. we could modify this like this: void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int cfg, u32 dither_enable, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, dither_enable, comp, cfg); > > Regards, > CK > > > > > > > Regards, > > > > CK > > > > > > > > > > > > Regards, > > > > > > CK > > > > > > > > > > > > > + &priv->cmdq_reg, priv->regs, DITHER_REG(16)); > > > > > > > + } > > > > > > > + > > > > > > > + > > > > > > > + if (enable) { > > > > > > > + u32 idx; > > > > > > > + > > > > > > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) > > > > > > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, > > > > > > > + DITHER_REG(idx + 5)); > > > > > > > + } > > > > > > > + > > > > > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > > > > > > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > > > > > > > } > > > > > > > > > > > > > > static void mtk_dither_start(struct device *dev) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel