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Mon, 01 Feb 2021 21:44:27 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Feb 2021 21:44:25 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 13:44:18 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 13:44:18 +0800 Message-ID: <1612244658.5495.2.camel@mtksdaap41> Subject: Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 13:44:18 +0800 In-Reply-To: <20210201103727.376721-5-hsinyi@chromium.org> References: <20210201103727.376721-1-hsinyi@chromium.org> <20210201103727.376721-5-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3B4EDF650D9376DA38E614DC23D5CDAC244606E571EB1A9E0DF85DFCA0AA314D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_004429_258989_84F0F84D X-CRM114-Status: GOOD ( 29.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Hsin-Yi: On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > ccorr ctm matrix bits will be different in mt8192 Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index 13a0eafabf9c0..f119bef6d6e66 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_postmask.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index 06d4d4e1c0d05..469d4e12b2003 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index d884807809635..4a8015d247ec7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -234,82 +220,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -348,8 +258,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -610,6 +520,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DISP_POSTMASK || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index d99afc8528684..3da8996438dbc 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -635,6 +636,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 7e7b28e32aa2f..b49062364c3d2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D70AC43381 for ; Tue, 2 Feb 2021 05:45:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 080AB64EE2 for ; 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Mon, 01 Feb 2021 21:44:27 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 1 Feb 2021 21:44:25 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 13:44:18 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 13:44:18 +0800 Message-ID: <1612244658.5495.2.camel@mtksdaap41> Subject: Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 13:44:18 +0800 In-Reply-To: <20210201103727.376721-5-hsinyi@chromium.org> References: <20210201103727.376721-1-hsinyi@chromium.org> <20210201103727.376721-5-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3B4EDF650D9376DA38E614DC23D5CDAC244606E571EB1A9E0DF85DFCA0AA314D2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_004429_258989_84F0F84D X-CRM114-Status: GOOD ( 29.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Hsin-Yi: On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > ccorr ctm matrix bits will be different in mt8192 Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index 13a0eafabf9c0..f119bef6d6e66 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_postmask.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index 06d4d4e1c0d05..469d4e12b2003 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index d884807809635..4a8015d247ec7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -234,82 +220,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -348,8 +258,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -610,6 +520,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DISP_POSTMASK || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index d99afc8528684..3da8996438dbc 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -635,6 +636,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 7e7b28e32aa2f..b49062364c3d2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DFFBC433DB for ; Tue, 2 Feb 2021 05:45:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DEE364EDF for ; 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(mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1763200846; Tue, 02 Feb 2021 13:44:24 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 13:44:18 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 13:44:18 +0800 Message-ID: <1612244658.5495.2.camel@mtksdaap41> Subject: Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module From: CK Hu To: Hsin-Yi Wang CC: Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Date: Tue, 2 Feb 2021 13:44:18 +0800 In-Reply-To: <20210201103727.376721-5-hsinyi@chromium.org> References: <20210201103727.376721-1-hsinyi@chromium.org> <20210201103727.376721-5-hsinyi@chromium.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3B4EDF650D9376DA38E614DC23D5CDAC244606E571EB1A9E0DF85DFCA0AA314D2000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SGksIEhzaW4tWWk6DQoNCk9uIE1vbiwgMjAyMS0wMi0wMSBhdCAxODozNyArMDgwMCwgSHNpbi1Z aSBXYW5nIHdyb3RlOg0KPiBGcm9tOiBZb25ncWlhbmcgTml1IDx5b25ncWlhbmcubml1QG1lZGlh dGVrLmNvbT4NCj4gDQo+IGNjb3JyIGN0bSBtYXRyaXggYml0cyB3aWxsIGJlIGRpZmZlcmVudCBp biBtdDgxOTINCg0KUmV2aWV3ZWQtYnk6IENLIEh1IDxjay5odUBtZWRpYXRlay5jb20+DQoNCj4g DQo+IFNpZ25lZC1vZmYtYnk6IFlvbmdxaWFuZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsu Y29tPg0KPiBTaWduZWQtb2ZmLWJ5OiBIc2luLVlpIFdhbmcgPGhzaW55aUBjaHJvbWl1bS5vcmc+ DQo+IC0tLQ0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL01ha2VmaWxlICAgICAgICAgICB8 ICAgMyArLQ0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kaXNwX2Njb3JyLmMgICB8 IDIxNiArKysrKysrKysrKysrKysrKysrKw0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kaXNwX2Rydi5oICAgICB8ICAgOSArDQo+ICBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRr X2RybV9kZHBfY29tcC5jIHwgIDk1ICstLS0tLS0tLQ0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlh dGVrL210a19kcm1fZHJ2LmMgICAgICB8ICAgOCArLQ0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlh dGVrL210a19kcm1fZHJ2LmggICAgICB8ICAgMSArDQo+ICA2IGZpbGVzIGNoYW5nZWQsIDIzNiBp bnNlcnRpb25zKCspLCA5NiBkZWxldGlvbnMoLSkNCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2 ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Rpc3BfY2NvcnIuYw0KPiANCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9NYWtlZmlsZSBiL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9NYWtlZmlsZQ0KPiBpbmRleCAxM2EwZWFmYWJmOWMwLi5mMTE5YmVmNmQ2ZTY2IDEwMDY0 NA0KPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvTWFrZWZpbGUNCj4gKysrIGIvZHJp dmVycy9ncHUvZHJtL21lZGlhdGVrL01ha2VmaWxlDQo+IEBAIC0xLDYgKzEsNyBAQA0KPiAgIyBT UERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMA0KPiAgDQo+IC1tZWRpYXRlay1kcm0teSA6 PSBtdGtfZGlzcF9jb2xvci5vIFwNCj4gK21lZGlhdGVrLWRybS15IDo9IG10a19kaXNwX2Njb3Jy Lm8gXA0KPiArCQkgIG10a19kaXNwX2NvbG9yLm8gXA0KPiAgCQkgIG10a19kaXNwX2dhbW1hLm8g XA0KPiAgCQkgIG10a19kaXNwX292bC5vIFwNCj4gIAkJICBtdGtfZGlzcF9wb3N0bWFzay5vIFwN Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9jY29yci5j IGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kaXNwX2Njb3JyLmMNCj4gbmV3IGZpbGUg bW9kZSAxMDA2NDQNCj4gaW5kZXggMDAwMDAwMDAwMDAwMC4uNmVlMjQzMWU2Yjg0Mw0KPiAtLS0g L2Rldi9udWxsDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9jY29y ci5jDQo+IEBAIC0wLDAgKzEsMjE2IEBADQo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjog R1BMLTIuMC1vbmx5DQo+ICsvKg0KPiArICogQ29weXJpZ2h0IChjKSAyMDIxIE1lZGlhVGVrIElu Yy4NCj4gKyAqLw0KPiArDQo+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+DQo+ICsjaW5jbHVkZSA8 bGludXgvY29tcG9uZW50Lmg+DQo+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+DQo+ICsjaW5j bHVkZSA8bGludXgvb2ZfZGV2aWNlLmg+DQo+ICsjaW5jbHVkZSA8bGludXgvb2ZfaXJxLmg+DQo+ ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+DQo+ICsjaW5jbHVkZSA8bGludXgv c29jL21lZGlhdGVrL210ay1jbWRxLmg+DQo+ICsNCj4gKyNpbmNsdWRlICJtdGtfZGlzcF9kcnYu aCINCj4gKyNpbmNsdWRlICJtdGtfZHJtX2NydGMuaCINCj4gKyNpbmNsdWRlICJtdGtfZHJtX2Rk cF9jb21wLmgiDQo+ICsNCj4gKyNkZWZpbmUgRElTUF9DQ09SUl9FTgkJCQkweDAwMDANCj4gKyNk ZWZpbmUgQ0NPUlJfRU4JCQkJCUJJVCgwKQ0KPiArI2RlZmluZSBESVNQX0NDT1JSX0NGRwkJCQkw eDAwMjANCj4gKyNkZWZpbmUgQ0NPUlJfUkVMQVlfTU9ERQkJCQlCSVQoMCkNCj4gKyNkZWZpbmUg Q0NPUlJfRU5HSU5FX0VOCQkJCQlCSVQoMSkNCj4gKyNkZWZpbmUgQ0NPUlJfR0FNTUFfT0ZGCQkJ CQlCSVQoMikNCj4gKyNkZWZpbmUgQ0NPUlJfV0dBTVVUX1NSQ19DTElQCQkJCUJJVCgzKQ0KPiAr I2RlZmluZSBESVNQX0NDT1JSX1NJWkUJCQkJMHgwMDMwDQo+ICsjZGVmaW5lIERJU1BfQ0NPUlJf Q09FRl8wCQkJMHgwMDgwDQo+ICsjZGVmaW5lIERJU1BfQ0NPUlJfQ09FRl8xCQkJMHgwMDg0DQo+ ICsjZGVmaW5lIERJU1BfQ0NPUlJfQ09FRl8yCQkJMHgwMDg4DQo+ICsjZGVmaW5lIERJU1BfQ0NP UlJfQ09FRl8zCQkJMHgwMDhDDQo+ICsjZGVmaW5lIERJU1BfQ0NPUlJfQ09FRl80CQkJMHgwMDkw DQo+ICsNCj4gK3N0cnVjdCBtdGtfZGlzcF9jY29ycl9kYXRhIHsNCj4gKwl1MzIgcmVzZXJ2ZWQ7 DQo+ICt9Ow0KPiArDQo+ICsvKioNCj4gKyAqIHN0cnVjdCBtdGtfZGlzcF9jY29yciAtIERJU1Bf Q0NPUlIgZHJpdmVyIHN0cnVjdHVyZQ0KPiArICogQGRkcF9jb21wIC0gc3RydWN0dXJlIGNvbnRh aW5pbmcgdHlwZSBlbnVtIGFuZCBoYXJkd2FyZSByZXNvdXJjZXMNCj4gKyAqIEBjcnRjIC0gYXNz b2NpYXRlZCBjcnRjIHRvIHJlcG9ydCBpcnEgZXZlbnRzIHRvDQo+ICsgKi8NCj4gK3N0cnVjdCBt dGtfZGlzcF9jY29yciB7DQo+ICsJc3RydWN0IGNsayAqY2xrOw0KPiArCXZvaWQgX19pb21lbSAq cmVnczsNCj4gKwlzdHJ1Y3QgY21kcV9jbGllbnRfcmVnIGNtZHFfcmVnOw0KPiArCWNvbnN0IHN0 cnVjdCBtdGtfZGlzcF9jY29ycl9kYXRhCSpkYXRhOw0KPiArfTsNCj4gKw0KPiAraW50IG10a19j Y29ycl9jbGtfZW5hYmxlKHN0cnVjdCBkZXZpY2UgKmRldikNCj4gK3sNCj4gKwlzdHJ1Y3QgbXRr X2Rpc3BfY2NvcnIgKmNjb3JyID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+ICsNCj4gKwlyZXR1 cm4gY2xrX3ByZXBhcmVfZW5hYmxlKGNjb3JyLT5jbGspOw0KPiArfQ0KPiArDQo+ICt2b2lkIG10 a19jY29ycl9jbGtfZGlzYWJsZShzdHJ1Y3QgZGV2aWNlICpkZXYpDQo+ICt7DQo+ICsJc3RydWN0 IG10a19kaXNwX2Njb3JyICpjY29yciA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiArDQo+ICsJ Y2xrX2Rpc2FibGVfdW5wcmVwYXJlKGNjb3JyLT5jbGspOw0KPiArfQ0KPiArDQo+ICt2b2lkIG10 a19jY29ycl9jb25maWcoc3RydWN0IGRldmljZSAqZGV2LCB1bnNpZ25lZCBpbnQgdywNCj4gKwkJ CSAgICAgdW5zaWduZWQgaW50IGgsIHVuc2lnbmVkIGludCB2cmVmcmVzaCwNCj4gKwkJCSAgICAg dW5zaWduZWQgaW50IGJwYywgc3RydWN0IGNtZHFfcGt0ICpjbWRxX3BrdCkNCj4gK3sNCj4gKwlz dHJ1Y3QgbXRrX2Rpc3BfY2NvcnIgKmNjb3JyID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+ICsN Cj4gKwltdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBoIDw8IDE2IHwgdywgJmNjb3JyLT5jbWRxX3Jl ZywgY2NvcnItPnJlZ3MsDQo+ICsJCSAgICAgIERJU1BfQ0NPUlJfU0laRSk7DQo+ICsJbXRrX2Rk cF93cml0ZShjbWRxX3BrdCwgQ0NPUlJfRU5HSU5FX0VOLCAmY2NvcnItPmNtZHFfcmVnLCBjY29y ci0+cmVncywNCj4gKwkJICAgICAgRElTUF9DQ09SUl9DRkcpOw0KPiArfQ0KPiArDQo+ICt2b2lk IG10a19jY29ycl9zdGFydChzdHJ1Y3QgZGV2aWNlICpkZXYpDQo+ICt7DQo+ICsJc3RydWN0IG10 a19kaXNwX2Njb3JyICpjY29yciA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiArDQo+ICsJd3Jp dGVsKENDT1JSX0VOLCBjY29yci0+cmVncyArIERJU1BfQ0NPUlJfRU4pOw0KPiArfQ0KPiArDQo+ ICt2b2lkIG10a19jY29ycl9zdG9wKHN0cnVjdCBkZXZpY2UgKmRldikNCj4gK3sNCj4gKwlzdHJ1 Y3QgbXRrX2Rpc3BfY2NvcnIgKmNjb3JyID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+ICsNCj4g Kwl3cml0ZWxfcmVsYXhlZCgweDAsIGNjb3JyLT5yZWdzICsgRElTUF9DQ09SUl9FTik7DQo+ICt9 DQo+ICsNCj4gKy8qIENvbnZlcnRzIGEgRFJNIFMzMS4zMiB2YWx1ZSB0byB0aGUgSFcgUzEuMTAg Zm9ybWF0LiAqLw0KPiArc3RhdGljIHUxNiBtdGtfY3RtX3MzMV8zMl90b19zMV8xMCh1NjQgaW4p DQo+ICt7DQo+ICsJdTE2IHI7DQo+ICsNCj4gKwkvKiBTaWduIGJpdC4gKi8NCj4gKwlyID0gaW4g JiBCSVRfVUxMKDYzKSA/IEJJVCgxMSkgOiAwOw0KPiArDQo+ICsJaWYgKChpbiAmIEdFTk1BU0tf VUxMKDYyLCAzMykpID4gMCkgew0KPiArCQkvKiBpZGVudGl0eSB2YWx1ZSAweDEwMDAwMDAwMCAt PiAweDQwMCwgKi8NCj4gKwkJLyogaWYgYmlnZ2VyIHRoaXMsIHNldCBpdCB0byBtYXggMHg3ZmYu ICovDQo+ICsJCXIgfD0gR0VOTUFTSygxMCwgMCk7DQo+ICsJfSBlbHNlIHsNCj4gKwkJLyogdGFr ZSB0aGUgMTEgbW9zdCBpbXBvcnRhbnQgYml0cy4gKi8NCj4gKwkJciB8PSAoaW4gPj4gMjIpICYg R0VOTUFTSygxMCwgMCk7DQo+ICsJfQ0KPiArDQo+ICsJcmV0dXJuIHI7DQo+ICt9DQo+ICsNCj4g K3ZvaWQgbXRrX2Njb3JyX2N0bV9zZXQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZHJtX2Ny dGNfc3RhdGUgKnN0YXRlKQ0KPiArew0KPiArCXN0cnVjdCBtdGtfZGlzcF9jY29yciAqY2NvcnIg PSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gKwlzdHJ1Y3QgZHJtX3Byb3BlcnR5X2Jsb2IgKmJs b2IgPSBzdGF0ZS0+Y3RtOw0KPiArCXN0cnVjdCBkcm1fY29sb3JfY3RtICpjdG07DQo+ICsJY29u c3QgdTY0ICppbnB1dDsNCj4gKwl1aW50MTZfdCBjb2VmZnNbOV0gPSB7IDAgfTsNCj4gKwlpbnQg aTsNCj4gKwlzdHJ1Y3QgY21kcV9wa3QgKmNtZHFfcGt0ID0gTlVMTDsNCj4gKw0KPiArCWlmICgh YmxvYikNCj4gKwkJcmV0dXJuOw0KPiArDQo+ICsJY3RtID0gKHN0cnVjdCBkcm1fY29sb3JfY3Rt ICopYmxvYi0+ZGF0YTsNCj4gKwlpbnB1dCA9IGN0bS0+bWF0cml4Ow0KPiArDQo+ICsJZm9yIChp ID0gMDsgaSA8IEFSUkFZX1NJWkUoY29lZmZzKTsgaSsrKQ0KPiArCQljb2VmZnNbaV0gPSBtdGtf Y3RtX3MzMV8zMl90b19zMV8xMChpbnB1dFtpXSk7DQo+ICsNCj4gKwltdGtfZGRwX3dyaXRlKGNt ZHFfcGt0LCBjb2VmZnNbMF0gPDwgMTYgfCBjb2VmZnNbMV0sDQo+ICsJCSAgICAgICZjY29yci0+ Y21kcV9yZWcsIGNjb3JyLT5yZWdzLCBESVNQX0NDT1JSX0NPRUZfMCk7DQo+ICsJbXRrX2RkcF93 cml0ZShjbWRxX3BrdCwgY29lZmZzWzJdIDw8IDE2IHwgY29lZmZzWzNdLA0KPiArCQkgICAgICAm Y2NvcnItPmNtZHFfcmVnLCBjY29yci0+cmVncywgRElTUF9DQ09SUl9DT0VGXzEpOw0KPiArCW10 a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s0XSA8PCAxNiB8IGNvZWZmc1s1XSwNCj4gKwkJ ICAgICAgJmNjb3JyLT5jbWRxX3JlZywgY2NvcnItPnJlZ3MsIERJU1BfQ0NPUlJfQ09FRl8yKTsN Cj4gKwltdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBjb2VmZnNbNl0gPDwgMTYgfCBjb2VmZnNbN10s DQo+ICsJCSAgICAgICZjY29yci0+Y21kcV9yZWcsIGNjb3JyLT5yZWdzLCBESVNQX0NDT1JSX0NP RUZfMyk7DQo+ICsJbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgY29lZmZzWzhdIDw8IDE2LA0KPiAr CQkgICAgICAmY2NvcnItPmNtZHFfcmVnLCBjY29yci0+cmVncywgRElTUF9DQ09SUl9DT0VGXzQp Ow0KPiArfQ0KPiArDQo+ICtzdGF0aWMgaW50IG10a19kaXNwX2Njb3JyX2JpbmQoc3RydWN0IGRl dmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsDQo+ICsJCQkgICAgICAgdm9pZCAqZGF0 YSkNCj4gK3sNCj4gKwlyZXR1cm4gMDsNCj4gK30NCj4gKw0KPiArc3RhdGljIHZvaWQgbXRrX2Rp c3BfY2NvcnJfdW5iaW5kKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGRldmljZSAqbWFzdGVy LA0KPiArCQkJCSAgdm9pZCAqZGF0YSkNCj4gK3sNCj4gK30NCj4gKw0KPiArc3RhdGljIGNvbnN0 IHN0cnVjdCBjb21wb25lbnRfb3BzIG10a19kaXNwX2Njb3JyX2NvbXBvbmVudF9vcHMgPSB7DQo+ ICsJLmJpbmQJPSBtdGtfZGlzcF9jY29ycl9iaW5kLA0KPiArCS51bmJpbmQJPSBtdGtfZGlzcF9j Y29ycl91bmJpbmQsDQo+ICt9Ow0KPiArDQo+ICtzdGF0aWMgaW50IG10a19kaXNwX2Njb3JyX3By b2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpDQo+ICt7DQo+ICsJc3RydWN0IGRldmlj ZSAqZGV2ID0gJnBkZXYtPmRldjsNCj4gKwlzdHJ1Y3QgbXRrX2Rpc3BfY2NvcnIgKnByaXY7DQo+ ICsJc3RydWN0IHJlc291cmNlICpyZXM7DQo+ICsJaW50IHJldDsNCj4gKw0KPiArCXByaXYgPSBk ZXZtX2t6YWxsb2MoZGV2LCBzaXplb2YoKnByaXYpLCBHRlBfS0VSTkVMKTsNCj4gKwlpZiAoIXBy aXYpDQo+ICsJCXJldHVybiAtRU5PTUVNOw0KPiArDQo+ICsJcHJpdi0+Y2xrID0gZGV2bV9jbGtf Z2V0KGRldiwgTlVMTCk7DQo+ICsJaWYgKElTX0VSUihwcml2LT5jbGspKSB7DQo+ICsJCWRldl9l cnIoZGV2LCAiZmFpbGVkIHRvIGdldCBjY29yciBjbGtcbiIpOw0KPiArCQlyZXR1cm4gUFRSX0VS Uihwcml2LT5jbGspOw0KPiArCX0NCj4gKw0KPiArCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJj ZShwZGV2LCBJT1JFU09VUkNFX01FTSwgMCk7DQo+ICsJcHJpdi0+cmVncyA9IGRldm1faW9yZW1h cF9yZXNvdXJjZShkZXYsIHJlcyk7DQo+ICsJaWYgKElTX0VSUihwcml2LT5yZWdzKSkgew0KPiAr CQlkZXZfZXJyKGRldiwgImZhaWxlZCB0byBpb3JlbWFwIGNjb3JyXG4iKTsNCj4gKwkJcmV0dXJu IFBUUl9FUlIocHJpdi0+cmVncyk7DQo+ICsJfQ0KPiArDQo+ICsjaWYgSVNfUkVBQ0hBQkxFKENP TkZJR19NVEtfQ01EUSkNCj4gKwlyZXQgPSBjbWRxX2Rldl9nZXRfY2xpZW50X3JlZyhkZXYsICZw cml2LT5jbWRxX3JlZywgMCk7DQo+ICsJaWYgKHJldCkNCj4gKwkJZGV2X2RiZyhkZXYsICJnZXQg bWVkaWF0ZWssZ2NlLWNsaWVudC1yZWcgZmFpbCFcbiIpOw0KPiArI2VuZGlmDQo+ICsNCj4gKwlw cml2LT5kYXRhID0gb2ZfZGV2aWNlX2dldF9tYXRjaF9kYXRhKGRldik7DQo+ICsJcGxhdGZvcm1f c2V0X2RydmRhdGEocGRldiwgcHJpdik7DQo+ICsNCj4gKwlyZXQgPSBjb21wb25lbnRfYWRkKGRl diwgJm10a19kaXNwX2Njb3JyX2NvbXBvbmVudF9vcHMpOw0KPiArCWlmIChyZXQpDQo+ICsJCWRl dl9lcnIoZGV2LCAiRmFpbGVkIHRvIGFkZCBjb21wb25lbnQ6ICVkXG4iLCByZXQpOw0KPiArDQo+ ICsJcmV0dXJuIHJldDsNCj4gK30NCj4gKw0KPiArc3RhdGljIGludCBtdGtfZGlzcF9jY29ycl9y ZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gK3sNCj4gKwljb21wb25lbnRf ZGVsKCZwZGV2LT5kZXYsICZtdGtfZGlzcF9jY29ycl9jb21wb25lbnRfb3BzKTsNCj4gKw0KPiAr CXJldHVybiAwOw0KPiArfQ0KPiArDQo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9p ZCBtdGtfZGlzcF9jY29ycl9kcml2ZXJfZHRfbWF0Y2hbXSA9IHsNCj4gKwl7IC5jb21wYXRpYmxl ID0gIm1lZGlhdGVrLG10ODE4My1kaXNwLWNjb3JyIn0sDQo+ICsJe30sDQo+ICt9Ow0KPiArTU9E VUxFX0RFVklDRV9UQUJMRShvZiwgbXRrX2Rpc3BfY2NvcnJfZHJpdmVyX2R0X21hdGNoKTsNCj4g Kw0KPiArc3RydWN0IHBsYXRmb3JtX2RyaXZlciBtdGtfZGlzcF9jY29ycl9kcml2ZXIgPSB7DQo+ ICsJLnByb2JlCQk9IG10a19kaXNwX2Njb3JyX3Byb2JlLA0KPiArCS5yZW1vdmUJCT0gbXRrX2Rp c3BfY2NvcnJfcmVtb3ZlLA0KPiArCS5kcml2ZXIJCT0gew0KPiArCQkubmFtZQk9ICJtZWRpYXRl ay1kaXNwLWNjb3JyIiwNCj4gKwkJLm93bmVyCT0gVEhJU19NT0RVTEUsDQo+ICsJCS5vZl9tYXRj aF90YWJsZSA9IG10a19kaXNwX2Njb3JyX2RyaXZlcl9kdF9tYXRjaCwNCj4gKwl9LA0KPiArfTsN Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9kcnYuaCBi L2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZGlzcF9kcnYuaA0KPiBpbmRleCAwNmQ0ZDRl MWMwZDA1Li40NjlkNGUxMmIyMDAzIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2Rpc3BfZHJ2LmgNCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210 a19kaXNwX2Rydi5oDQo+IEBAIC05LDYgKzksMTUgQEANCj4gICNpbmNsdWRlIDxsaW51eC9zb2Mv bWVkaWF0ZWsvbXRrLWNtZHEuaD4NCj4gICNpbmNsdWRlICJtdGtfZHJtX3BsYW5lLmgiDQo+ICAN Cj4gK3ZvaWQgbXRrX2Njb3JyX2N0bV9zZXQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZHJt X2NydGNfc3RhdGUgKnN0YXRlKTsNCj4gK2ludCBtdGtfY2NvcnJfY2xrX2VuYWJsZShzdHJ1Y3Qg ZGV2aWNlICpkZXYpOw0KPiArdm9pZCBtdGtfY2NvcnJfY2xrX2Rpc2FibGUoc3RydWN0IGRldmlj ZSAqZGV2KTsNCj4gK3ZvaWQgbXRrX2Njb3JyX2NvbmZpZyhzdHJ1Y3QgZGV2aWNlICpkZXYsIHVu c2lnbmVkIGludCB3LA0KPiArCQkgICAgICB1bnNpZ25lZCBpbnQgaCwgdW5zaWduZWQgaW50IHZy ZWZyZXNoLA0KPiArCQkgICAgICB1bnNpZ25lZCBpbnQgYnBjLCBzdHJ1Y3QgY21kcV9wa3QgKmNt ZHFfcGt0KTsNCj4gK3ZvaWQgbXRrX2Njb3JyX3N0YXJ0KHN0cnVjdCBkZXZpY2UgKmRldik7DQo+ ICt2b2lkIG10a19jY29ycl9zdG9wKHN0cnVjdCBkZXZpY2UgKmRldik7DQo+ICsNCj4gIHZvaWQg bXRrX2NvbG9yX2J5cGFzc19zaGFkb3coc3RydWN0IGRldmljZSAqZGV2KTsNCj4gIGludCBtdGtf Y29sb3JfY2xrX2VuYWJsZShzdHJ1Y3QgZGV2aWNlICpkZXYpOw0KPiAgdm9pZCBtdGtfY29sb3Jf Y2xrX2Rpc2FibGUoc3RydWN0IGRldmljZSAqZGV2KTsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVk aWF0ZWsvbXRrX2RybV9kZHBfY29tcC5jDQo+IGluZGV4IGQ4ODQ4MDc4MDk2MzUuLjRhODAxNWQy NDdlYzcgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rk cF9jb21wLmMNCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2Nv bXAuYw0KPiBAQCAtMzUsMjAgKzM1LDYgQEANCj4gICNkZWZpbmUgRElTUF9BQUxfRU4JCQkJMHgw MDAwDQo+ICAjZGVmaW5lIERJU1BfQUFMX1NJWkUJCQkJMHgwMDMwDQo+ICANCj4gLSNkZWZpbmUg RElTUF9DQ09SUl9FTgkJCQkweDAwMDANCj4gLSNkZWZpbmUgQ0NPUlJfRU4JCQkJQklUKDApDQo+ IC0jZGVmaW5lIERJU1BfQ0NPUlJfQ0ZHCQkJCTB4MDAyMA0KPiAtI2RlZmluZSBDQ09SUl9SRUxB WV9NT0RFCQkJQklUKDApDQo+IC0jZGVmaW5lIENDT1JSX0VOR0lORV9FTgkJCQlCSVQoMSkNCj4g LSNkZWZpbmUgQ0NPUlJfR0FNTUFfT0ZGCQkJCUJJVCgyKQ0KPiAtI2RlZmluZSBDQ09SUl9XR0FN VVRfU1JDX0NMSVAJCQlCSVQoMykNCj4gLSNkZWZpbmUgRElTUF9DQ09SUl9TSVpFCQkJCTB4MDAz MA0KPiAtI2RlZmluZSBESVNQX0NDT1JSX0NPRUZfMAkJCTB4MDA4MA0KPiAtI2RlZmluZSBESVNQ X0NDT1JSX0NPRUZfMQkJCTB4MDA4NA0KPiAtI2RlZmluZSBESVNQX0NDT1JSX0NPRUZfMgkJCTB4 MDA4OA0KPiAtI2RlZmluZSBESVNQX0NDT1JSX0NPRUZfMwkJCTB4MDA4Qw0KPiAtI2RlZmluZSBE SVNQX0NDT1JSX0NPRUZfNAkJCTB4MDA5MA0KPiAtDQo+ICAjZGVmaW5lIERJU1BfRElUSEVSX0VO CQkJCTB4MDAwMA0KPiAgI2RlZmluZSBESVRIRVJfRU4JCQkJQklUKDApDQo+ICAjZGVmaW5lIERJ U1BfRElUSEVSX0NGRwkJCQkweDAwMjANCj4gQEAgLTIzNCw4MiArMjIwLDYgQEAgc3RhdGljIHZv aWQgbXRrX2FhbF9zdG9wKHN0cnVjdCBkZXZpY2UgKmRldikNCj4gIAl3cml0ZWxfcmVsYXhlZCgw eDAsIHByaXYtPnJlZ3MgKyBESVNQX0FBTF9FTik7DQo+ICB9DQo+ICANCj4gLXN0YXRpYyB2b2lk IG10a19jY29ycl9jb25maWcoc3RydWN0IGRldmljZSAqZGV2LCB1bnNpZ25lZCBpbnQgdywNCj4g LQkJCSAgICAgdW5zaWduZWQgaW50IGgsIHVuc2lnbmVkIGludCB2cmVmcmVzaCwNCj4gLQkJCSAg ICAgdW5zaWduZWQgaW50IGJwYywgc3RydWN0IGNtZHFfcGt0ICpjbWRxX3BrdCkNCj4gLXsNCj4g LQlzdHJ1Y3QgbXRrX2RkcF9jb21wX2RldiAqcHJpdiA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0K PiAtDQo+IC0JbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgaCA8PCAxNiB8IHcsICZwcml2LT5jbWRx X3JlZywgcHJpdi0+cmVncywgRElTUF9DQ09SUl9TSVpFKTsNCj4gLQltdGtfZGRwX3dyaXRlKGNt ZHFfcGt0LCBDQ09SUl9FTkdJTkVfRU4sICZwcml2LT5jbWRxX3JlZywgcHJpdi0+cmVncywgRElT UF9DQ09SUl9DRkcpOw0KPiAtfQ0KPiAtDQo+IC1zdGF0aWMgdm9pZCBtdGtfY2NvcnJfc3RhcnQo c3RydWN0IGRldmljZSAqZGV2KQ0KPiAtew0KPiAtCXN0cnVjdCBtdGtfZGRwX2NvbXBfZGV2ICpw cml2ID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+IC0NCj4gLQl3cml0ZWwoQ0NPUlJfRU4sIHBy aXYtPnJlZ3MgKyBESVNQX0NDT1JSX0VOKTsNCj4gLX0NCj4gLQ0KPiAtc3RhdGljIHZvaWQgbXRr X2Njb3JyX3N0b3Aoc3RydWN0IGRldmljZSAqZGV2KQ0KPiAtew0KPiAtCXN0cnVjdCBtdGtfZGRw X2NvbXBfZGV2ICpwcml2ID0gZGV2X2dldF9kcnZkYXRhKGRldik7DQo+IC0NCj4gLQl3cml0ZWxf cmVsYXhlZCgweDAsIHByaXYtPnJlZ3MgKyBESVNQX0NDT1JSX0VOKTsNCj4gLX0NCj4gLQ0KPiAt LyogQ29udmVydHMgYSBEUk0gUzMxLjMyIHZhbHVlIHRvIHRoZSBIVyBTMS4xMCBmb3JtYXQuICov DQo+IC1zdGF0aWMgdTE2IG10a19jdG1fczMxXzMyX3RvX3MxXzEwKHU2NCBpbikNCj4gLXsNCj4g LQl1MTYgcjsNCj4gLQ0KPiAtCS8qIFNpZ24gYml0LiAqLw0KPiAtCXIgPSBpbiAmIEJJVF9VTEwo NjMpID8gQklUKDExKSA6IDA7DQo+IC0NCj4gLQlpZiAoKGluICYgR0VOTUFTS19VTEwoNjIsIDMz KSkgPiAwKSB7DQo+IC0JCS8qIGlkZW50aXR5IHZhbHVlIDB4MTAwMDAwMDAwIC0+IDB4NDAwLCAq Lw0KPiAtCQkvKiBpZiBiaWdnZXIgdGhpcywgc2V0IGl0IHRvIG1heCAweDdmZi4gKi8NCj4gLQkJ ciB8PSBHRU5NQVNLKDEwLCAwKTsNCj4gLQl9IGVsc2Ugew0KPiAtCQkvKiB0YWtlIHRoZSAxMSBt b3N0IGltcG9ydGFudCBiaXRzLiAqLw0KPiAtCQlyIHw9IChpbiA+PiAyMikgJiBHRU5NQVNLKDEw LCAwKTsNCj4gLQl9DQo+IC0NCj4gLQlyZXR1cm4gcjsNCj4gLX0NCj4gLQ0KPiAtc3RhdGljIHZv aWQgbXRrX2Njb3JyX2N0bV9zZXQoc3RydWN0IGRldmljZSAqZGV2LA0KPiAtCQkJICAgICAgc3Ry dWN0IGRybV9jcnRjX3N0YXRlICpzdGF0ZSkNCj4gLXsNCj4gLQlzdHJ1Y3QgbXRrX2RkcF9jb21w X2RldiAqcHJpdiA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiAtCXN0cnVjdCBkcm1fcHJvcGVy dHlfYmxvYiAqYmxvYiA9IHN0YXRlLT5jdG07DQo+IC0Jc3RydWN0IGRybV9jb2xvcl9jdG0gKmN0 bTsNCj4gLQljb25zdCB1NjQgKmlucHV0Ow0KPiAtCXVpbnQxNl90IGNvZWZmc1s5XSA9IHsgMCB9 Ow0KPiAtCWludCBpOw0KPiAtCXN0cnVjdCBjbWRxX3BrdCAqY21kcV9wa3QgPSBOVUxMOw0KPiAt DQo+IC0JaWYgKCFibG9iKQ0KPiAtCQlyZXR1cm47DQo+IC0NCj4gLQljdG0gPSAoc3RydWN0IGRy bV9jb2xvcl9jdG0gKilibG9iLT5kYXRhOw0KPiAtCWlucHV0ID0gY3RtLT5tYXRyaXg7DQo+IC0N Cj4gLQlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0laRShjb2VmZnMpOyBpKyspDQo+IC0JCWNvZWZm c1tpXSA9IG10a19jdG1fczMxXzMyX3RvX3MxXzEwKGlucHV0W2ldKTsNCj4gLQ0KPiAtCW10a19k ZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1swXSA8PCAxNiB8IGNvZWZmc1sxXSwNCj4gLQkJICAg ICAgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVNQX0NDT1JSX0NPRUZfMCk7DQo+IC0J bXRrX2RkcF93cml0ZShjbWRxX3BrdCwgY29lZmZzWzJdIDw8IDE2IHwgY29lZmZzWzNdLA0KPiAt CQkgICAgICAmcHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfQ0NPUlJfQ09FRl8xKTsN Cj4gLQltdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCBjb2VmZnNbNF0gPDwgMTYgfCBjb2VmZnNbNV0s DQo+IC0JCSAgICAgICZwcml2LT5jbWRxX3JlZywgcHJpdi0+cmVncywgRElTUF9DQ09SUl9DT0VG XzIpOw0KPiAtCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIGNvZWZmc1s2XSA8PCAxNiB8IGNvZWZm c1s3XSwNCj4gLQkJICAgICAgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLCBESVNQX0NDT1JS X0NPRUZfMyk7DQo+IC0JbXRrX2RkcF93cml0ZShjbWRxX3BrdCwgY29lZmZzWzhdIDw8IDE2LA0K PiAtCQkgICAgICAmcHJpdi0+Y21kcV9yZWcsIHByaXYtPnJlZ3MsIERJU1BfQ0NPUlJfQ09FRl80 KTsNCj4gLX0NCj4gLQ0KPiAgc3RhdGljIHZvaWQgbXRrX2RpdGhlcl9jb25maWcoc3RydWN0IGRl dmljZSAqZGV2LCB1bnNpZ25lZCBpbnQgdywNCj4gIAkJCSAgICAgIHVuc2lnbmVkIGludCBoLCB1 bnNpZ25lZCBpbnQgdnJlZnJlc2gsDQo+ICAJCQkgICAgICB1bnNpZ25lZCBpbnQgYnBjLCBzdHJ1 Y3QgY21kcV9wa3QgKmNtZHFfcGt0KQ0KPiBAQCAtMzQ4LDggKzI1OCw4IEBAIHN0YXRpYyBjb25z dCBzdHJ1Y3QgbXRrX2RkcF9jb21wX2Z1bmNzIGRkcF9hYWwgPSB7DQo+ICB9Ow0KPiAgDQo+ICBz dGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9mdW5jcyBkZHBfY2NvcnIgPSB7DQo+IC0J LmNsa19lbmFibGUgPSBtdGtfZGRwX2Nsa19lbmFibGUsDQo+IC0JLmNsa19kaXNhYmxlID0gbXRr X2RkcF9jbGtfZGlzYWJsZSwNCj4gKwkuY2xrX2VuYWJsZSA9IG10a19jY29ycl9jbGtfZW5hYmxl LA0KPiArCS5jbGtfZGlzYWJsZSA9IG10a19jY29ycl9jbGtfZGlzYWJsZSwNCj4gIAkuY29uZmln ID0gbXRrX2Njb3JyX2NvbmZpZywNCj4gIAkuc3RhcnQgPSBtdGtfY2NvcnJfc3RhcnQsDQo+ICAJ LnN0b3AgPSBtdGtfY2NvcnJfc3RvcCwNCj4gQEAgLTYxMCw2ICs1MjAsNyBAQCBpbnQgbXRrX2Rk cF9jb21wX2luaXQoc3RydWN0IGRldmljZV9ub2RlICpub2RlLCBzdHJ1Y3QgbXRrX2RkcF9jb21w ICpjb21wLA0KPiAgCX0NCj4gIA0KPiAgCWlmICh0eXBlID09IE1US19ESVNQX0JMUyB8fA0KPiAr CSAgICB0eXBlID09IE1US19ESVNQX0NDT1JSIHx8DQo+ICAJICAgIHR5cGUgPT0gTVRLX0RJU1Bf Q09MT1IgfHwNCj4gIAkgICAgdHlwZSA9PSBNVEtfRElTUF9HQU1NQSB8fA0KPiAgCSAgICB0eXBl ID09IE1US19ESVNQX1BPU1RNQVNLIHx8DQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RybV9kcnYuYyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJt X2Rydi5jDQo+IGluZGV4IGQ5OWFmYzg1Mjg2ODQuLjNkYTg5OTY0MzhkYmMgMTAwNjQ0DQo+IC0t LSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5jDQo+ICsrKyBiL2RyaXZl cnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5jDQo+IEBAIC01MzEsMTEgKzUzMSwxMiBA QCBzdGF0aWMgaW50IG10a19kcm1fcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikN Cj4gIAkJcHJpdmF0ZS0+Y29tcF9ub2RlW2NvbXBfaWRdID0gb2Zfbm9kZV9nZXQobm9kZSk7DQo+ ICANCj4gIAkJLyoNCj4gLQkJICogQ3VycmVudGx5IG9ubHkgdGhlIENPTE9SLCBHQU1NQSwgT1ZM LCBQT1NUTUFTSywgUkRNQSwgRFNJLCBhbmQgRFBJIGJsb2NrcyBoYXZlDQo+IC0JCSAqIHNlcGFy YXRlIGNvbXBvbmVudCBwbGF0Zm9ybSBkcml2ZXJzIGFuZCBpbml0aWFsaXplIHRoZWlyIG93bg0K PiArCQkgKiBDdXJyZW50bHkgb25seSB0aGUgQ0NPUlIsIENPTE9SLCBHQU1NQSwgT1ZMLCBQT1NU TUFTSywgUkRNQSwgRFNJLCBhbmQgRFBJDQo+ICsJCSAqIGJsb2NrcyBoYXZlIHNlcGFyYXRlIGNv bXBvbmVudCBwbGF0Zm9ybSBkcml2ZXJzIGFuZCBpbml0aWFsaXplIHRoZWlyIG93bg0KPiAgCQkg KiBERFAgY29tcG9uZW50IHN0cnVjdHVyZS4gVGhlIG90aGVycyBhcmUgaW5pdGlhbGl6ZWQgaGVy ZS4NCj4gIAkJICovDQo+IC0JCWlmIChjb21wX3R5cGUgPT0gTVRLX0RJU1BfQ09MT1IgfHwNCj4g KwkJaWYgKGNvbXBfdHlwZSA9PSBNVEtfRElTUF9DQ09SUiB8fA0KPiArCQkgICAgY29tcF90eXBl ID09IE1US19ESVNQX0NPTE9SIHx8DQo+ICAJCSAgICBjb21wX3R5cGUgPT0gTVRLX0RJU1BfR0FN TUEgfHwNCj4gIAkJICAgIGNvbXBfdHlwZSA9PSBNVEtfRElTUF9PVkwgfHwNCj4gIAkJICAgIGNv bXBfdHlwZSA9PSBNVEtfRElTUF9PVkxfMkwgfHwNCj4gQEAgLTYzNSw2ICs2MzYsNyBAQCBzdGF0 aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciBtdGtfZHJtX3BsYXRmb3JtX2RyaXZlciA9IHsNCj4g IH07DQo+ICANCj4gIHN0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyICogY29uc3QgbXRrX2Ry bV9kcml2ZXJzW10gPSB7DQo+ICsJJm10a19kaXNwX2Njb3JyX2RyaXZlciwNCj4gIAkmbXRrX2Rp c3BfY29sb3JfZHJpdmVyLA0KPiAgCSZtdGtfZGlzcF9nYW1tYV9kcml2ZXIsDQo+ICAJJm10a19k aXNwX292bF9kcml2ZXIsDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsv bXRrX2RybV9kcnYuaCBiL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5oDQo+ IGluZGV4IDdlN2IyOGUzMmFhMmYuLmI0OTA2MjM2NGMzZDIgMTAwNjQ0DQo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Rydi5oDQo+ICsrKyBiL2RyaXZlcnMvZ3B1L2Ry bS9tZWRpYXRlay9tdGtfZHJtX2Rydi5oDQo+IEBAIC00Niw2ICs0Niw3IEBAIHN0cnVjdCBtdGtf ZHJtX3ByaXZhdGUgew0KPiAgCXN0cnVjdCBkcm1fYXRvbWljX3N0YXRlICpzdXNwZW5kX3N0YXRl Ow0KPiAgfTsNCj4gIA0KPiArZXh0ZXJuIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbXRrX2Rpc3Bf Y2NvcnJfZHJpdmVyOw0KPiAgZXh0ZXJuIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbXRrX2Rpc3Bf Y29sb3JfZHJpdmVyOw0KPiAgZXh0ZXJuIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbXRrX2Rpc3Bf Z2FtbWFfZHJpdmVyOw0KPiAgZXh0ZXJuIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgbXRrX2Rpc3Bf b3ZsX2RyaXZlcjsNCg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0A2D6E41D; Tue, 2 Feb 2021 05:44:32 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id C516F6E41D for ; Tue, 2 Feb 2021 05:44:30 +0000 (UTC) X-UUID: 6a00aef4f2cf4d0ba6c3dc2837633599-20210202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=a/XbKNWHZrzGHmkllglJ5U3wFGb3n7mDtJTAzF3Eq3w=; b=jxSFo4t/bREHFSuvYZmzUNojtjhMNHhpUtpzMw9fu/B/tjd/pkfWau7nRzL2ORbrmSp75LlkdKP0icBzFMgdyCjf/OKo9L55i3DpaXzc+uaBjJAajH5ZfbncHo2zonWz2e5GJxgl/WBvoLcQd3aWiLmih4jjhKm0p1v/yNTZazE=; X-UUID: 6a00aef4f2cf4d0ba6c3dc2837633599-20210202 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1763200846; Tue, 02 Feb 2021 13:44:24 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 13:44:18 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 13:44:18 +0800 Message-ID: <1612244658.5495.2.camel@mtksdaap41> Subject: Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 13:44:18 +0800 In-Reply-To: <20210201103727.376721-5-hsinyi@chromium.org> References: <20210201103727.376721-1-hsinyi@chromium.org> <20210201103727.376721-5-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3B4EDF650D9376DA38E614DC23D5CDAC244606E571EB1A9E0DF85DFCA0AA314D2000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Hsin-Yi: On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > ccorr ctm matrix bits will be different in mt8192 Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index 13a0eafabf9c0..f119bef6d6e66 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_postmask.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index 06d4d4e1c0d05..469d4e12b2003 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index d884807809635..4a8015d247ec7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -234,82 +220,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -348,8 +258,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -610,6 +520,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DISP_POSTMASK || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index d99afc8528684..3da8996438dbc 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -635,6 +636,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 7e7b28e32aa2f..b49062364c3d2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel