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Tue, 02 Feb 2021 01:09:51 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 01:09:50 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 17:09:45 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 17:09:44 +0800 Message-ID: <1612256984.30872.0.camel@mtksdaap41> Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 17:09:44 +0800 In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org> References: <20210202081237.774442-1-hsinyi@chromium.org> <20210202081237.774442-3-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 24F1D7A119950105001D4492531F056C91B137514E2BF6EB5320F55228C749DB2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_040954_506050_2ACA5A1F X-CRM114-Status: GOOD ( 21.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add component POSTMASK. Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56317C433E0 for ; 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Tue, 2 Feb 2021 17:09:44 +0800 Message-ID: <1612256984.30872.0.camel@mtksdaap41> Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 17:09:44 +0800 In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org> References: <20210202081237.774442-1-hsinyi@chromium.org> <20210202081237.774442-3-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 24F1D7A119950105001D4492531F056C91B137514E2BF6EB5320F55228C749DB2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_040954_506050_2ACA5A1F X-CRM114-Status: GOOD ( 21.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Daniel Vetter , Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add component POSTMASK. Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ linux-arm-kernel mailing list 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from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 17:09:45 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 17:09:44 +0800 Message-ID: <1612256984.30872.0.camel@mtksdaap41> Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK From: CK Hu To: Hsin-Yi Wang CC: Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , , , , , , Yongqiang Niu Date: Tue, 2 Feb 2021 17:09:44 +0800 In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org> References: <20210202081237.774442-1-hsinyi@chromium.org> <20210202081237.774442-3-hsinyi@chromium.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 24F1D7A119950105001D4492531F056C91B137514E2BF6EB5320F55228C749DB2000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SGksIEhzaW4tWWk6DQoNCk9uIFR1ZSwgMjAyMS0wMi0wMiBhdCAxNjoxMiArMDgwMCwgSHNpbi1Z aSBXYW5nIHdyb3RlOg0KPiBGcm9tOiBZb25ncWlhbmcgTml1IDx5b25ncWlhbmcubml1QG1lZGlh dGVrLmNvbT4NCj4gDQo+IFRoaXMgcGF0Y2ggYWRkIGNvbXBvbmVudCBQT1NUTUFTSy4NCg0KUmV2 aWV3ZWQtYnk6IENLIEh1IDxjay5odUBtZWRpYXRlay5jb20+DQoNCj4gDQo+IFNpZ25lZC1vZmYt Ynk6IFlvbmdxaWFuZyBOaXUgPHlvbmdxaWFuZy5uaXVAbWVkaWF0ZWsuY29tPg0KPiBTaWduZWQt b2ZmLWJ5OiBIc2luLVlpIFdhbmcgPGhzaW55aUBjaHJvbWl1bS5vcmc+DQo+IC0tLQ0KPiAgZHJp dmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYyB8IDEwMiArKysrKysrKysr KysrKy0tLS0tLQ0KPiAgZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAu aCB8ICAgMSArDQo+ICAyIGZpbGVzIGNoYW5nZWQsIDczIGluc2VydGlvbnMoKyksIDMwIGRlbGV0 aW9ucygtKQ0KPiANCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtf ZHJtX2RkcF9jb21wLmMgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29t cC5jDQo+IGluZGV4IGI2YzRlNzMwMzFjYTYuLjBhODRhZTUzZWI3MmEgMTAwNjQ0DQo+IC0tLSBh L2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmMNCj4gKysrIGIvZHJp dmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuYw0KPiBAQCAtNjQsNiArNjQs MTIgQEANCj4gIA0KPiAgI2RlZmluZSBBQUxfRU4JCQkJCUJJVCgwKQ0KPiAgDQo+ICsjZGVmaW5l IERJU1BfUE9TVE1BU0tfRU4JCQkweDAwMDANCj4gKyNkZWZpbmUgUE9TVE1BU0tfRU4JCQkJQklU KDApDQo+ICsjZGVmaW5lIERJU1BfUE9TVE1BU0tfQ0ZHCQkJMHgwMDIwDQo+ICsjZGVmaW5lIFBP U1RNQVNLX1JFTEFZX01PREUJCQlCSVQoMCkNCj4gKyNkZWZpbmUgRElTUF9QT1NUTUFTS19TSVpF CQkJMHgwMDMwDQo+ICsNCj4gICNkZWZpbmUgRElTUF9ESVRIRVJJTkcJCQkJQklUKDIpDQo+ICAj ZGVmaW5lIERJVEhFUl9MU0JfRVJSX1NISUZUX1IoeCkJCSgoKHgpICYgMHg3KSA8PCAyOCkNCj4g ICNkZWZpbmUgRElUSEVSX09WRkxXX0JJVF9SKHgpCQkJKCgoeCkgJiAweDcpIDw8IDI0KQ0KPiBA QCAtMjA0LDYgKzIxMCwzMiBAQCBzdGF0aWMgdm9pZCBtdGtfdWZvZV9zdGFydChzdHJ1Y3QgZGV2 aWNlICpkZXYpDQo+ICAJd3JpdGVsKFVGT19CWVBBU1MsIHByaXYtPnJlZ3MgKyBESVNQX1JFR19V Rk9fU1RBUlQpOw0KPiAgfQ0KPiAgDQo+ICt2b2lkIG10a19wb3N0bWFza19jb25maWcoc3RydWN0 IGRldmljZSAqZGV2LCB1bnNpZ25lZCBpbnQgdywNCj4gKwkJCXVuc2lnbmVkIGludCBoLCB1bnNp Z25lZCBpbnQgdnJlZnJlc2gsDQo+ICsJCQl1bnNpZ25lZCBpbnQgYnBjLCBzdHJ1Y3QgY21kcV9w a3QgKmNtZHFfcGt0KQ0KPiArew0KPiArCXN0cnVjdCBtdGtfZGRwX2NvbXBfZGV2ICpwcml2ID0g ZGV2X2dldF9kcnZkYXRhKGRldik7DQo+ICsNCj4gKwltdGtfZGRwX3dyaXRlKGNtZHFfcGt0LCB3 IDw8IDE2IHwgaCwgJnByaXYtPmNtZHFfcmVnLCBwcml2LT5yZWdzLA0KPiArCQkgICAgICBESVNQ X1BPU1RNQVNLX1NJWkUpOw0KPiArCW10a19kZHBfd3JpdGUoY21kcV9wa3QsIFBPU1RNQVNLX1JF TEFZX01PREUsICZwcml2LT5jbWRxX3JlZywNCj4gKwkJICAgICAgcHJpdi0+cmVncywgRElTUF9Q T1NUTUFTS19DRkcpOw0KPiArfQ0KPiArDQo+ICt2b2lkIG10a19wb3N0bWFza19zdGFydChzdHJ1 Y3QgZGV2aWNlICpkZXYpDQo+ICt7DQo+ICsJc3RydWN0IG10a19kZHBfY29tcF9kZXYgKnByaXYg PSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gKw0KPiArCXdyaXRlbChQT1NUTUFTS19FTiwgcHJp di0+cmVncyArIERJU1BfUE9TVE1BU0tfRU4pOw0KPiArfQ0KPiArDQo+ICt2b2lkIG10a19wb3N0 bWFza19zdG9wKHN0cnVjdCBkZXZpY2UgKmRldikNCj4gK3sNCj4gKwlzdHJ1Y3QgbXRrX2RkcF9j b21wX2RldiAqcHJpdiA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiArDQo+ICsJd3JpdGVsX3Jl bGF4ZWQoMHgwLCBwcml2LT5yZWdzICsgRElTUF9QT1NUTUFTS19FTik7DQo+ICt9DQo+ICsNCj4g IHN0YXRpYyB2b2lkIG10a19hYWxfY29uZmlnKHN0cnVjdCBkZXZpY2UgKmRldiwgdW5zaWduZWQg aW50IHcsDQo+ICAJCQkgICB1bnNpZ25lZCBpbnQgaCwgdW5zaWduZWQgaW50IHZyZWZyZXNoLA0K PiAgCQkJICAgdW5zaWduZWQgaW50IGJwYywgc3RydWN0IGNtZHFfcGt0ICpjbWRxX3BrdCkNCj4g QEAgLTQxMyw2ICs0NDUsMTQgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfZGRwX2NvbXBfZnVu Y3MgZGRwX292bCA9IHsNCj4gIAkuYmdjbHJfaW5fb2ZmID0gbXRrX292bF9iZ2Nscl9pbl9vZmYs DQo+ICB9Ow0KPiAgDQo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9mdW5jcyBk ZHBfcG9zdG1hc2sgPSB7DQo+ICsJLmNsa19lbmFibGUgPSBtdGtfZGRwX2Nsa19lbmFibGUsDQo+ ICsJLmNsa19kaXNhYmxlID0gbXRrX2RkcF9jbGtfZGlzYWJsZSwNCj4gKwkuY29uZmlnID0gbXRr X3Bvc3RtYXNrX2NvbmZpZywNCj4gKwkuc3RhcnQgPSBtdGtfcG9zdG1hc2tfc3RhcnQsDQo+ICsJ LnN0b3AgPSBtdGtfcG9zdG1hc2tfc3RvcCwNCj4gK307DQo+ICsNCj4gIHN0YXRpYyBjb25zdCBz dHJ1Y3QgbXRrX2RkcF9jb21wX2Z1bmNzIGRkcF9yZG1hID0gew0KPiAgCS5jbGtfZW5hYmxlID0g bXRrX3JkbWFfY2xrX2VuYWJsZSwNCj4gIAkuY2xrX2Rpc2FibGUgPSBtdGtfcmRtYV9jbGtfZGlz YWJsZSwNCj4gQEAgLTQ0OCw2ICs0ODgsNyBAQCBzdGF0aWMgY29uc3QgY2hhciAqIGNvbnN0IG10 a19kZHBfY29tcF9zdGVtW01US19ERFBfQ09NUF9UWVBFX01BWF0gPSB7DQo+ICAJW01US19ESVNQ X01VVEVYXSA9ICJtdXRleCIsDQo+ICAJW01US19ESVNQX09EXSA9ICJvZCIsDQo+ICAJW01US19E SVNQX0JMU10gPSAiYmxzIiwNCj4gKwlbTVRLX0RJU1BfUE9TVE1BU0tdID0gInBvc3RtYXNrIiwN Cj4gIH07DQo+ICANCj4gIHN0cnVjdCBtdGtfZGRwX2NvbXBfbWF0Y2ggew0KPiBAQCAtNDU3LDM2 ICs0OTgsMzcgQEAgc3RydWN0IG10a19kZHBfY29tcF9tYXRjaCB7DQo+ICB9Ow0KPiAgDQo+ICBz dGF0aWMgY29uc3Qgc3RydWN0IG10a19kZHBfY29tcF9tYXRjaCBtdGtfZGRwX21hdGNoZXNbRERQ X0NPTVBPTkVOVF9JRF9NQVhdID0gew0KPiAtCVtERFBfQ09NUE9ORU5UX0FBTDBdCT0geyBNVEtf RElTUF9BQUwsCTAsICZkZHBfYWFsIH0sDQo+IC0JW0REUF9DT01QT05FTlRfQUFMMV0JPSB7IE1U S19ESVNQX0FBTCwJMSwgJmRkcF9hYWwgfSwNCj4gLQlbRERQX0NPTVBPTkVOVF9CTFNdCT0geyBN VEtfRElTUF9CTFMsCTAsIE5VTEwgfSwNCj4gLQlbRERQX0NPTVBPTkVOVF9DQ09SUl0JPSB7IE1U S19ESVNQX0NDT1JSLAkwLCAmZGRwX2Njb3JyIH0sDQo+IC0JW0REUF9DT01QT05FTlRfQ09MT1Iw XQk9IHsgTVRLX0RJU1BfQ09MT1IsCTAsICZkZHBfY29sb3IgfSwNCj4gLQlbRERQX0NPTVBPTkVO VF9DT0xPUjFdCT0geyBNVEtfRElTUF9DT0xPUiwJMSwgJmRkcF9jb2xvciB9LA0KPiAtCVtERFBf Q09NUE9ORU5UX0RJVEhFUl0JPSB7IE1US19ESVNQX0RJVEhFUiwJMCwgJmRkcF9kaXRoZXIgfSwN Cj4gLQlbRERQX0NPTVBPTkVOVF9EUEkwXQk9IHsgTVRLX0RQSSwJCTAsICZkZHBfZHBpIH0sDQo+ IC0JW0REUF9DT01QT05FTlRfRFBJMV0JPSB7IE1US19EUEksCQkxLCAmZGRwX2RwaSB9LA0KPiAt CVtERFBfQ09NUE9ORU5UX0RTSTBdCT0geyBNVEtfRFNJLAkJMCwgJmRkcF9kc2kgfSwNCj4gLQlb RERQX0NPTVBPTkVOVF9EU0kxXQk9IHsgTVRLX0RTSSwJCTEsICZkZHBfZHNpIH0sDQo+IC0JW0RE UF9DT01QT05FTlRfRFNJMl0JPSB7IE1US19EU0ksCQkyLCAmZGRwX2RzaSB9LA0KPiAtCVtERFBf Q09NUE9ORU5UX0RTSTNdCT0geyBNVEtfRFNJLAkJMywgJmRkcF9kc2kgfSwNCj4gLQlbRERQX0NP TVBPTkVOVF9HQU1NQV0JPSB7IE1US19ESVNQX0dBTU1BLAkwLCAmZGRwX2dhbW1hIH0sDQo+IC0J W0REUF9DT01QT05FTlRfT0QwXQk9IHsgTVRLX0RJU1BfT0QsCTAsICZkZHBfb2QgfSwNCj4gLQlb RERQX0NPTVBPTkVOVF9PRDFdCT0geyBNVEtfRElTUF9PRCwJMSwgJmRkcF9vZCB9LA0KPiAtCVtE RFBfQ09NUE9ORU5UX09WTDBdCT0geyBNVEtfRElTUF9PVkwsCTAsICZkZHBfb3ZsIH0sDQo+IC0J W0REUF9DT01QT05FTlRfT1ZMMV0JPSB7IE1US19ESVNQX09WTCwJMSwgJmRkcF9vdmwgfSwNCj4g LQlbRERQX0NPTVBPTkVOVF9PVkxfMkwwXQk9IHsgTVRLX0RJU1BfT1ZMXzJMLAkwLCAmZGRwX292 bCB9LA0KPiAtCVtERFBfQ09NUE9ORU5UX09WTF8yTDFdCT0geyBNVEtfRElTUF9PVkxfMkwsCTEs ICZkZHBfb3ZsIH0sDQo+IC0JW0REUF9DT01QT05FTlRfT1ZMXzJMMl0gPSB7IE1US19ESVNQX09W TF8yTCwgICAgMiwgJmRkcF9vdmwgfSwNCj4gLQlbRERQX0NPTVBPTkVOVF9QV00wXQk9IHsgTVRL X0RJU1BfUFdNLAkwLCBOVUxMIH0sDQo+IC0JW0REUF9DT01QT05FTlRfUFdNMV0JPSB7IE1US19E SVNQX1BXTSwJMSwgTlVMTCB9LA0KPiAtCVtERFBfQ09NUE9ORU5UX1BXTTJdCT0geyBNVEtfRElT UF9QV00sCTIsIE5VTEwgfSwNCj4gLQlbRERQX0NPTVBPTkVOVF9SRE1BMF0JPSB7IE1US19ESVNQ X1JETUEsCTAsICZkZHBfcmRtYSB9LA0KPiAtCVtERFBfQ09NUE9ORU5UX1JETUExXQk9IHsgTVRL X0RJU1BfUkRNQSwJMSwgJmRkcF9yZG1hIH0sDQo+IC0JW0REUF9DT01QT05FTlRfUkRNQTJdCT0g eyBNVEtfRElTUF9SRE1BLAkyLCAmZGRwX3JkbWEgfSwNCj4gLQlbRERQX0NPTVBPTkVOVF9VRk9F XQk9IHsgTVRLX0RJU1BfVUZPRSwJMCwgJmRkcF91Zm9lIH0sDQo+IC0JW0REUF9DT01QT05FTlRf V0RNQTBdCT0geyBNVEtfRElTUF9XRE1BLAkwLCBOVUxMIH0sDQo+IC0JW0REUF9DT01QT05FTlRf V0RNQTFdCT0geyBNVEtfRElTUF9XRE1BLAkxLCBOVUxMIH0sDQo+ICsJW0REUF9DT01QT05FTlRf QUFMMF0JCT0geyBNVEtfRElTUF9BQUwsCTAsICZkZHBfYWFsIH0sDQo+ICsJW0REUF9DT01QT05F TlRfQUFMMV0JCT0geyBNVEtfRElTUF9BQUwsCTEsICZkZHBfYWFsIH0sDQo+ICsJW0REUF9DT01Q T05FTlRfQkxTXQkJPSB7IE1US19ESVNQX0JMUywJMCwgTlVMTCB9LA0KPiArCVtERFBfQ09NUE9O RU5UX0NDT1JSXQkJPSB7IE1US19ESVNQX0NDT1JSLAkwLCAmZGRwX2Njb3JyIH0sDQo+ICsJW0RE UF9DT01QT05FTlRfQ09MT1IwXQkJPSB7IE1US19ESVNQX0NPTE9SLAkwLCAmZGRwX2NvbG9yIH0s DQo+ICsJW0REUF9DT01QT05FTlRfQ09MT1IxXQkJPSB7IE1US19ESVNQX0NPTE9SLAkxLCAmZGRw X2NvbG9yIH0sDQo+ICsJW0REUF9DT01QT05FTlRfRElUSEVSXQkJPSB7IE1US19ESVNQX0RJVEhF UiwJMCwgJmRkcF9kaXRoZXIgfSwNCj4gKwlbRERQX0NPTVBPTkVOVF9EUEkwXQkJPSB7IE1US19E UEksCQkwLCAmZGRwX2RwaSB9LA0KPiArCVtERFBfQ09NUE9ORU5UX0RQSTFdCQk9IHsgTVRLX0RQ SSwJCTEsICZkZHBfZHBpIH0sDQo+ICsJW0REUF9DT01QT05FTlRfRFNJMF0JCT0geyBNVEtfRFNJ LAkJMCwgJmRkcF9kc2kgfSwNCj4gKwlbRERQX0NPTVBPTkVOVF9EU0kxXQkJPSB7IE1US19EU0ks CQkxLCAmZGRwX2RzaSB9LA0KPiArCVtERFBfQ09NUE9ORU5UX0RTSTJdCQk9IHsgTVRLX0RTSSwJ CTIsICZkZHBfZHNpIH0sDQo+ICsJW0REUF9DT01QT05FTlRfRFNJM10JCT0geyBNVEtfRFNJLAkJ MywgJmRkcF9kc2kgfSwNCj4gKwlbRERQX0NPTVBPTkVOVF9HQU1NQV0JCT0geyBNVEtfRElTUF9H QU1NQSwJMCwgJmRkcF9nYW1tYSB9LA0KPiArCVtERFBfQ09NUE9ORU5UX09EMF0JCT0geyBNVEtf RElTUF9PRCwJMCwgJmRkcF9vZCB9LA0KPiArCVtERFBfQ09NUE9ORU5UX09EMV0JCT0geyBNVEtf RElTUF9PRCwJMSwgJmRkcF9vZCB9LA0KPiArCVtERFBfQ09NUE9ORU5UX09WTDBdCQk9IHsgTVRL X0RJU1BfT1ZMLAkwLCAmZGRwX292bCB9LA0KPiArCVtERFBfQ09NUE9ORU5UX09WTDFdCQk9IHsg TVRLX0RJU1BfT1ZMLAkxLCAmZGRwX292bCB9LA0KPiArCVtERFBfQ09NUE9ORU5UX09WTF8yTDBd CQk9IHsgTVRLX0RJU1BfT1ZMXzJMLAkwLCAmZGRwX292bCB9LA0KPiArCVtERFBfQ09NUE9ORU5U X09WTF8yTDFdCQk9IHsgTVRLX0RJU1BfT1ZMXzJMLAkxLCAmZGRwX292bCB9LA0KPiArCVtERFBf Q09NUE9ORU5UX09WTF8yTDJdCQk9IHsgTVRLX0RJU1BfT1ZMXzJMLCAgICAyLCAmZGRwX292bCB9 LA0KPiArCVtERFBfQ09NUE9ORU5UX1BPU1RNQVNLMF0JPSB7IE1US19ESVNQX1BPU1RNQVNLLAkw LCAmZGRwX3Bvc3RtYXNrIH0sDQo+ICsJW0REUF9DT01QT05FTlRfUFdNMF0JCT0geyBNVEtfRElT UF9QV00sCTAsIE5VTEwgfSwNCj4gKwlbRERQX0NPTVBPTkVOVF9QV00xXQkJPSB7IE1US19ESVNQ X1BXTSwJMSwgTlVMTCB9LA0KPiArCVtERFBfQ09NUE9ORU5UX1BXTTJdCQk9IHsgTVRLX0RJU1Bf UFdNLAkyLCBOVUxMIH0sDQo+ICsJW0REUF9DT01QT05FTlRfUkRNQTBdCQk9IHsgTVRLX0RJU1Bf UkRNQSwJMCwgJmRkcF9yZG1hIH0sDQo+ICsJW0REUF9DT01QT05FTlRfUkRNQTFdCQk9IHsgTVRL X0RJU1BfUkRNQSwJMSwgJmRkcF9yZG1hIH0sDQo+ICsJW0REUF9DT01QT05FTlRfUkRNQTJdCQk9 IHsgTVRLX0RJU1BfUkRNQSwJMiwgJmRkcF9yZG1hIH0sDQo+ICsJW0REUF9DT01QT05FTlRfVUZP RV0JCT0geyBNVEtfRElTUF9VRk9FLAkwLCAmZGRwX3Vmb2UgfSwNCj4gKwlbRERQX0NPTVBPTkVO VF9XRE1BMF0JCT0geyBNVEtfRElTUF9XRE1BLAkwLCBOVUxMIH0sDQo+ICsJW0REUF9DT01QT05F TlRfV0RNQTFdCQk9IHsgTVRLX0RJU1BfV0RNQSwJMSwgTlVMTCB9LA0KPiAgfTsNCj4gIA0KPiAg c3RhdGljIGJvb2wgbXRrX2RybV9maW5kX2NvbXBfaW5fZGRwKHN0cnVjdCBkZXZpY2UgKmRldiwN Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21w LmggYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHBfY29tcC5oDQo+IGluZGV4 IGJiOTE0ZDk3NmNmNWQuLmNkMWRlYzZiNGNkZjIgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHJtX2RkcF9jb21wLmgNCj4gKysrIGIvZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kcm1fZGRwX2NvbXAuaA0KPiBAQCAtMzAsNiArMzAsNyBAQCBlbnVtIG10 a19kZHBfY29tcF90eXBlIHsNCj4gIAlNVEtfRElTUF9VRk9FLA0KPiAgCU1US19EU0ksDQo+ICAJ TVRLX0RQSSwNCj4gKwlNVEtfRElTUF9QT1NUTUFTSywNCj4gIAlNVEtfRElTUF9QV00sDQo+ICAJ TVRLX0RJU1BfTVVURVgsDQo+ICAJTVRLX0RJU1BfT0QsDQoNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B17FDC433DB for ; Tue, 2 Feb 2021 09:09:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63E4164F60 for ; Tue, 2 Feb 2021 09:09:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63E4164F60 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C81276E917; Tue, 2 Feb 2021 09:09:56 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by gabe.freedesktop.org (Postfix) with ESMTP id F0B0C6E917 for ; Tue, 2 Feb 2021 09:09:54 +0000 (UTC) X-UUID: 9c4d6605fa1444f584f3e8ca62be12cf-20210202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=48WMS0C2dNHok4VaSyMe6J6g/25yOj+mMhFukkBEv/Q=; b=HRvtPGwCs4qZXdPyV2kk+cXb26Zl6YH1dxADC7Uv2JA+mn7jitkqbWOGRClftH79w1RLAdm9QH/wyI1MGsQJhyu8nVKi45+QYsyiVFWIKyDCUwF9ulAQAIv9OCuV97+QfrKy9vu+i/ryapyIhJKNMafFJ9j6OKQ/nHrdPLRiqUU=; X-UUID: 9c4d6605fa1444f584f3e8ca62be12cf-20210202 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 690614006; Tue, 02 Feb 2021 17:09:49 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 17:09:45 +0800 Received: from [172.21.77.4] (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 2 Feb 2021 17:09:44 +0800 Message-ID: <1612256984.30872.0.camel@mtksdaap41> Subject: Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK From: CK Hu To: Hsin-Yi Wang Date: Tue, 2 Feb 2021 17:09:44 +0800 In-Reply-To: <20210202081237.774442-3-hsinyi@chromium.org> References: <20210202081237.774442-1-hsinyi@chromium.org> <20210202081237.774442-3-hsinyi@chromium.org> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 24F1D7A119950105001D4492531F056C91B137514E2BF6EB5320F55228C749DB2000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add component POSTMASK. Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel