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Sat, 06 Feb 2021 18:27:26 -0800 Received: from MTKMBS32N2.mediatek.inc (172.27.4.72) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Feb 2021 18:27:19 -0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS32N2.mediatek.inc (172.27.4.72) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 7 Feb 2021 10:27:14 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 7 Feb 2021 10:27:13 +0800 Message-ID: <1612664833.5147.30.camel@mhfsdcap03> Subject: Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 From: Chunfeng Yun To: Mathias Nyman Date: Sun, 7 Feb 2021 10:27:13 +0800 In-Reply-To: <20210203102642.7353-2-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> <20210203102642.7353-2-chunfeng.yun@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1B014D2086C1D7CBBFCF7F12F97C71D0892D48B7553418545A58616630F2A3202000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210206_212732_565776_60B2A829 X-CRM114-Status: GOOD ( 23.92 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Mathias Nyman , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Ikjoon Jang , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Mathias, On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote: > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > exclude IP0) have a wrong default SOF/ITP interval which is > calculated from the frame counter clock 24Mhz by default, but > in fact, the frame counter clock is 48Mhz, so we should set > the accurate interval according to 48Mhz for those controllers. > Note: the first controller no need set it. > > Signed-off-by: Chunfeng Yun > --- > v2: fix typo of comaptible > --- > drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c > index 8f321f39ab96..0a68c4ac8b48 100644 > --- a/drivers/usb/host/xhci-mtk.c > +++ b/drivers/usb/host/xhci-mtk.c > @@ -68,11 +68,71 @@ > #define SSC_IP_SLEEP_EN BIT(4) > #define SSC_SPM_INT_EN BIT(1) > Can I Read/Write the following xHCI controller's registers in xhci-mtk.c? Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a glue driver used to initialize clocks/power and IPPC registers which don't belong to xHCI controller. Thanks > +/* xHCI csr */ > +#define LS_EOF 0x930 > +#define LS_EOF_OFFSET 0x89 > + > +#define FS_EOF 0x934 > +#define FS_EOF_OFFSET 0x2e > + > +#define SS_GEN1_EOF 0x93c > +#define SS_GEN1_EOF_OFFSET 0x78 > + > +#define HFCNTR_CFG 0x944 > +#define ITP_DELTA_CLK (0xa << 1) > +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) > +#define FRMCNT_LEV1_RANG (0x12b << 8) > +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) > + > +#define SS_GEN2_EOF 0x990 > +#define SS_GEN2_EOF_OFFSET 0x3c > +#define EOF_OFFSET_MASK GENMASK(11, 0) > + > enum ssusb_uwk_vers { > SSUSB_UWK_V1 = 1, > SSUSB_UWK_V2, > }; > > +/* > + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval > + * is calculated from the frame counter clock 24M, but in fact, the clock > + * is 48M, so need change the interval. > + */ > +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) > +{ > + struct device *dev = mtk->dev; > + struct usb_hcd *hcd = mtk->hcd; > + u32 value; > + > + if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) > + return; > + > + value = readl(hcd->regs + HFCNTR_CFG); > + value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); > + value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); > + writel(value, hcd->regs + HFCNTR_CFG); > + > + value = readl(hcd->regs + LS_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= LS_EOF_OFFSET; > + writel(value, hcd->regs + LS_EOF); > + > + value = readl(hcd->regs + FS_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= FS_EOF_OFFSET; > + writel(value, hcd->regs + FS_EOF); > + > + value = readl(hcd->regs + SS_GEN1_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= SS_GEN1_EOF_OFFSET; > + writel(value, hcd->regs + SS_GEN1_EOF); > + > + value = readl(hcd->regs + SS_GEN2_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= SS_GEN2_EOF_OFFSET; > + writel(value, hcd->regs + SS_GEN2_EOF); > +} > + > static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) > { > struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; > @@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) > ret = xhci_mtk_ssusb_config(mtk); > if (ret) > return ret; > + > + xhci_mtk_set_frame_interval(mtk); > } > > ret = xhci_gen_setup(hcd, xhci_mtk_quirks); > @@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = { > #ifdef CONFIG_OF > static const struct of_device_id mtk_xhci_of_match[] = { > { .compatible = "mediatek,mt8173-xhci"}, > + { .compatible = "mediatek,mt8195-xhci"}, > { .compatible = "mediatek,mtk-xhci"}, > { }, > }; _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, 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<1612664833.5147.30.camel@mhfsdcap03> Subject: Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 From: Chunfeng Yun To: Mathias Nyman CC: Rob Herring , Matthias Brugger , Mathias Nyman , "Greg Kroah-Hartman" , , , , , , "Ikjoon Jang" , Nicolas Boichat Date: Sun, 7 Feb 2021 10:27:13 +0800 In-Reply-To: <20210203102642.7353-2-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> <20210203102642.7353-2-chunfeng.yun@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1B014D2086C1D7CBBFCF7F12F97C71D0892D48B7553418545A58616630F2A3202000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org SGkgTWF0aGlhcywNCg0KT24gV2VkLCAyMDIxLTAyLTAzIGF0IDE4OjI2ICswODAwLCBDaHVuZmVu ZyBZdW4gd3JvdGU6DQo+IFRoZXJlIGFyZSA0IFVTQiBjb250cm9sbGVycyBvbiBNVDgxOTUsIHRo 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mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 71108271; Sat, 06 Feb 2021 18:27:26 -0800 Received: from MTKMBS32N2.mediatek.inc (172.27.4.72) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Feb 2021 18:27:19 -0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS32N2.mediatek.inc (172.27.4.72) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 7 Feb 2021 10:27:14 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 7 Feb 2021 10:27:13 +0800 Message-ID: <1612664833.5147.30.camel@mhfsdcap03> Subject: Re: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 From: Chunfeng Yun To: Mathias Nyman Date: Sun, 7 Feb 2021 10:27:13 +0800 In-Reply-To: <20210203102642.7353-2-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> <20210203102642.7353-2-chunfeng.yun@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1B014D2086C1D7CBBFCF7F12F97C71D0892D48B7553418545A58616630F2A3202000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210206_212732_565776_60B2A829 X-CRM114-Status: GOOD ( 23.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Mathias Nyman , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Ikjoon Jang , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mathias, On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote: > There are 4 USB controllers on MT8195, the controllers (IP1~IP3, > exclude IP0) have a wrong default SOF/ITP interval which is > calculated from the frame counter clock 24Mhz by default, but > in fact, the frame counter clock is 48Mhz, so we should set > the accurate interval according to 48Mhz for those controllers. > Note: the first controller no need set it. > > Signed-off-by: Chunfeng Yun > --- > v2: fix typo of comaptible > --- > drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c > index 8f321f39ab96..0a68c4ac8b48 100644 > --- a/drivers/usb/host/xhci-mtk.c > +++ b/drivers/usb/host/xhci-mtk.c > @@ -68,11 +68,71 @@ > #define SSC_IP_SLEEP_EN BIT(4) > #define SSC_SPM_INT_EN BIT(1) > Can I Read/Write the following xHCI controller's registers in xhci-mtk.c? Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a glue driver used to initialize clocks/power and IPPC registers which don't belong to xHCI controller. Thanks > +/* xHCI csr */ > +#define LS_EOF 0x930 > +#define LS_EOF_OFFSET 0x89 > + > +#define FS_EOF 0x934 > +#define FS_EOF_OFFSET 0x2e > + > +#define SS_GEN1_EOF 0x93c > +#define SS_GEN1_EOF_OFFSET 0x78 > + > +#define HFCNTR_CFG 0x944 > +#define ITP_DELTA_CLK (0xa << 1) > +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) > +#define FRMCNT_LEV1_RANG (0x12b << 8) > +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) > + > +#define SS_GEN2_EOF 0x990 > +#define SS_GEN2_EOF_OFFSET 0x3c > +#define EOF_OFFSET_MASK GENMASK(11, 0) > + > enum ssusb_uwk_vers { > SSUSB_UWK_V1 = 1, > SSUSB_UWK_V2, > }; > > +/* > + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval > + * is calculated from the frame counter clock 24M, but in fact, the clock > + * is 48M, so need change the interval. > + */ > +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) > +{ > + struct device *dev = mtk->dev; > + struct usb_hcd *hcd = mtk->hcd; > + u32 value; > + > + if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) > + return; > + > + value = readl(hcd->regs + HFCNTR_CFG); > + value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); > + value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); > + writel(value, hcd->regs + HFCNTR_CFG); > + > + value = readl(hcd->regs + LS_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= LS_EOF_OFFSET; > + writel(value, hcd->regs + LS_EOF); > + > + value = readl(hcd->regs + FS_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= FS_EOF_OFFSET; > + writel(value, hcd->regs + FS_EOF); > + > + value = readl(hcd->regs + SS_GEN1_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= SS_GEN1_EOF_OFFSET; > + writel(value, hcd->regs + SS_GEN1_EOF); > + > + value = readl(hcd->regs + SS_GEN2_EOF); > + value &= ~EOF_OFFSET_MASK; > + value |= SS_GEN2_EOF_OFFSET; > + writel(value, hcd->regs + SS_GEN2_EOF); > +} > + > static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) > { > struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; > @@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) > ret = xhci_mtk_ssusb_config(mtk); > if (ret) > return ret; > + > + xhci_mtk_set_frame_interval(mtk); > } > > ret = xhci_gen_setup(hcd, xhci_mtk_quirks); > @@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = { > #ifdef CONFIG_OF > static const struct of_device_id mtk_xhci_of_match[] = { > { .compatible = "mediatek,mt8173-xhci"}, > + { .compatible = "mediatek,mt8195-xhci"}, > { .compatible = "mediatek,mtk-xhci"}, > { }, > }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel