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diff for duplicates of <1613388.aipGbOUUHC@phil>

diff --git a/a/1.txt b/N1/1.txt
index e950ce7..663cfd4 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -10,17 +10,15 @@ is way safer than using clk_ignore_unused - see rk3399.
 Some highlights down below
 
 
-Am Donnerstag, 16. M=E4rz 2017, 16:44:52 CET schrieb Elaine Zhang:
+Am Donnerstag, 16. März 2017, 16:44:52 CET schrieb Elaine Zhang:
 > set pclk_cpu and hclk_cpu as critical_clocks
->=20
+> 
 > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 > ---
->  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------=
-=2D-----
+>  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------------
 >  1 file changed, 34 insertions(+), 32 deletions(-)
->=20
-> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk=
-=2Drk3228.c
+> 
+> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
 > index db6e5a9e6de6..9f82d089084e 100644
 > --- a/drivers/clk/rockchip/clk-rk3228.c
 > +++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -42,262 +40,164 @@ both not needed if you make pclk_ddrupctl and friends critical
 > @@ -445,7 +445,7 @@ enum rk3228_plls {
 >  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
 >  			&rk3228_spdif_fracmux),
-> =20
+>  
 > -	GATE(0, "jtag", "ext_jtag", 0,
 > +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 >  			RK2928_CLKGATE_CON(1), 3, GFLAGS),
-> =20
+>  
 >  	GATE(0, "sclk_otgphy0", "xin24m", 0,
 > @@ -527,24 +527,24 @@ enum rk3228_plls {
-> =20
+>  
 >  	/* PD_VOP */
->  	GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAG=
-S),
-> -	GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, =
-GFLAGS),
-> +	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 11, GFLAGS),
->  	GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAG=
-S),
-> -	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, G=
-=46LAGS),
-> +	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 9, GFLAGS),
+>  	GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
+> -	GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
+> +	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),
+>  	GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
+> -	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
+> +	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),
 
 please make noc-clocks critical, see rk3399
 
-> =20
->  	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5=
-, GFLAGS),
-> -	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, =
-GFLAGS),
-> +	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 12, GFLAGS),
-> =20
->  	GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GF=
-LAGS),
-> -	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10=
-, GFLAGS),
-> +	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(13), 10, GFLAGS),
-> =20
->  	GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAG=
-S),
->  	GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAG=
-S),
->  	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6=
-, GFLAGS),
-> -	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13),=
- 7, GFLAGS),
-> -	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, G=
-=46LAGS),
-> -	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, =
-GFLAGS),
-> +	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_=
-CLKGATE_CON(13), 7, GFLAGS),
-> +	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 8, GFLAGS),
-> +	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 13, GFLAGS),
->  	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, G=
-=46LAGS),
-> -	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12,=
- GFLAGS),
-> +	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(14), 12, GFLAGS),
+>  
+>  	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
+> -	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
+> +	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),
+>  
+>  	GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
+> -	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
+> +	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 10, GFLAGS),
+>  
+>  	GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
+>  	GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
+>  	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
+> -	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
+> -	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
+> -	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
+> +	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),
+> +	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),
+> +	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),
+>  	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
+> -	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
+> +	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 12, GFLAGS),
 
 I would assume the hdcp-iommu should handle this clock, why does it need
 to be always on?
 
 
->  	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGAT=
-E_CON(14), 6, GFLAGS),
->  	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, G=
-=46LAGS),
->  	GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFL=
-AGS),
+>  	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
+>  	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
+>  	GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
 > @@ -558,13 +558,13 @@ enum rk3228_plls {
->  	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2,=
- GFLAGS),
->  	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), =
-3, GFLAGS),
->  	GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS=
-),
-> -	GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GF=
-LAGS),
-> +	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 7, GFLAGS),
->  	GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS=
-),
-> -	GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GF=
-LAGS),
-> +	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 9, GFLAGS),
->  	GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAG=
-S),
+>  	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
+>  	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
+>  	GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
+> -	GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
+> +	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),
+>  	GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
+> -	GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
+> +	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),
+>  	GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
 >  	GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
-> -	GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFL=
-AGS),
-> -	GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, G=
-=46LAGS),
-> +	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_=
-CON(11), 13, GFLAGS),
-> +	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 14, GFLAGS),
+> -	GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
+> -	GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
+> +	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),
+> +	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),
 
 same as noc clocks, make arbiter clocks critical instead
 
->  	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE=
-_CON(12), 1, GFLAGS),
-> =20
->  	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5,=
- GFLAGS),
+>  	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
+>  
+>  	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
 > @@ -572,15 +572,15 @@ enum rk3228_plls {
-> =20
+>  
 >  	/* PD_GPU */
->  	GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLA=
-GS),
-> -	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, =
-GFLAGS),
-> +	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 15, GFLAGS),
-> =20
+>  	GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
+> -	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+> +	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+>  
 >  	/* PD_BUS */
-> -	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, =
-GFLAGS),
-> -	GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS=
-),
-> +	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(8), 1, GFLAGS),
-> +	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=
-ON(8), 0, GFLAGS),
->  	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), =
-2, GFLAGS),
->  	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=
-ON(10), 1, GFLAGS),
-> =20
+> -	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
+> -	GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
+> +	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),
+> +	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),
+>  	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
+>  	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
+>  
 > -	GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
-> +	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8=
-), 3, GFLAGS),
->  	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 7, GFLAGS),
->  	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 8, GFLAGS),
->  	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 9, GFLAGS),
+> +	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),
+>  	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
+>  	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
+>  	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
 > @@ -589,18 +589,18 @@ enum rk3228_plls {
->  	GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GF=
-LAGS),
->  	GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GF=
-LAGS),
-> =20
-> -	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, G=
-=46LAGS),
-> -	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFL=
-AGS),
-> -	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, =
-GFLAGS),
-> +	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(8), 4, GFLAGS),
-> +	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(8), 6, GFLAGS),
-> +	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(10), 2, GFLAGS),
+>  	GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+>  	GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+>  
+> -	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+> -	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+> -	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+> +	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+> +	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+> +	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
 
 again critical
 
 
-> -	GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GF=
-LAGS),
-> -	GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFL=
-AGS),
-> +	GATE(0, "pclk_efuse_1024", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(8), 13, GFLAGS),
-> +	GATE(0, "pclk_efuse_256", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE=
-_CON(8), 14, GFLAGS),
+> -	GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+> -	GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
+> +	GATE(0, "pclk_efuse_1024", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+> +	GATE(0, "pclk_efuse_256", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 14, GFLAGS),
 
 we do have a general efuse driver, why do these clocks need to be on?
 
 
->  	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, =
-GFLAGS),
->  	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, G=
-=46LAGS),
->  	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, G=
-=46LAGS),
->  	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, G=
-=46LAGS),
->  	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4=
-, GFLAGS),
+>  	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
+>  	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
+>  	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
+>  	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
+>  	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
 > -	GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
-> +	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CO=
-N(9), 5, GFLAGS),
->  	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, G=
-=46LAGS),
->  	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, =
-GFLAGS),
->  	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8,=
- GFLAGS),
+> +	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),
+>  	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
+>  	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
+>  	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
 > @@ -616,20 +616,20 @@ enum rk3228_plls {
->  	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(=
-10), 2, GFLAGS),
+>  	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
 >  	GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
-> =20
-> -	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GF=
-LAGS),
-> -	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5,=
- GFLAGS),
-> +	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(10), 3, GFLAGS),
-> +	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(10), 5, GFLAGS),
->  	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_C=
-ON(10), 7, GFLAGS),
->  	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, G=
-=46LAGS),
-> -	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, G=
-=46LAGS),
-> +	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(10), 9, GFLAGS),
-> =20
->  	GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAG=
-S),
-> -	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, G=
-=46LAGS),
-> +	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(15), 4, GFLAGS),
->  	GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2,=
- GFLAGS),
-> -	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15)=
-, 6, GFLAGS),
-> +	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928=
-_CLKGATE_CON(15), 6, GFLAGS),
->  	GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAG=
-S),
-> -	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, G=
-=46LAGS),
-> +	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(15), 5, GFLAGS),
->  	GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3,=
- GFLAGS),
-> -	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15)=
-, 7, GFLAGS),
-> +	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928=
-_CLKGATE_CON(15), 7, GFLAGS),
-> =20
+>  
+> -	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+> -	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+> +	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+> +	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+>  	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+>  	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
+> -	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+> +	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+>  
+>  	GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
+> -	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
+> +	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),
+>  	GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
+> -	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
+> +	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),
+>  	GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
+> -	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
+> +	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),
+>  	GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
+> -	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
+> +	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),
+>  
 >  	/* PD_MMC */
->  	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0,=
- 1),
+>  	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
 > @@ -644,6 +644,8 @@ enum rk3228_plls {
-> =20
->  static const char *const rk3228_critical_clocks[] __initconst =3D {
+>  
+>  static const char *const rk3228_critical_clocks[] __initconst = {
 >  	"aclk_cpu",
 > +	"pclk_cpu",
 > +	"hclk_cpu",
 >  	"aclk_peri",
 >  	"hclk_peri",
 >  	"pclk_peri",
->=20
+> 
 
 
 Heiko
diff --git a/a/content_digest b/N1/content_digest
index ac738ea..7ceab19 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -26,17 +26,15 @@
  "Some highlights down below\n"
  "\n"
  "\n"
- "Am Donnerstag, 16. M=E4rz 2017, 16:44:52 CET schrieb Elaine Zhang:\n"
+ "Am Donnerstag, 16. M\303\244rz 2017, 16:44:52 CET schrieb Elaine Zhang:\n"
  "> set pclk_cpu and hclk_cpu as critical_clocks\n"
- ">=20\n"
+ "> \n"
  "> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>\n"
  "> ---\n"
- ">  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------=\n"
- "=2D-----\n"
+ ">  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------------\n"
  ">  1 file changed, 34 insertions(+), 32 deletions(-)\n"
- ">=20\n"
- "> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk=\n"
- "=2Drk3228.c\n"
+ "> \n"
+ "> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c\n"
  "> index db6e5a9e6de6..9f82d089084e 100644\n"
  "> --- a/drivers/clk/rockchip/clk-rk3228.c\n"
  "> +++ b/drivers/clk/rockchip/clk-rk3228.c\n"
@@ -58,264 +56,166 @@
  "> @@ -445,7 +445,7 @@ enum rk3228_plls {\n"
  ">  \t\t\tRK2928_CLKGATE_CON(2), 12, GFLAGS,\n"
  ">  \t\t\t&rk3228_spdif_fracmux),\n"
- "> =20\n"
+ ">  \n"
  "> -\tGATE(0, \"jtag\", \"ext_jtag\", 0,\n"
  "> +\tGATE(0, \"jtag\", \"ext_jtag\", CLK_IGNORE_UNUSED,\n"
  ">  \t\t\tRK2928_CLKGATE_CON(1), 3, GFLAGS),\n"
- "> =20\n"
+ ">  \n"
  ">  \tGATE(0, \"sclk_otgphy0\", \"xin24m\", 0,\n"
  "> @@ -527,24 +527,24 @@ enum rk3228_plls {\n"
- "> =20\n"
+ ">  \n"
  ">  \t/* PD_VOP */\n"
- ">  \tGATE(0, \"aclk_rga\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 0, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 11, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 11, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_iep\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 2, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 9, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 9, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_rga\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_iep\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),\n"
  "\n"
  "please make noc-clocks critical, see rk3399\n"
  "\n"
- "> =20\n"
- ">  \tGATE(ACLK_VOP, \"aclk_vop\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 5=\n"
- ", GFLAGS),\n"
- "> -\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 12, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 12, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"aclk_hdcp\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(14), 10, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(13), 10=\n"
- ", GFLAGS),\n"
- "> +\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(13), 10, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"hclk_rga\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 1, GFLAG=\n"
- "S),\n"
- ">  \tGATE(0, \"hclk_iep\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 3, GFLAG=\n"
- "S),\n"
- ">  \tGATE(HCLK_VOP, \"hclk_vop\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 6=\n"
- ", GFLAGS),\n"
- "> -\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13),=\n"
- " 7, GFLAGS),\n"
- "> -\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 8, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 13, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_=\n"
- "CLKGATE_CON(13), 7, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 8, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 13, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 7, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 12,=\n"
- " GFLAGS),\n"
- "> +\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(14), 12, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(ACLK_VOP, \"aclk_vop\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"aclk_hdcp\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 10, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"hclk_rga\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_iep\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),\n"
+ ">  \tGATE(HCLK_VOP, \"hclk_vop\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 12, GFLAGS),\n"
  "\n"
  "I would assume the hdcp-iommu should handle this clock, why does it need\n"
  "to be always on?\n"
  "\n"
  "\n"
- ">  \tGATE(PCLK_HDMI_CTRL, \"pclk_hdmi_ctrl\", \"hclk_vio_pre\", 0, RK2928_CLKGAT=\n"
- "E_CON(14), 6, GFLAGS),\n"
- ">  \tGATE(0, \"pclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 8, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(0, \"pclk_hdcp\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 11, GFL=\n"
- "AGS),\n"
+ ">  \tGATE(PCLK_HDMI_CTRL, \"pclk_hdmi_ctrl\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_hdcp\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),\n"
  "> @@ -558,13 +558,13 @@ enum rk3228_plls {\n"
- ">  \tGATE(HCLK_EMMC, \"hclk_emmc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 2,=\n"
- " GFLAGS),\n"
- ">  \tGATE(HCLK_NANDC, \"hclk_nandc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), =\n"
- "3, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host0\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS=\n"
- "),\n"
- "> -\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 7, GF=\n"
- "LAGS),\n"
- "> +\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 7, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host1\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS=\n"
- "),\n"
- "> -\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 9, GF=\n"
- "LAGS),\n"
- "> +\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 9, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host2\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 10, GFLAG=\n"
- "S),\n"
+ ">  \tGATE(HCLK_EMMC, \"hclk_emmc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),\n"
+ ">  \tGATE(HCLK_NANDC, \"hclk_nandc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host0\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host1\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host2\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),\n"
  ">  \tGATE(0, \"hclk_otg\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),\n"
- "> -\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 13, GFL=\n"
- "AGS),\n"
- "> -\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 14, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_=\n"
- "CON(11), 13, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),\n"
  "\n"
  "same as noc clocks, make arbiter clocks critical instead\n"
  "\n"
- ">  \tGATE(0, \"hclk_peri_noc\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE=\n"
- "_CON(12), 1, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(PCLK_GMAC, \"pclk_gmac\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(11), 5,=\n"
- " GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_peri_noc\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(PCLK_GMAC, \"pclk_gmac\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),\n"
  "> @@ -572,15 +572,15 @@ enum rk3228_plls {\n"
- "> =20\n"
+ ">  \n"
  ">  \t/* PD_GPU */\n"
- ">  \tGATE(0, \"aclk_gpu\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 14, GFLA=\n"
- "GS),\n"
- "> -\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 15, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 15, GFLAGS),\n"
- "> =20\n"
+ ">  \tGATE(0, \"aclk_gpu\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 15, GFLAGS),\n"
+ ">  \n"
  ">  \t/* PD_BUS */\n"
- "> -\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 1, =\n"
- "GFLAGS),\n"
- "> -\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS=\n"
- "),\n"
- "> +\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(8), 1, GFLAGS),\n"
- "> +\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=\n"
- "ON(8), 0, GFLAGS),\n"
- ">  \tGATE(ACLK_DMAC, \"aclk_dmac_bus\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), =\n"
- "2, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_bus_noc\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=\n"
- "ON(10), 1, GFLAGS),\n"
- "> =20\n"
+ "> -\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),\n"
+ "> +\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),\n"
+ ">  \tGATE(ACLK_DMAC, \"aclk_dmac_bus\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_bus_noc\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),\n"
+ ">  \n"
  "> -\tGATE(0, \"hclk_rom\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_rom\", \"hclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8=\n"
- "), 3, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S0_8CH, \"hclk_i2s0_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 7, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S1_8CH, \"hclk_i2s1_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 8, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S2_2CH, \"hclk_i2s2_2ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_rom\", \"hclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S0_8CH, \"hclk_i2s0_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S1_8CH, \"hclk_i2s1_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S2_2CH, \"hclk_i2s2_2ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),\n"
  "> @@ -589,18 +589,18 @@ enum rk3228_plls {\n"
- ">  \tGATE(0, \"hclk_crypto_mst\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 11, GF=\n"
- "LAGS),\n"
- ">  \tGATE(0, \"hclk_crypto_slv\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 12, GF=\n"
- "LAGS),\n"
- "> =20\n"
- "> -\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 4, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 6, GFL=\n"
- "AGS),\n"
- "> -\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(10), 2, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(8), 4, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(8), 6, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(10), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_crypto_mst\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_crypto_slv\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),\n"
+ ">  \n"
+ "> -\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
  "\n"
  "again critical\n"
  "\n"
  "\n"
- "> -\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 13, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 14, GFL=\n"
- "AGS),\n"
- "> +\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(8), 13, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE=\n"
- "_CON(8), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 14, GFLAGS),\n"
  "\n"
  "we do have a general efuse driver, why do these clocks need to be on?\n"
  "\n"
  "\n"
- ">  \tGATE(PCLK_I2C0, \"pclk_i2c0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 15, =\n"
- "GFLAGS),\n"
- ">  \tGATE(PCLK_I2C1, \"pclk_i2c1\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 0, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_I2C2, \"pclk_i2c2\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 1, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_I2C3, \"pclk_i2c3\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 2, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_TIMER, \"pclk_timer0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 4=\n"
- ", GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C0, \"pclk_i2c0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C1, \"pclk_i2c1\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C2, \"pclk_i2c2\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C3, \"pclk_i2c3\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),\n"
+ ">  \tGATE(PCLK_TIMER, \"pclk_timer0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),\n"
  "> -\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CO=\n"
- "N(9), 5, GFLAGS),\n"
- ">  \tGATE(PCLK_SPI0, \"pclk_spi0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 6, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_PWM, \"pclk_rk_pwm\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 7, =\n"
- "GFLAGS),\n"
- ">  \tGATE(PCLK_GPIO0, \"pclk_gpio0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 8,=\n"
- " GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),\n"
+ ">  \tGATE(PCLK_SPI0, \"pclk_spi0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),\n"
+ ">  \tGATE(PCLK_PWM, \"pclk_rk_pwm\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),\n"
+ ">  \tGATE(PCLK_GPIO0, \"pclk_gpio0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),\n"
  "> @@ -616,20 +616,20 @@ enum rk3228_plls {\n"
- ">  \tGATE(0, \"pclk_sgrf\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(=\n"
- "10), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_sgrf\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
  ">  \tGATE(0, \"pclk_sim\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
- "> =20\n"
- "> -\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 3, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 5,=\n"
- " GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(10), 3, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(10), 5, GFLAGS),\n"
- ">  \tGATE(PCLK_HDMI_PHY, \"pclk_hdmiphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_C=\n"
- "ON(10), 7, GFLAGS),\n"
- ">  \tGATE(0, \"pclk_vdacphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 8, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 9, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(10), 9, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"aclk_vpu\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 0, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 4, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(15), 4, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_rkvdec\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 2,=\n"
- " GFLAGS),\n"
- "> -\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15)=\n"
- ", 6, GFLAGS),\n"
- "> +\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928=\n"
- "_CLKGATE_CON(15), 6, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_vpu\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 1, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 5, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(15), 5, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_rkvdec\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 3,=\n"
- " GFLAGS),\n"
- "> -\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15)=\n"
- ", 7, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928=\n"
- "_CLKGATE_CON(15), 7, GFLAGS),\n"
- "> =20\n"
+ ">  \n"
+ "> -\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),\n"
+ ">  \tGATE(PCLK_HDMI_PHY, \"pclk_hdmiphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_vdacphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"aclk_vpu\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_rkvdec\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_vpu\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_rkvdec\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),\n"
+ ">  \n"
  ">  \t/* PD_MMC */\n"
- ">  \tMMC(SCLK_SDMMC_DRV,    \"sdmmc_drv\",    \"sclk_sdmmc\", RK3228_SDMMC_CON0,=\n"
- " 1),\n"
+ ">  \tMMC(SCLK_SDMMC_DRV,    \"sdmmc_drv\",    \"sclk_sdmmc\", RK3228_SDMMC_CON0, 1),\n"
  "> @@ -644,6 +644,8 @@ enum rk3228_plls {\n"
- "> =20\n"
- ">  static const char *const rk3228_critical_clocks[] __initconst =3D {\n"
+ ">  \n"
+ ">  static const char *const rk3228_critical_clocks[] __initconst = {\n"
  ">  \t\"aclk_cpu\",\n"
  "> +\t\"pclk_cpu\",\n"
  "> +\t\"hclk_cpu\",\n"
  ">  \t\"aclk_peri\",\n"
  ">  \t\"hclk_peri\",\n"
  ">  \t\"pclk_peri\",\n"
- ">=20\n"
+ "> \n"
  "\n"
  "\n"
  Heiko
 
-bd06af38e5f948362264255037b2d2902887b444a3b09745fa3d37fa482246b5
+7dcb6a0f552a963e1e0c2e8d7df28da43366df4bf83a87d79351c2d36f382139

diff --git a/a/1.txt b/N2/1.txt
index e950ce7..66ebf47 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -10,17 +10,15 @@ is way safer than using clk_ignore_unused - see rk3399.
 Some highlights down below
 
 
-Am Donnerstag, 16. M=E4rz 2017, 16:44:52 CET schrieb Elaine Zhang:
+Am Donnerstag, 16. M?rz 2017, 16:44:52 CET schrieb Elaine Zhang:
 > set pclk_cpu and hclk_cpu as critical_clocks
->=20
+> 
 > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 > ---
->  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------=
-=2D-----
+>  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------------
 >  1 file changed, 34 insertions(+), 32 deletions(-)
->=20
-> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk=
-=2Drk3228.c
+> 
+> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
 > index db6e5a9e6de6..9f82d089084e 100644
 > --- a/drivers/clk/rockchip/clk-rk3228.c
 > +++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -42,262 +40,164 @@ both not needed if you make pclk_ddrupctl and friends critical
 > @@ -445,7 +445,7 @@ enum rk3228_plls {
 >  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
 >  			&rk3228_spdif_fracmux),
-> =20
+>  
 > -	GATE(0, "jtag", "ext_jtag", 0,
 > +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 >  			RK2928_CLKGATE_CON(1), 3, GFLAGS),
-> =20
+>  
 >  	GATE(0, "sclk_otgphy0", "xin24m", 0,
 > @@ -527,24 +527,24 @@ enum rk3228_plls {
-> =20
+>  
 >  	/* PD_VOP */
->  	GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAG=
-S),
-> -	GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, =
-GFLAGS),
-> +	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 11, GFLAGS),
->  	GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAG=
-S),
-> -	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, G=
-=46LAGS),
-> +	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 9, GFLAGS),
+>  	GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
+> -	GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
+> +	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),
+>  	GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
+> -	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
+> +	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),
 
 please make noc-clocks critical, see rk3399
 
-> =20
->  	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5=
-, GFLAGS),
-> -	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, =
-GFLAGS),
-> +	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 12, GFLAGS),
-> =20
->  	GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GF=
-LAGS),
-> -	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10=
-, GFLAGS),
-> +	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(13), 10, GFLAGS),
-> =20
->  	GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAG=
-S),
->  	GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAG=
-S),
->  	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6=
-, GFLAGS),
-> -	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13),=
- 7, GFLAGS),
-> -	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, G=
-=46LAGS),
-> -	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, =
-GFLAGS),
-> +	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_=
-CLKGATE_CON(13), 7, GFLAGS),
-> +	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 8, GFLAGS),
-> +	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 13, GFLAGS),
->  	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, G=
-=46LAGS),
-> -	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12,=
- GFLAGS),
-> +	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(14), 12, GFLAGS),
+>  
+>  	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
+> -	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
+> +	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),
+>  
+>  	GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
+> -	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
+> +	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 10, GFLAGS),
+>  
+>  	GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
+>  	GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
+>  	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
+> -	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
+> -	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
+> -	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
+> +	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),
+> +	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),
+> +	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),
+>  	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
+> -	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
+> +	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 12, GFLAGS),
 
 I would assume the hdcp-iommu should handle this clock, why does it need
 to be always on?
 
 
->  	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGAT=
-E_CON(14), 6, GFLAGS),
->  	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, G=
-=46LAGS),
->  	GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFL=
-AGS),
+>  	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
+>  	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
+>  	GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
 > @@ -558,13 +558,13 @@ enum rk3228_plls {
->  	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2,=
- GFLAGS),
->  	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), =
-3, GFLAGS),
->  	GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS=
-),
-> -	GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GF=
-LAGS),
-> +	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 7, GFLAGS),
->  	GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS=
-),
-> -	GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GF=
-LAGS),
-> +	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 9, GFLAGS),
->  	GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAG=
-S),
+>  	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
+>  	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
+>  	GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
+> -	GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
+> +	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),
+>  	GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
+> -	GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
+> +	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),
+>  	GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
 >  	GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
-> -	GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFL=
-AGS),
-> -	GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, G=
-=46LAGS),
-> +	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_=
-CON(11), 13, GFLAGS),
-> +	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(11), 14, GFLAGS),
+> -	GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
+> -	GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
+> +	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),
+> +	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),
 
 same as noc clocks, make arbiter clocks critical instead
 
->  	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE=
-_CON(12), 1, GFLAGS),
-> =20
->  	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5,=
- GFLAGS),
+>  	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
+>  
+>  	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
 > @@ -572,15 +572,15 @@ enum rk3228_plls {
-> =20
+>  
 >  	/* PD_GPU */
->  	GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLA=
-GS),
-> -	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, =
-GFLAGS),
-> +	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(13), 15, GFLAGS),
-> =20
+>  	GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
+> -	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+> +	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+>  
 >  	/* PD_BUS */
-> -	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, =
-GFLAGS),
-> -	GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS=
-),
-> +	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(8), 1, GFLAGS),
-> +	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=
-ON(8), 0, GFLAGS),
->  	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), =
-2, GFLAGS),
->  	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=
-ON(10), 1, GFLAGS),
-> =20
+> -	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
+> -	GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
+> +	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),
+> +	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),
+>  	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
+>  	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
+>  
 > -	GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
-> +	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8=
-), 3, GFLAGS),
->  	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 7, GFLAGS),
->  	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 8, GFLAGS),
->  	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(=
-8), 9, GFLAGS),
+> +	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),
+>  	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
+>  	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
+>  	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
 > @@ -589,18 +589,18 @@ enum rk3228_plls {
->  	GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GF=
-LAGS),
->  	GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GF=
-LAGS),
-> =20
-> -	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, G=
-=46LAGS),
-> -	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFL=
-AGS),
-> -	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, =
-GFLAGS),
-> +	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(8), 4, GFLAGS),
-> +	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(8), 6, GFLAGS),
-> +	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKG=
-ATE_CON(10), 2, GFLAGS),
+>  	GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+>  	GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+>  
+> -	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+> -	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+> -	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+> +	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+> +	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+> +	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
 
 again critical
 
 
-> -	GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GF=
-LAGS),
-> -	GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFL=
-AGS),
-> +	GATE(0, "pclk_efuse_1024", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(8), 13, GFLAGS),
-> +	GATE(0, "pclk_efuse_256", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE=
-_CON(8), 14, GFLAGS),
+> -	GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+> -	GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
+> +	GATE(0, "pclk_efuse_1024", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+> +	GATE(0, "pclk_efuse_256", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 14, GFLAGS),
 
 we do have a general efuse driver, why do these clocks need to be on?
 
 
->  	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, =
-GFLAGS),
->  	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, G=
-=46LAGS),
->  	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, G=
-=46LAGS),
->  	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, G=
-=46LAGS),
->  	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4=
-, GFLAGS),
+>  	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
+>  	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
+>  	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
+>  	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
+>  	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
 > -	GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
-> +	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CO=
-N(9), 5, GFLAGS),
->  	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, G=
-=46LAGS),
->  	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, =
-GFLAGS),
->  	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8,=
- GFLAGS),
+> +	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),
+>  	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
+>  	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
+>  	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
 > @@ -616,20 +616,20 @@ enum rk3228_plls {
->  	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(=
-10), 2, GFLAGS),
+>  	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
 >  	GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
-> =20
-> -	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GF=
-LAGS),
-> -	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5,=
- GFLAGS),
-> +	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGAT=
-E_CON(10), 3, GFLAGS),
-> +	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLK=
-GATE_CON(10), 5, GFLAGS),
->  	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_C=
-ON(10), 7, GFLAGS),
->  	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, G=
-=46LAGS),
-> -	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, G=
-=46LAGS),
-> +	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(10), 9, GFLAGS),
-> =20
->  	GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAG=
-S),
-> -	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, G=
-=46LAGS),
-> +	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(15), 4, GFLAGS),
->  	GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2,=
- GFLAGS),
-> -	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15)=
-, 6, GFLAGS),
-> +	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928=
-_CLKGATE_CON(15), 6, GFLAGS),
->  	GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAG=
-S),
-> -	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, G=
-=46LAGS),
-> +	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGA=
-TE_CON(15), 5, GFLAGS),
->  	GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3,=
- GFLAGS),
-> -	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15)=
-, 7, GFLAGS),
-> +	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928=
-_CLKGATE_CON(15), 7, GFLAGS),
-> =20
+>  
+> -	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+> -	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+> +	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+> +	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+>  	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+>  	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
+> -	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+> +	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+>  
+>  	GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
+> -	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
+> +	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),
+>  	GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
+> -	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
+> +	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),
+>  	GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
+> -	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
+> +	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),
+>  	GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
+> -	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
+> +	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),
+>  
 >  	/* PD_MMC */
->  	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0,=
- 1),
+>  	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
 > @@ -644,6 +644,8 @@ enum rk3228_plls {
-> =20
->  static const char *const rk3228_critical_clocks[] __initconst =3D {
+>  
+>  static const char *const rk3228_critical_clocks[] __initconst = {
 >  	"aclk_cpu",
 > +	"pclk_cpu",
 > +	"hclk_cpu",
 >  	"aclk_peri",
 >  	"hclk_peri",
 >  	"pclk_peri",
->=20
+> 
 
 
 Heiko
diff --git a/a/content_digest b/N2/content_digest
index ac738ea..fea07c9 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -1,17 +1,9 @@
  "ref\01489653894-2440-1-git-send-email-zhangqing@rock-chips.com\0"
  "ref\01489653894-2440-3-git-send-email-zhangqing@rock-chips.com\0"
- "From\0Heiko Stuebner <heiko@sntech.de>\0"
- "Subject\0Re: [PATCH v1 2/4] clk: rockchip: rk3228: add CLK_IGNORE_UNUSED flag for some clks\0"
+ "From\0heiko@sntech.de (Heiko Stuebner)\0"
+ "Subject\0[PATCH v1 2/4] clk: rockchip: rk3228: add CLK_IGNORE_UNUSED flag for some clks\0"
  "Date\0Wed, 22 Mar 2017 18:24:04 +0100\0"
- "To\0Elaine Zhang <zhangqing@rock-chips.com>\0"
- "Cc\0mturquette@baylibre.com"
-  sboyd@codeaurora.org
-  linux-clk@vger.kernel.org
-  huangtao@rock-chips.com
-  xxx@rock-chips.com
-  linux-rockchip@lists.infradead.org
-  linux-kernel@vger.kernel.org
- " linux-arm-kernel@lists.infradead.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hi Elaine,\n"
@@ -26,17 +18,15 @@
  "Some highlights down below\n"
  "\n"
  "\n"
- "Am Donnerstag, 16. M=E4rz 2017, 16:44:52 CET schrieb Elaine Zhang:\n"
+ "Am Donnerstag, 16. M?rz 2017, 16:44:52 CET schrieb Elaine Zhang:\n"
  "> set pclk_cpu and hclk_cpu as critical_clocks\n"
- ">=20\n"
+ "> \n"
  "> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>\n"
  "> ---\n"
- ">  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------=\n"
- "=2D-----\n"
+ ">  drivers/clk/rockchip/clk-rk3228.c | 66 ++++++++++++++++++++-------------------\n"
  ">  1 file changed, 34 insertions(+), 32 deletions(-)\n"
- ">=20\n"
- "> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk=\n"
- "=2Drk3228.c\n"
+ "> \n"
+ "> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c\n"
  "> index db6e5a9e6de6..9f82d089084e 100644\n"
  "> --- a/drivers/clk/rockchip/clk-rk3228.c\n"
  "> +++ b/drivers/clk/rockchip/clk-rk3228.c\n"
@@ -58,264 +48,166 @@
  "> @@ -445,7 +445,7 @@ enum rk3228_plls {\n"
  ">  \t\t\tRK2928_CLKGATE_CON(2), 12, GFLAGS,\n"
  ">  \t\t\t&rk3228_spdif_fracmux),\n"
- "> =20\n"
+ ">  \n"
  "> -\tGATE(0, \"jtag\", \"ext_jtag\", 0,\n"
  "> +\tGATE(0, \"jtag\", \"ext_jtag\", CLK_IGNORE_UNUSED,\n"
  ">  \t\t\tRK2928_CLKGATE_CON(1), 3, GFLAGS),\n"
- "> =20\n"
+ ">  \n"
  ">  \tGATE(0, \"sclk_otgphy0\", \"xin24m\", 0,\n"
  "> @@ -527,24 +527,24 @@ enum rk3228_plls {\n"
- "> =20\n"
+ ">  \n"
  ">  \t/* PD_VOP */\n"
- ">  \tGATE(0, \"aclk_rga\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 0, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 11, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 11, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_iep\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 2, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 9, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 9, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_rga\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_rga_noc\", \"aclk_rga_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_iep\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_iep_noc\", \"aclk_iep_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),\n"
  "\n"
  "please make noc-clocks critical, see rk3399\n"
  "\n"
- "> =20\n"
- ">  \tGATE(ACLK_VOP, \"aclk_vop\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 5=\n"
- ", GFLAGS),\n"
- "> -\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 12, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 12, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"aclk_hdcp\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(14), 10, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(13), 10=\n"
- ", GFLAGS),\n"
- "> +\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(13), 10, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"hclk_rga\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 1, GFLAG=\n"
- "S),\n"
- ">  \tGATE(0, \"hclk_iep\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 3, GFLAG=\n"
- "S),\n"
- ">  \tGATE(HCLK_VOP, \"hclk_vop\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 6=\n"
- ", GFLAGS),\n"
- "> -\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13),=\n"
- " 7, GFLAGS),\n"
- "> -\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 8, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 13, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_=\n"
- "CLKGATE_CON(13), 7, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 8, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 13, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 7, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 12,=\n"
- " GFLAGS),\n"
- "> +\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(14), 12, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(ACLK_VOP, \"aclk_vop\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_vop_noc\", \"aclk_vop_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"aclk_hdcp\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_hdcp_noc\", \"aclk_hdcp_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 10, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"hclk_rga\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_iep\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),\n"
+ ">  \tGATE(HCLK_VOP, \"hclk_vop\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vio_ahb_arbi\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vio_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vop_noc\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_hdcp_mmu\", \"hclk_vio_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 12, GFLAGS),\n"
  "\n"
  "I would assume the hdcp-iommu should handle this clock, why does it need\n"
  "to be always on?\n"
  "\n"
  "\n"
- ">  \tGATE(PCLK_HDMI_CTRL, \"pclk_hdmi_ctrl\", \"hclk_vio_pre\", 0, RK2928_CLKGAT=\n"
- "E_CON(14), 6, GFLAGS),\n"
- ">  \tGATE(0, \"pclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 8, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(0, \"pclk_hdcp\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 11, GFL=\n"
- "AGS),\n"
+ ">  \tGATE(PCLK_HDMI_CTRL, \"pclk_hdmi_ctrl\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_vio_h2p\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_hdcp\", \"hclk_vio_pre\", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),\n"
  "> @@ -558,13 +558,13 @@ enum rk3228_plls {\n"
- ">  \tGATE(HCLK_EMMC, \"hclk_emmc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 2,=\n"
- " GFLAGS),\n"
- ">  \tGATE(HCLK_NANDC, \"hclk_nandc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), =\n"
- "3, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host0\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS=\n"
- "),\n"
- "> -\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 7, GF=\n"
- "LAGS),\n"
- "> +\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 7, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host1\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS=\n"
- "),\n"
- "> -\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 9, GF=\n"
- "LAGS),\n"
- "> +\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 9, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_host2\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 10, GFLAG=\n"
- "S),\n"
+ ">  \tGATE(HCLK_EMMC, \"hclk_emmc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),\n"
+ ">  \tGATE(HCLK_NANDC, \"hclk_nandc\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host0\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host0_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host1\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host1_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_host2\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),\n"
  ">  \tGATE(0, \"hclk_otg\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),\n"
- "> -\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 13, GFL=\n"
- "AGS),\n"
- "> -\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 14, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_=\n"
- "CON(11), 13, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(11), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_otg_pmu\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_host2_arb\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),\n"
  "\n"
  "same as noc clocks, make arbiter clocks critical instead\n"
  "\n"
- ">  \tGATE(0, \"hclk_peri_noc\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE=\n"
- "_CON(12), 1, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(PCLK_GMAC, \"pclk_gmac\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(11), 5,=\n"
- " GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_peri_noc\", \"hclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(PCLK_GMAC, \"pclk_gmac\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),\n"
  "> @@ -572,15 +572,15 @@ enum rk3228_plls {\n"
- "> =20\n"
+ ">  \n"
  ">  \t/* PD_GPU */\n"
- ">  \tGATE(0, \"aclk_gpu\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 14, GFLA=\n"
- "GS),\n"
- "> -\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 15, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(13), 15, GFLAGS),\n"
- "> =20\n"
+ ">  \tGATE(0, \"aclk_gpu\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_gpu_noc\", \"aclk_gpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 15, GFLAGS),\n"
+ ">  \n"
  ">  \t/* PD_BUS */\n"
- "> -\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 1, =\n"
- "GFLAGS),\n"
- "> -\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS=\n"
- "),\n"
- "> +\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(8), 1, GFLAGS),\n"
- "> +\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=\n"
- "ON(8), 0, GFLAGS),\n"
- ">  \tGATE(ACLK_DMAC, \"aclk_dmac_bus\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), =\n"
- "2, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_bus_noc\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_C=\n"
- "ON(10), 1, GFLAGS),\n"
- "> =20\n"
+ "> -\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),\n"
+ "> +\tGATE(0, \"sclk_initmem_mbist\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_initmem\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),\n"
+ ">  \tGATE(ACLK_DMAC, \"aclk_dmac_bus\", \"aclk_cpu\", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_bus_noc\", \"aclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),\n"
+ ">  \n"
  "> -\tGATE(0, \"hclk_rom\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_rom\", \"hclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8=\n"
- "), 3, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S0_8CH, \"hclk_i2s0_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 7, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S1_8CH, \"hclk_i2s1_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 8, GFLAGS),\n"
- ">  \tGATE(HCLK_I2S2_2CH, \"hclk_i2s2_2ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(=\n"
- "8), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_rom\", \"hclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S0_8CH, \"hclk_i2s0_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S1_8CH, \"hclk_i2s1_8ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),\n"
+ ">  \tGATE(HCLK_I2S2_2CH, \"hclk_i2s2_2ch\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),\n"
  "> @@ -589,18 +589,18 @@ enum rk3228_plls {\n"
- ">  \tGATE(0, \"hclk_crypto_mst\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 11, GF=\n"
- "LAGS),\n"
- ">  \tGATE(0, \"hclk_crypto_slv\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 12, GF=\n"
- "LAGS),\n"
- "> =20\n"
- "> -\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 4, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 6, GFL=\n"
- "AGS),\n"
- "> -\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(10), 2, =\n"
- "GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(8), 4, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(8), 6, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKG=\n"
- "ATE_CON(10), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_crypto_mst\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_crypto_slv\", \"hclk_cpu\", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),\n"
+ ">  \n"
+ "> -\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrupctl\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrmon\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_msch_noc\", \"pclk_ddr_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
  "\n"
  "again critical\n"
  "\n"
  "\n"
- "> -\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 13, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 14, GFL=\n"
- "AGS),\n"
- "> +\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(8), 13, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE=\n"
- "_CON(8), 14, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_efuse_1024\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 13, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_efuse_256\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 14, GFLAGS),\n"
  "\n"
  "we do have a general efuse driver, why do these clocks need to be on?\n"
  "\n"
  "\n"
- ">  \tGATE(PCLK_I2C0, \"pclk_i2c0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 15, =\n"
- "GFLAGS),\n"
- ">  \tGATE(PCLK_I2C1, \"pclk_i2c1\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 0, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_I2C2, \"pclk_i2c2\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 1, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_I2C3, \"pclk_i2c3\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 2, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_TIMER, \"pclk_timer0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 4=\n"
- ", GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C0, \"pclk_i2c0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C1, \"pclk_i2c1\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C2, \"pclk_i2c2\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),\n"
+ ">  \tGATE(PCLK_I2C3, \"pclk_i2c3\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),\n"
+ ">  \tGATE(PCLK_TIMER, \"pclk_timer0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),\n"
  "> -\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CO=\n"
- "N(9), 5, GFLAGS),\n"
- ">  \tGATE(PCLK_SPI0, \"pclk_spi0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 6, G=\n"
- "=46LAGS),\n"
- ">  \tGATE(PCLK_PWM, \"pclk_rk_pwm\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 7, =\n"
- "GFLAGS),\n"
- ">  \tGATE(PCLK_GPIO0, \"pclk_gpio0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 8,=\n"
- " GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_stimer\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),\n"
+ ">  \tGATE(PCLK_SPI0, \"pclk_spi0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),\n"
+ ">  \tGATE(PCLK_PWM, \"pclk_rk_pwm\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),\n"
+ ">  \tGATE(PCLK_GPIO0, \"pclk_gpio0\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),\n"
  "> @@ -616,20 +616,20 @@ enum rk3228_plls {\n"
- ">  \tGATE(0, \"pclk_sgrf\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(=\n"
- "10), 2, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_sgrf\", \"pclk_cpu\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),\n"
  ">  \tGATE(0, \"pclk_sim\", \"pclk_cpu\", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
- "> =20\n"
- "> -\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 3, GF=\n"
- "LAGS),\n"
- "> -\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 5,=\n"
- " GFLAGS),\n"
- "> +\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGAT=\n"
- "E_CON(10), 3, GFLAGS),\n"
- "> +\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLK=\n"
- "GATE_CON(10), 5, GFLAGS),\n"
- ">  \tGATE(PCLK_HDMI_PHY, \"pclk_hdmiphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_C=\n"
- "ON(10), 7, GFLAGS),\n"
- ">  \tGATE(0, \"pclk_vdacphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 8, G=\n"
- "=46LAGS),\n"
- "> -\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 9, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(10), 9, GFLAGS),\n"
- "> =20\n"
- ">  \tGATE(0, \"aclk_vpu\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 0, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 4, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(15), 4, GFLAGS),\n"
- ">  \tGATE(0, \"aclk_rkvdec\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 2,=\n"
- " GFLAGS),\n"
- "> -\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15)=\n"
- ", 6, GFLAGS),\n"
- "> +\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928=\n"
- "_CLKGATE_CON(15), 6, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_vpu\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 1, GFLAG=\n"
- "S),\n"
- "> -\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 5, G=\n"
- "=46LAGS),\n"
- "> +\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGA=\n"
- "TE_CON(15), 5, GFLAGS),\n"
- ">  \tGATE(0, \"hclk_rkvdec\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 3,=\n"
- " GFLAGS),\n"
- "> -\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15)=\n"
- ", 7, GFLAGS),\n"
- "> +\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928=\n"
- "_CLKGATE_CON(15), 7, GFLAGS),\n"
- "> =20\n"
+ ">  \n"
+ "> -\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_ddrphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_acodecphy\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),\n"
+ ">  \tGATE(PCLK_HDMI_PHY, \"pclk_hdmiphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),\n"
+ ">  \tGATE(0, \"pclk_vdacphy\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),\n"
+ "> -\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),\n"
+ "> +\tGATE(0, \"pclk_phy_noc\", \"pclk_phy_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),\n"
+ ">  \n"
+ ">  \tGATE(0, \"aclk_vpu\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_vpu_noc\", \"aclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),\n"
+ ">  \tGATE(0, \"aclk_rkvdec\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),\n"
+ "> -\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),\n"
+ "> +\tGATE(0, \"aclk_rkvdec_noc\", \"aclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_vpu\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_vpu_noc\", \"hclk_vpu_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),\n"
+ ">  \tGATE(0, \"hclk_rkvdec\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),\n"
+ "> -\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),\n"
+ "> +\tGATE(0, \"hclk_rkvdec_noc\", \"hclk_rkvdec_pre\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),\n"
+ ">  \n"
  ">  \t/* PD_MMC */\n"
- ">  \tMMC(SCLK_SDMMC_DRV,    \"sdmmc_drv\",    \"sclk_sdmmc\", RK3228_SDMMC_CON0,=\n"
- " 1),\n"
+ ">  \tMMC(SCLK_SDMMC_DRV,    \"sdmmc_drv\",    \"sclk_sdmmc\", RK3228_SDMMC_CON0, 1),\n"
  "> @@ -644,6 +644,8 @@ enum rk3228_plls {\n"
- "> =20\n"
- ">  static const char *const rk3228_critical_clocks[] __initconst =3D {\n"
+ ">  \n"
+ ">  static const char *const rk3228_critical_clocks[] __initconst = {\n"
  ">  \t\"aclk_cpu\",\n"
  "> +\t\"pclk_cpu\",\n"
  "> +\t\"hclk_cpu\",\n"
  ">  \t\"aclk_peri\",\n"
  ">  \t\"hclk_peri\",\n"
  ">  \t\"pclk_peri\",\n"
- ">=20\n"
+ "> \n"
  "\n"
  "\n"
  Heiko
 
-bd06af38e5f948362264255037b2d2902887b444a3b09745fa3d37fa482246b5
+1b25e8d0792b1920e1c85a0b0a27df546a2fbe862b434c05a94e7c1a4dac9f9a

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