From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DATE_IN_PAST_06_12, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CFFAC43381 for ; Fri, 19 Feb 2021 06:02:39 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3AD464EC4 for ; Fri, 19 Feb 2021 06:02:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3AD464EC4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 436BF606D2 for ; Fri, 19 Feb 2021 06:02:38 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X6PET3jAP_fP for ; Fri, 19 Feb 2021 06:02:37 +0000 (UTC) Received: by smtp3.osuosl.org (Postfix, from userid 1001) id 00831606CD; Fri, 19 Feb 2021 06:02:36 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by smtp3.osuosl.org (Postfix) with ESMTP id 7D69D605F7; Fri, 19 Feb 2021 06:02:34 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 5FBC9C000E; Fri, 19 Feb 2021 06:02:34 +0000 (UTC) Received: from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133]) by lists.linuxfoundation.org (Postfix) with ESMTP id F30DEC000D for ; Fri, 19 Feb 2021 06:02:30 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id E83B18739D for ; Fri, 19 Feb 2021 06:02:30 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id y1yvFm0XA6bh for ; Fri, 19 Feb 2021 06:02:30 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by hemlock.osuosl.org (Postfix) with ESMTPS id 3F23C872B2 for ; Fri, 19 Feb 2021 06:02:30 +0000 (UTC) IronPort-SDR: ePZ3jTXvinn3DrYoKuSsKsnX30En5vdTRTNDwVmM6zWhyL75h1HwYsViVauit1krjNCaqPDBIq 1IKi2wDj5a7g== X-IronPort-AV: E=McAfee;i="6000,8403,9899"; a="245198111" X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="245198111" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2021 22:02:29 -0800 IronPort-SDR: q5sM8qjyrdiqLebPhYkAic93/sddjrQ8IqEV49ww5JS2AxoW1ah9ipbTfL3+8cWY6Y9uQwbXRG hGCwvhHxQbjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="362829344" Received: from otc-wp-03.jf.intel.com ([10.54.39.79]) by orsmga003.jf.intel.com with ESMTP; 18 Feb 2021 22:02:29 -0800 From: Jacob Pan To: LKML , iommu@lists.linux-foundation.org, Joerg Roedel , "Lu Baolu" Subject: [PATCH 1/4] iommu/vt-d: Enable write protect for supervisor SVM Date: Thu, 18 Feb 2021 13:31:15 -0800 Message-Id: <1613683878-89946-2-git-send-email-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613683878-89946-1-git-send-email-jacob.jun.pan@linux.intel.com> References: <1613683878-89946-1-git-send-email-jacob.jun.pan@linux.intel.com> Cc: "Tian, Kevin" , Dave Jiang , Raj Ashok , Sanjay Kumar , Yi Sun , Jean-Philippe Brucker , Wu Hao X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Write protect bit, when set, inhibits supervisor writes to the read-only pages. In supervisor shared virtual addressing (SVA), where page tables are shared between CPU and DMA, IOMMU PASID entry WPE bit should match CR0.WP bit in the CPU. This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. Signed-off-by: Sanjay Kumar Signed-off-by: Jacob Pan --- drivers/iommu/intel/pasid.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 0cceaabc3ce6..0b7e0e726ade 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -410,6 +410,15 @@ static inline void pasid_set_sre(struct pasid_entry *pe) pasid_set_bits(&pe->val[2], 1 << 0, 1); } +/* + * Setup the WPE(Write Protect Enable) field (Bit 132) of a + * scalable mode PASID entry. + */ +static inline void pasid_set_wpe(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4); +} + /* * Setup the P(Present) field (Bit 0) of a scalable mode PASID * entry. @@ -553,6 +562,20 @@ static void pasid_flush_caches(struct intel_iommu *iommu, } } +static inline int pasid_enable_wpe(struct pasid_entry *pte) +{ + unsigned long cr0 = read_cr0(); + + /* CR0.WP is normally set but just to be sure */ + if (unlikely(!(cr0 & X86_CR0_WP))) { + pr_err_ratelimited("No CPU write protect!\n"); + return -EINVAL; + } + pasid_set_wpe(pte); + + return 0; +}; + /* * Set up the scalable mode pasid table entry for first only * translation type. @@ -584,6 +607,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, return -EINVAL; } pasid_set_sre(pte); + if (pasid_enable_wpe(pte)) + return -EINVAL; + } if (flags & PASID_FLAG_FL5LP) { -- 2.25.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DATE_IN_PAST_06_12, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F82C433E0 for ; Fri, 19 Feb 2021 06:06:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23FA464EC0 for ; Fri, 19 Feb 2021 06:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229707AbhBSGGI (ORCPT ); Fri, 19 Feb 2021 01:06:08 -0500 Received: from mga18.intel.com ([134.134.136.126]:39881 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbhBSGGE (ORCPT ); Fri, 19 Feb 2021 01:06:04 -0500 IronPort-SDR: ItsY0Gv6F3p0OVIIWgZSFZEKA9J6EUy7LSsyNa8+RuR2m7s5zINXVHZv6vE6IQZs9ROqFRDD5o eAvCwyBoDlcg== X-IronPort-AV: E=McAfee;i="6000,8403,9899"; a="171424152" X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="171424152" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2021 22:02:29 -0800 IronPort-SDR: q5sM8qjyrdiqLebPhYkAic93/sddjrQ8IqEV49ww5JS2AxoW1ah9ipbTfL3+8cWY6Y9uQwbXRG hGCwvhHxQbjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="362829344" Received: from otc-wp-03.jf.intel.com ([10.54.39.79]) by orsmga003.jf.intel.com with ESMTP; 18 Feb 2021 22:02:29 -0800 From: Jacob Pan To: LKML , iommu@lists.linux-foundation.org, Joerg Roedel , "Lu Baolu" Cc: Yi Liu , Raj Ashok , "Tian, Kevin" , Wu Hao , Yi Sun , Dave Jiang , Eric Auger , Jean-Philippe Brucker , Jacob Pan , Sanjay Kumar Subject: [PATCH 1/4] iommu/vt-d: Enable write protect for supervisor SVM Date: Thu, 18 Feb 2021 13:31:15 -0800 Message-Id: <1613683878-89946-2-git-send-email-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613683878-89946-1-git-send-email-jacob.jun.pan@linux.intel.com> References: <1613683878-89946-1-git-send-email-jacob.jun.pan@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Write protect bit, when set, inhibits supervisor writes to the read-only pages. In supervisor shared virtual addressing (SVA), where page tables are shared between CPU and DMA, IOMMU PASID entry WPE bit should match CR0.WP bit in the CPU. This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. Signed-off-by: Sanjay Kumar Signed-off-by: Jacob Pan --- drivers/iommu/intel/pasid.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 0cceaabc3ce6..0b7e0e726ade 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -410,6 +410,15 @@ static inline void pasid_set_sre(struct pasid_entry *pe) pasid_set_bits(&pe->val[2], 1 << 0, 1); } +/* + * Setup the WPE(Write Protect Enable) field (Bit 132) of a + * scalable mode PASID entry. + */ +static inline void pasid_set_wpe(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4); +} + /* * Setup the P(Present) field (Bit 0) of a scalable mode PASID * entry. @@ -553,6 +562,20 @@ static void pasid_flush_caches(struct intel_iommu *iommu, } } +static inline int pasid_enable_wpe(struct pasid_entry *pte) +{ + unsigned long cr0 = read_cr0(); + + /* CR0.WP is normally set but just to be sure */ + if (unlikely(!(cr0 & X86_CR0_WP))) { + pr_err_ratelimited("No CPU write protect!\n"); + return -EINVAL; + } + pasid_set_wpe(pte); + + return 0; +}; + /* * Set up the scalable mode pasid table entry for first only * translation type. @@ -584,6 +607,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, return -EINVAL; } pasid_set_sre(pte); + if (pasid_enable_wpe(pte)) + return -EINVAL; + } if (flags & PASID_FLAG_FL5LP) { -- 2.25.1